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7d393aed WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
7d393aed WD |
6 | * |
7 | * TODO: clean-up | |
8 | */ | |
9 | ||
10 | #include <common.h> | |
11 | #include "pip405.h" | |
12 | #include <asm/processor.h> | |
13 | #include <i2c.h> | |
28c34504 | 14 | #include <stdio_dev.h> |
7d393aed WD |
15 | #include "../common/isa.h" |
16 | #include "../common/common_util.h" | |
17 | ||
d87080b7 WD |
18 | DECLARE_GLOBAL_DATA_PTR; |
19 | ||
7d393aed WD |
20 | #undef SDRAM_DEBUG |
21 | ||
7d393aed WD |
22 | /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ |
23 | #ifndef __ldiv_t_defined | |
24 | typedef struct { | |
25 | long int quot; /* Quotient */ | |
26 | long int rem; /* Remainder */ | |
27 | } ldiv_t; | |
28 | extern ldiv_t ldiv (long int __numer, long int __denom); | |
29 | ||
30 | # define __ldiv_t_defined 1 | |
31 | #endif | |
32 | ||
33 | ||
34 | typedef enum { | |
35 | SDRAM_NO_ERR, | |
36 | SDRAM_SPD_COMM_ERR, | |
37 | SDRAM_SPD_CHKSUM_ERR, | |
38 | SDRAM_UNSUPPORTED_ERR, | |
39 | SDRAM_UNKNOWN_ERR | |
40 | } SDRAM_ERR; | |
41 | ||
42 | typedef struct { | |
43 | const unsigned char mode; | |
44 | const unsigned char row; | |
45 | const unsigned char col; | |
46 | const unsigned char bank; | |
47 | } SDRAM_SETUP; | |
48 | ||
49 | static const SDRAM_SETUP sdram_setup_table[] = { | |
50 | {1, 11, 9, 2}, | |
51 | {1, 11, 10, 2}, | |
52 | {2, 12, 9, 4}, | |
53 | {2, 12, 10, 4}, | |
54 | {3, 13, 9, 4}, | |
55 | {3, 13, 10, 4}, | |
56 | {3, 13, 11, 4}, | |
57 | {4, 12, 8, 2}, | |
58 | {4, 12, 8, 4}, | |
59 | {5, 11, 8, 2}, | |
60 | {5, 11, 8, 4}, | |
61 | {6, 13, 8, 2}, | |
62 | {6, 13, 8, 4}, | |
63 | {7, 13, 9, 2}, | |
64 | {7, 13, 10, 2}, | |
65 | {0, 0, 0, 0} | |
66 | }; | |
67 | ||
68 | static const unsigned char cal_indextable[] = { | |
69 | 9, 23, 25 | |
70 | }; | |
71 | ||
72 | ||
73 | /* | |
74 | * translate ns.ns/10 coding of SPD timing values | |
75 | * into 10 ps unit values | |
76 | */ | |
77 | ||
78 | unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version) | |
79 | { | |
80 | unsigned short ns, ns10; | |
81 | ||
82 | /* isolate upper nibble */ | |
83 | ns = (spd_byte >> 4) & 0x0F; | |
84 | /* isolate lower nibble */ | |
85 | ns10 = (spd_byte & 0x0F); | |
86 | ||
87 | return (ns * 100 + ns10 * 10); | |
88 | } | |
89 | ||
90 | /* | |
91 | * translate ns.ns/4 coding of SPD timing values | |
92 | * into 10 ps unit values | |
93 | */ | |
94 | ||
95 | unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version) | |
96 | { | |
97 | unsigned short ns, ns4; | |
98 | ||
99 | /* isolate upper 6 bits */ | |
100 | ns = (spd_byte >> 2) & 0x3F; | |
101 | /* isloate lower 2 bits */ | |
102 | ns4 = (spd_byte & 0x03); | |
103 | ||
104 | return (ns * 100 + ns4 * 25); | |
105 | } | |
106 | ||
107 | /* | |
108 | * translate ns coding of SPD timing values | |
109 | * into 10 ps unit values | |
110 | */ | |
111 | ||
112 | unsigned short NSto10PS (unsigned char spd_byte) | |
113 | { | |
114 | return (spd_byte * 100); | |
115 | } | |
116 | ||
117 | void SDRAM_err (const char *s) | |
118 | { | |
119 | #ifndef SDRAM_DEBUG | |
7d393aed WD |
120 | (void) get_clocks (); |
121 | gd->baudrate = 9600; | |
122 | serial_init (); | |
123 | #endif | |
124 | serial_puts ("\n"); | |
125 | serial_puts (s); | |
126 | serial_puts ("\n enable SDRAM_DEBUG for more info\n"); | |
127 | for (;;); | |
128 | } | |
129 | ||
130 | ||
131 | #ifdef SDRAM_DEBUG | |
132 | ||
133 | void write_hex (unsigned char i) | |
134 | { | |
135 | char cc; | |
136 | ||
137 | cc = i >> 4; | |
138 | cc &= 0xf; | |
139 | if (cc > 9) | |
140 | serial_putc (cc + 55); | |
141 | else | |
142 | serial_putc (cc + 48); | |
143 | cc = i & 0xf; | |
144 | if (cc > 9) | |
145 | serial_putc (cc + 55); | |
146 | else | |
147 | serial_putc (cc + 48); | |
148 | } | |
149 | ||
150 | void write_4hex (unsigned long val) | |
151 | { | |
152 | write_hex ((unsigned char) (val >> 24)); | |
153 | write_hex ((unsigned char) (val >> 16)); | |
154 | write_hex ((unsigned char) (val >> 8)); | |
155 | write_hex ((unsigned char) val); | |
156 | } | |
157 | ||
158 | #endif | |
159 | ||
c837dcb1 | 160 | int board_early_init_f (void) |
7d393aed | 161 | { |
7d393aed | 162 | unsigned char datain[128]; |
77ddac94 | 163 | unsigned long sdram_size = 0; |
7d393aed WD |
164 | SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; |
165 | unsigned long memclk; | |
166 | unsigned long tmemclk = 0; | |
167 | unsigned long tmp, bank, baseaddr, bank_size; | |
168 | unsigned short i; | |
169 | unsigned char rows, cols, banks, sdram_banks, density; | |
170 | unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, | |
4e11c351 | 171 | trc_clocks; |
7d393aed WD |
172 | unsigned char cal_index, cal_val, spd_version, spd_chksum; |
173 | unsigned char buf[8]; | |
4e11c351 SR |
174 | #ifdef SDRAM_DEBUG |
175 | unsigned char tctp_clocks; | |
176 | #endif | |
177 | ||
7205e407 | 178 | /* set up the config port */ |
d1c3b275 SR |
179 | mtdcr (EBC0_CFGADDR, PB7AP); |
180 | mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); | |
181 | mtdcr (EBC0_CFGADDR, PB7CR); | |
182 | mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR); | |
7d393aed WD |
183 | |
184 | memclk = get_bus_freq (tmemclk); | |
185 | tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ | |
186 | ||
187 | #ifdef SDRAM_DEBUG | |
188 | (void) get_clocks (); | |
189 | gd->baudrate = 9600; | |
190 | serial_init (); | |
191 | serial_puts ("\nstart SDRAM Setup\n"); | |
192 | #endif | |
193 | ||
194 | /* Read Serial Presence Detect Information */ | |
880540de | 195 | i2c_set_bus_num(0); |
7d393aed WD |
196 | for (i = 0; i < 128; i++) |
197 | datain[i] = 127; | |
198 | i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); | |
199 | #ifdef SDRAM_DEBUG | |
200 | serial_puts ("\ni2c_read returns "); | |
201 | write_hex (i); | |
202 | serial_puts ("\n"); | |
203 | #endif | |
204 | ||
205 | #ifdef SDRAM_DEBUG | |
206 | for (i = 0; i < 128; i++) { | |
207 | write_hex (datain[i]); | |
208 | serial_puts (" "); | |
209 | if (((i + 1) % 16) == 0) | |
210 | serial_puts ("\n"); | |
211 | } | |
212 | serial_puts ("\n"); | |
213 | #endif | |
214 | spd_chksum = 0; | |
215 | for (i = 0; i < 63; i++) { | |
216 | spd_chksum += datain[i]; | |
217 | } /* endfor */ | |
218 | if (datain[63] != spd_chksum) { | |
219 | #ifdef SDRAM_DEBUG | |
220 | serial_puts ("SPD chksum: 0x"); | |
221 | write_hex (datain[63]); | |
222 | serial_puts (" != calc. chksum: 0x"); | |
223 | write_hex (spd_chksum); | |
224 | serial_puts ("\n"); | |
225 | #endif | |
226 | SDRAM_err ("SPD checksum Error"); | |
227 | } | |
228 | /* SPD seems to be ok, use it */ | |
229 | ||
230 | /* get SPD version */ | |
231 | spd_version = datain[62]; | |
232 | ||
233 | /* do some sanity checks on the kind of RAM */ | |
234 | if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */ | |
235 | (datain[2] != 0x04) || /* if not SDRAM */ | |
236 | (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ | |
237 | (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ | |
8ed44d91 | 238 | (datain[126] == 0x66)) /* or a 66MHz modules */ |
7d393aed WD |
239 | SDRAM_err ("unsupported SDRAM"); |
240 | #ifdef SDRAM_DEBUG | |
241 | serial_puts ("SDRAM sanity ok\n"); | |
242 | #endif | |
243 | ||
244 | /* get number of rows/cols/banks out of byte 3+4+5 */ | |
245 | rows = datain[3]; | |
246 | cols = datain[4]; | |
247 | banks = datain[5]; | |
248 | ||
249 | /* get number of SDRAM banks out of byte 17 and | |
250 | supported CAS latencies out of byte 18 */ | |
251 | sdram_banks = datain[17]; | |
252 | supported_cal = datain[18] & ~0x81; | |
253 | ||
254 | while (t->mode != 0) { | |
255 | if ((t->row == rows) && (t->col == cols) | |
256 | && (t->bank == sdram_banks)) | |
257 | break; | |
258 | t++; | |
259 | } /* endwhile */ | |
260 | ||
261 | #ifdef SDRAM_DEBUG | |
262 | serial_puts ("rows: "); | |
263 | write_hex (rows); | |
264 | serial_puts (" cols: "); | |
265 | write_hex (cols); | |
266 | serial_puts (" banks: "); | |
267 | write_hex (banks); | |
268 | serial_puts (" mode: "); | |
269 | write_hex (t->mode); | |
270 | serial_puts ("\n"); | |
271 | #endif | |
272 | if (t->mode == 0) | |
273 | SDRAM_err ("unsupported SDRAM"); | |
274 | /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */ | |
275 | #ifdef SDRAM_DEBUG | |
276 | serial_puts ("tRP: "); | |
277 | write_hex (datain[27]); | |
278 | serial_puts ("\ntRCD: "); | |
279 | write_hex (datain[29]); | |
280 | serial_puts ("\ntRAS: "); | |
281 | write_hex (datain[30]); | |
282 | serial_puts ("\n"); | |
283 | #endif | |
284 | ||
285 | trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk; | |
286 | trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk; | |
287 | tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk; | |
288 | density = datain[31]; | |
289 | ||
290 | /* trc_clocks is sum of trp_clocks + tras_clocks */ | |
291 | trc_clocks = trp_clocks + tras_clocks; | |
4e11c351 SR |
292 | |
293 | #ifdef SDRAM_DEBUG | |
7d393aed WD |
294 | /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ |
295 | tctp_clocks = | |
296 | ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + | |
297 | (tmemclk - 1)) / tmemclk; | |
298 | ||
7d393aed WD |
299 | serial_puts ("c_RP: "); |
300 | write_hex (trp_clocks); | |
301 | serial_puts ("\nc_RCD: "); | |
302 | write_hex (trcd_clocks); | |
303 | serial_puts ("\nc_RAS: "); | |
304 | write_hex (tras_clocks); | |
305 | serial_puts ("\nc_RC: (RP+RAS): "); | |
306 | write_hex (trc_clocks); | |
307 | serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): "); | |
308 | write_hex (tctp_clocks); | |
309 | serial_puts ("\nt_CTP: RAS - RCD: "); | |
310 | write_hex ((unsigned | |
311 | char) ((NSto10PS (datain[30]) - | |
312 | NSto10PS (datain[29])) >> 8)); | |
313 | write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29]))); | |
314 | serial_puts ("\ntmemclk: "); | |
315 | write_hex ((unsigned char) (tmemclk >> 8)); | |
316 | write_hex ((unsigned char) (tmemclk)); | |
317 | serial_puts ("\n"); | |
318 | #endif | |
319 | ||
320 | ||
321 | cal_val = 255; | |
322 | for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) { | |
323 | /* is this CAS latency supported ? */ | |
324 | if ((supported_cal >> i) & 0x01) { | |
325 | buf[0] = datain[cal_indextable[cal_index]]; | |
326 | if (cal_index < 2) { | |
327 | if (NS10to10PS (buf[0], spd_version) <= tmemclk) | |
328 | cal_val = i; | |
329 | } else { | |
330 | /* SPD bytes 25+26 have another format */ | |
331 | if (NS4to10PS (buf[0], spd_version) <= tmemclk) | |
332 | cal_val = i; | |
333 | } /* endif */ | |
334 | cal_index++; | |
335 | } /* endif */ | |
336 | } /* endfor */ | |
337 | #ifdef SDRAM_DEBUG | |
338 | serial_puts ("CAL: "); | |
339 | write_hex (cal_val + 1); | |
340 | serial_puts ("\n"); | |
341 | #endif | |
342 | ||
343 | if (cal_val == 255) | |
344 | SDRAM_err ("unsupported SDRAM"); | |
345 | ||
346 | /* get SDRAM timing register */ | |
95b602ba | 347 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
d1c3b275 | 348 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; |
7d393aed WD |
349 | /* insert CASL value */ |
350 | /* tmp |= ((unsigned long)cal_val) << 23; */ | |
351 | tmp |= ((unsigned long) cal_val) << 23; | |
352 | /* insert PTA value */ | |
353 | tmp |= ((unsigned long) (trp_clocks - 1)) << 18; | |
354 | /* insert CTP value */ | |
355 | /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */ | |
356 | tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16; | |
357 | /* insert LDF (always 01) */ | |
358 | tmp |= ((unsigned long) 0x01) << 14; | |
359 | /* insert RFTA value */ | |
360 | tmp |= ((unsigned long) (trc_clocks - 4)) << 2; | |
361 | /* insert RCD value */ | |
362 | tmp |= ((unsigned long) (trcd_clocks - 1)) << 0; | |
363 | ||
364 | #ifdef SDRAM_DEBUG | |
365 | serial_puts ("sdtr: "); | |
366 | write_4hex (tmp); | |
367 | serial_puts ("\n"); | |
368 | #endif | |
369 | ||
370 | /* write SDRAM timing register */ | |
95b602ba | 371 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
d1c3b275 | 372 | mtdcr (SDRAM0_CFGDATA, tmp); |
6d0f6bcf | 373 | baseaddr = CONFIG_SYS_SDRAM_BASE; |
7d393aed WD |
374 | bank_size = (((unsigned long) density) << 22) / 2; |
375 | /* insert AM value */ | |
376 | tmp = ((unsigned long) t->mode - 1) << 13; | |
377 | /* insert SZ value; */ | |
378 | switch (bank_size) { | |
379 | case 0x00400000: | |
380 | tmp |= ((unsigned long) 0x00) << 17; | |
381 | break; | |
382 | case 0x00800000: | |
383 | tmp |= ((unsigned long) 0x01) << 17; | |
384 | break; | |
385 | case 0x01000000: | |
386 | tmp |= ((unsigned long) 0x02) << 17; | |
387 | break; | |
388 | case 0x02000000: | |
389 | tmp |= ((unsigned long) 0x03) << 17; | |
390 | break; | |
391 | case 0x04000000: | |
392 | tmp |= ((unsigned long) 0x04) << 17; | |
393 | break; | |
394 | case 0x08000000: | |
395 | tmp |= ((unsigned long) 0x05) << 17; | |
396 | break; | |
397 | case 0x10000000: | |
398 | tmp |= ((unsigned long) 0x06) << 17; | |
399 | break; | |
400 | default: | |
401 | SDRAM_err ("unsupported SDRAM"); | |
402 | } /* endswitch */ | |
403 | /* get SDRAM bank 0 register */ | |
95b602ba | 404 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 405 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
7d393aed WD |
406 | bank |= (baseaddr | tmp | 0x01); |
407 | #ifdef SDRAM_DEBUG | |
408 | serial_puts ("bank0: baseaddr: "); | |
409 | write_4hex (baseaddr); | |
410 | serial_puts (" banksize: "); | |
411 | write_4hex (bank_size); | |
412 | serial_puts (" mb0cf: "); | |
413 | write_4hex (bank); | |
414 | serial_puts ("\n"); | |
415 | #endif | |
416 | baseaddr += bank_size; | |
417 | sdram_size += bank_size; | |
418 | ||
419 | /* write SDRAM bank 0 register */ | |
95b602ba | 420 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 421 | mtdcr (SDRAM0_CFGDATA, bank); |
7d393aed WD |
422 | |
423 | /* get SDRAM bank 1 register */ | |
95b602ba | 424 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 425 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
7d393aed WD |
426 | sdram_size = 0; |
427 | ||
428 | #ifdef SDRAM_DEBUG | |
429 | serial_puts ("bank1: baseaddr: "); | |
430 | write_4hex (baseaddr); | |
431 | serial_puts (" banksize: "); | |
432 | write_4hex (bank_size); | |
433 | #endif | |
434 | if (banks == 2) { | |
435 | bank |= (baseaddr | tmp | 0x01); | |
436 | baseaddr += bank_size; | |
437 | sdram_size += bank_size; | |
438 | } /* endif */ | |
439 | #ifdef SDRAM_DEBUG | |
440 | serial_puts (" mb1cf: "); | |
441 | write_4hex (bank); | |
442 | serial_puts ("\n"); | |
443 | #endif | |
444 | /* write SDRAM bank 1 register */ | |
95b602ba | 445 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 446 | mtdcr (SDRAM0_CFGDATA, bank); |
7d393aed WD |
447 | |
448 | /* get SDRAM bank 2 register */ | |
95b602ba | 449 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
d1c3b275 | 450 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
7d393aed WD |
451 | |
452 | bank |= (baseaddr | tmp | 0x01); | |
453 | ||
454 | #ifdef SDRAM_DEBUG | |
455 | serial_puts ("bank2: baseaddr: "); | |
456 | write_4hex (baseaddr); | |
457 | serial_puts (" banksize: "); | |
458 | write_4hex (bank_size); | |
459 | serial_puts (" mb2cf: "); | |
460 | write_4hex (bank); | |
461 | serial_puts ("\n"); | |
462 | #endif | |
463 | ||
464 | baseaddr += bank_size; | |
465 | sdram_size += bank_size; | |
466 | ||
467 | /* write SDRAM bank 2 register */ | |
95b602ba | 468 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
d1c3b275 | 469 | mtdcr (SDRAM0_CFGDATA, bank); |
7d393aed WD |
470 | |
471 | /* get SDRAM bank 3 register */ | |
95b602ba | 472 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
d1c3b275 | 473 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
7d393aed WD |
474 | |
475 | #ifdef SDRAM_DEBUG | |
476 | serial_puts ("bank3: baseaddr: "); | |
477 | write_4hex (baseaddr); | |
478 | serial_puts (" banksize: "); | |
479 | write_4hex (bank_size); | |
480 | #endif | |
481 | ||
482 | if (banks == 2) { | |
483 | bank |= (baseaddr | tmp | 0x01); | |
484 | baseaddr += bank_size; | |
485 | sdram_size += bank_size; | |
486 | } | |
487 | /* endif */ | |
488 | #ifdef SDRAM_DEBUG | |
489 | serial_puts (" mb3cf: "); | |
490 | write_4hex (bank); | |
491 | serial_puts ("\n"); | |
492 | #endif | |
493 | ||
494 | /* write SDRAM bank 3 register */ | |
95b602ba | 495 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
d1c3b275 | 496 | mtdcr (SDRAM0_CFGDATA, bank); |
7d393aed WD |
497 | |
498 | ||
499 | /* get SDRAM refresh interval register */ | |
95b602ba | 500 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 501 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; |
7d393aed WD |
502 | |
503 | if (tmemclk < NSto10PS (16)) | |
504 | tmp |= 0x05F00000; | |
505 | else | |
506 | tmp |= 0x03F80000; | |
507 | ||
508 | /* write SDRAM refresh interval register */ | |
95b602ba | 509 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 510 | mtdcr (SDRAM0_CFGDATA, tmp); |
7d393aed WD |
511 | |
512 | /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ | |
95b602ba | 513 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 514 | tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; |
95b602ba | 515 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 516 | mtdcr (SDRAM0_CFGDATA, tmp); |
7d393aed WD |
517 | |
518 | ||
7d393aed WD |
519 | /*-------------------------------------------------------------------------+ |
520 | | Interrupt controller setup for the PIP405 board. | |
521 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
522 | | IRQ 16 405GP internally generated; active low; level sensitive | |
523 | | IRQ 17-24 RESERVED | |
524 | | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive | |
525 | | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive | |
526 | | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive | |
527 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
528 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
529 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
530 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
531 | | Note for PIP405 board: | |
532 | | An interrupt taken for the SouthBridge (IRQ 25) indicates that | |
533 | | the Interrupt Controller in the South Bridge has caused the | |
534 | | interrupt. The IC must be read to determine which device | |
535 | | caused the interrupt. | |
536 | | | |
537 | +-------------------------------------------------------------------------*/ | |
952e7760 SR |
538 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
539 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ | |
540 | mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ | |
541 | mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
542 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ | |
543 | mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
544 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
7d393aed WD |
545 | |
546 | return 0; | |
547 | } | |
548 | ||
21be309b DM |
549 | int board_early_init_r(void) |
550 | { | |
551 | int mode; | |
552 | ||
553 | /* | |
554 | * since we are relocated, we can finally enable i-cache | |
555 | * and set up the flash CS correctly | |
556 | */ | |
557 | icache_enable(); | |
558 | setup_cs_reloc(); | |
559 | /* get and display boot mode */ | |
560 | mode = get_boot_mode(); | |
561 | if (mode & BOOT_PCI) | |
562 | printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? | |
563 | "MPS" : "Flash"); | |
564 | else | |
565 | printf("%s Boot\n", (mode & BOOT_MPS) ? | |
566 | "MPS" : "Flash"); | |
7d393aed | 567 | |
21be309b DM |
568 | return 0; |
569 | } | |
7d393aed WD |
570 | /* ------------------------------------------------------------------------- */ |
571 | ||
572 | /* | |
573 | * Check Board Identity: | |
574 | */ | |
575 | ||
576 | int checkboard (void) | |
577 | { | |
77ddac94 | 578 | char s[50]; |
7d393aed WD |
579 | unsigned char bc; |
580 | int i; | |
581 | backup_t *b = (backup_t *) s; | |
582 | ||
583 | puts ("Board: "); | |
584 | ||
cdb74977 | 585 | i = getenv_f("serial#", (char *)s, 32); |
77ddac94 | 586 | if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { |
7d393aed WD |
587 | get_backup_values (b); |
588 | if (strncmp (b->signature, "MPL\0", 4) != 0) { | |
589 | puts ("### No HW ID - assuming PIP405"); | |
590 | } else { | |
591 | b->serial_name[6] = 0; | |
592 | printf ("%s SN: %s", b->serial_name, | |
593 | &b->serial_name[7]); | |
594 | } | |
595 | } else { | |
596 | s[6] = 0; | |
597 | printf ("%s SN: %s", s, &s[7]); | |
598 | } | |
599 | bc = in8 (CONFIG_PORT_ADDR); | |
600 | printf (" Boot Config: 0x%x\n", bc); | |
601 | return (0); | |
602 | } | |
603 | ||
604 | ||
605 | /* ------------------------------------------------------------------------- */ | |
606 | /* ------------------------------------------------------------------------- */ | |
607 | /* | |
f1683aa7 | 608 | dram_init() reads EEPROM via I2c. EEPROM contains all of |
7d393aed WD |
609 | the necessary info for SDRAM controller configuration |
610 | */ | |
611 | /* ------------------------------------------------------------------------- */ | |
612 | /* ------------------------------------------------------------------------- */ | |
613 | static int test_dram (unsigned long ramsize); | |
614 | ||
f1683aa7 | 615 | int dram_init(void) |
7d393aed | 616 | { |
7d393aed WD |
617 | unsigned long bank_reg[4], tmp, bank_size; |
618 | int i, ds; | |
619 | unsigned long TotalSize; | |
620 | ||
621 | ds = 0; | |
622 | /* since the DRAM controller is allready set up, | |
623 | * calculate the size with the bank registers | |
624 | */ | |
95b602ba | 625 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 626 | bank_reg[0] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 627 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 628 | bank_reg[1] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 629 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
d1c3b275 | 630 | bank_reg[2] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 631 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
d1c3b275 | 632 | bank_reg[3] = mfdcr (SDRAM0_CFGDATA); |
7d393aed WD |
633 | TotalSize = 0; |
634 | for (i = 0; i < 4; i++) { | |
635 | if ((bank_reg[i] & 0x1) == 0x1) { | |
636 | tmp = (bank_reg[i] >> 17) & 0x7; | |
637 | bank_size = 4 << tmp; | |
638 | TotalSize += bank_size; | |
639 | } else | |
640 | ds = 1; | |
641 | } | |
642 | if (ds == 1) | |
643 | printf ("single-sided DIMM "); | |
644 | else | |
645 | printf ("double-sided DIMM "); | |
646 | test_dram (TotalSize * 1024 * 1024); | |
647 | /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */ | |
648 | (void) get_clocks(); | |
649 | if (gd->cpu_clk > 220000000) | |
650 | TotalSize /= 2; | |
088454cd SG |
651 | gd->ram_size = TotalSize * 1024 * 1024; |
652 | ||
653 | return 0; | |
7d393aed WD |
654 | } |
655 | ||
656 | /* ------------------------------------------------------------------------- */ | |
657 | ||
658 | ||
659 | static int test_dram (unsigned long ramsize) | |
660 | { | |
661 | /* not yet implemented */ | |
662 | return (1); | |
663 | } | |
664 | ||
7d393aed WD |
665 | int misc_init_r (void) |
666 | { | |
7205e407 WD |
667 | /* adjust flash start and size as well as the offset */ |
668 | gd->bd->bi_flashstart=0-flash_info[0].size; | |
6d0f6bcf | 669 | gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; |
7205e407 WD |
670 | gd->bd->bi_flashoffset=0; |
671 | ||
672 | /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ | |
d1c3b275 | 673 | if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) |
58ea142f | 674 | mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); |
7205e407 | 675 | |
7d393aed WD |
676 | return (0); |
677 | } | |
678 | ||
679 | /*************************************************************************** | |
680 | * some helping routines | |
681 | */ | |
682 | ||
683 | int overwrite_console (void) | |
684 | { | |
472d5460 YS |
685 | /* return true if console should be overwritten */ |
686 | return in8(CONFIG_PORT_ADDR) & 0x1; | |
7d393aed WD |
687 | } |
688 | ||
689 | ||
7d393aed WD |
690 | extern int isa_init (void); |
691 | ||
692 | ||
693 | void print_pip405_rev (void) | |
694 | { | |
695 | unsigned char part, vers, cfg; | |
696 | ||
697 | part = in8 (PLD_PART_REG); | |
698 | vers = in8 (PLD_VERS_REG); | |
699 | cfg = in8 (PLD_BOARD_CFG_REG); | |
700 | printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n", | |
701 | 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf, | |
702 | vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf); | |
703 | } | |
704 | ||
705 | extern void check_env(void); | |
706 | ||
707 | ||
708 | int last_stage_init (void) | |
709 | { | |
710 | print_pip405_rev (); | |
711 | isa_init (); | |
28c34504 | 712 | stdio_print_current_devices (); |
7d393aed WD |
713 | check_env(); |
714 | return 0; | |
715 | } | |
716 | ||
717 | /************************************************************************ | |
718 | * Print PIP405 Info | |
719 | ************************************************************************/ | |
720 | void print_pip405_info (void) | |
721 | { | |
722 | unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr, | |
723 | compwr, nicvga, scsirst; | |
724 | ||
725 | part = in8 (PLD_PART_REG); | |
726 | vers = in8 (PLD_VERS_REG); | |
727 | cfg = in8 (PLD_BOARD_CFG_REG); | |
728 | ledu = in8 (PLD_LED_USER_REG); | |
729 | sysman = in8 (PLD_SYS_MAN_REG); | |
730 | flashcom = in8 (PLD_FLASH_COM_REG); | |
731 | can = in8 (PLD_CAN_REG); | |
732 | serpwr = in8 (PLD_SER_PWR_REG); | |
733 | compwr = in8 (PLD_COM_PWR_REG); | |
734 | nicvga = in8 (PLD_NIC_VGA_REG); | |
735 | scsirst = in8 (PLD_SCSI_RST_REG); | |
736 | printf ("PLD Part %d version %d\n", | |
737 | part & 0xf, vers & 0xf); | |
738 | printf ("PLD Part %d version %d\n", | |
739 | (part >> 4) & 0xf, (vers >> 4) & 0xf); | |
740 | printf ("Board Revision %c\n", (cfg & 0xf) + 'A'); | |
741 | printf ("Population Options %d %d %d %d\n", | |
742 | (cfg >> 4) & 0x1, (cfg >> 5) & 0x1, | |
743 | (cfg >> 6) & 0x1, (cfg >> 7) & 0x1); | |
744 | printf ("User LED0 %s User LED1 %s\n", | |
745 | ((ledu & 0x1) == 0x1) ? "on" : "off", | |
746 | ((ledu & 0x2) == 0x2) ? "on" : "off"); | |
747 | printf ("Additionally Options %d %d\n", | |
748 | (ledu >> 2) & 0x1, (ledu >> 3) & 0x1); | |
749 | printf ("User Config Switch %d %d %d %d\n", | |
750 | (ledu >> 4) & 0x1, (ledu >> 5) & 0x1, | |
751 | (ledu >> 6) & 0x1, (ledu >> 7) & 0x1); | |
752 | switch (sysman & 0x3) { | |
753 | case 0: | |
754 | printf ("PCI Clocks are running\n"); | |
755 | break; | |
756 | case 1: | |
757 | printf ("PCI Clocks are stopped in POS State\n"); | |
758 | break; | |
759 | case 2: | |
760 | printf ("PCI Clocks are stopped when PCI_STP# is asserted\n"); | |
761 | break; | |
762 | case 3: | |
763 | printf ("PCI Clocks are stopped\n"); | |
764 | break; | |
765 | } | |
766 | switch ((sysman >> 2) & 0x3) { | |
767 | case 0: | |
768 | printf ("Main Clocks are running\n"); | |
769 | break; | |
770 | case 1: | |
771 | printf ("Main Clocks are stopped in POS State\n"); | |
772 | break; | |
773 | case 2: | |
774 | case 3: | |
775 | printf ("PCI Clocks are stopped\n"); | |
776 | break; | |
777 | } | |
778 | printf ("INIT asserts %sINT2# (SMI)\n", | |
779 | ((sysman & 0x10) == 0x10) ? "" : "not "); | |
780 | printf ("INIT asserts %sINT1# (NMI)\n", | |
781 | ((sysman & 0x20) == 0x20) ? "" : "not "); | |
eae4b2b6 | 782 | printf ("INIT occurred %d\n", (sysman >> 6) & 0x1); |
7d393aed WD |
783 | printf ("SER1 is routed to %s\n", |
784 | ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232"); | |
785 | printf ("COM2 is routed to %s\n", | |
786 | ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232"); | |
787 | printf ("RS485 is configured as %s duplex\n", | |
788 | ((flashcom & 0x4) == 0x4) ? "full" : "half"); | |
789 | printf ("RS485 is connected to %s\n", | |
790 | ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2"); | |
791 | printf ("SER1 uses handshakes %s\n", | |
792 | ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS"); | |
793 | printf ("Bootflash is %swriteprotected\n", | |
794 | ((flashcom & 0x20) == 0x20) ? "not " : ""); | |
795 | printf ("Bootflash VPP is %s\n", | |
796 | ((flashcom & 0x40) == 0x40) ? "on" : "off"); | |
797 | printf ("Bootsector is %swriteprotected\n", | |
798 | ((flashcom & 0x80) == 0x80) ? "not " : ""); | |
799 | switch ((can) & 0x3) { | |
800 | case 0: | |
801 | printf ("CAN Controller is on address 0x1000..0x10FF\n"); | |
802 | break; | |
803 | case 1: | |
804 | printf ("CAN Controller is on address 0x8000..0x80FF\n"); | |
805 | break; | |
806 | case 2: | |
807 | printf ("CAN Controller is on address 0xE000..0xE0FF\n"); | |
808 | break; | |
809 | case 3: | |
810 | printf ("CAN Controller is disabled\n"); | |
811 | break; | |
812 | } | |
813 | switch ((can >> 2) & 0x3) { | |
814 | case 0: | |
815 | printf ("CAN Controller Reset is ISA Reset\n"); | |
816 | break; | |
817 | case 1: | |
818 | printf ("CAN Controller Reset is ISA Reset and POS State\n"); | |
819 | break; | |
820 | case 2: | |
821 | case 3: | |
822 | printf ("CAN Controller is in reset\n"); | |
823 | break; | |
824 | } | |
825 | if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13)) | |
826 | printf ("CAN Interrupt is disabled\n"); | |
827 | else | |
828 | printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf); | |
829 | switch (serpwr & 0x3) { | |
830 | case 0: | |
831 | printf ("SER0 Drivers are enabled\n"); | |
832 | break; | |
833 | case 1: | |
834 | printf ("SER0 Drivers are disabled in the POS state\n"); | |
835 | break; | |
836 | case 2: | |
837 | case 3: | |
838 | printf ("SER0 Drivers are disabled\n"); | |
839 | break; | |
840 | } | |
841 | switch ((serpwr >> 2) & 0x3) { | |
842 | case 0: | |
843 | printf ("SER1 Drivers are enabled\n"); | |
844 | break; | |
845 | case 1: | |
846 | printf ("SER1 Drivers are disabled in the POS state\n"); | |
847 | break; | |
848 | case 2: | |
849 | case 3: | |
850 | printf ("SER1 Drivers are disabled\n"); | |
851 | break; | |
852 | } | |
853 | switch (compwr & 0x3) { | |
854 | case 0: | |
855 | printf ("COM1 Drivers are enabled\n"); | |
856 | break; | |
857 | case 1: | |
858 | printf ("COM1 Drivers are disabled in the POS state\n"); | |
859 | break; | |
860 | case 2: | |
861 | case 3: | |
862 | printf ("COM1 Drivers are disabled\n"); | |
863 | break; | |
864 | } | |
865 | switch ((compwr >> 2) & 0x3) { | |
866 | case 0: | |
867 | printf ("COM2 Drivers are enabled\n"); | |
868 | break; | |
869 | case 1: | |
870 | printf ("COM2 Drivers are disabled in the POS state\n"); | |
871 | break; | |
872 | case 2: | |
873 | case 3: | |
874 | printf ("COM2 Drivers are disabled\n"); | |
875 | break; | |
876 | } | |
877 | switch ((nicvga) & 0x3) { | |
878 | case 0: | |
879 | printf ("PHY is running\n"); | |
880 | break; | |
881 | case 1: | |
882 | printf ("PHY is in Power save mode in POS state\n"); | |
883 | break; | |
884 | case 2: | |
885 | case 3: | |
886 | printf ("PHY is in Power save mode\n"); | |
887 | break; | |
888 | } | |
889 | switch ((nicvga >> 2) & 0x3) { | |
890 | case 0: | |
891 | printf ("VGA is running\n"); | |
892 | break; | |
893 | case 1: | |
894 | printf ("VGA is in Power save mode in POS state\n"); | |
895 | break; | |
896 | case 2: | |
897 | case 3: | |
898 | printf ("VGA is in Power save mode\n"); | |
899 | break; | |
900 | } | |
901 | printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not "); | |
902 | printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not "); | |
903 | printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1, | |
904 | (nicvga >> 7) & 0x1); | |
905 | switch ((scsirst) & 0x3) { | |
906 | case 0: | |
907 | printf ("SCSI Controller is running\n"); | |
908 | break; | |
909 | case 1: | |
910 | printf ("SCSI Controller is in Power save mode in POS state\n"); | |
911 | break; | |
912 | case 2: | |
913 | case 3: | |
914 | printf ("SCSI Controller is in Power save mode\n"); | |
915 | break; | |
916 | } | |
917 | printf ("SCSI termination is %s\n", | |
918 | ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled"); | |
919 | printf ("SCSI Controller is %sreseted\n", | |
920 | ((scsirst & 0x10) == 0x10) ? "" : "not "); | |
921 | printf ("IDE disks are %sreseted\n", | |
922 | ((scsirst & 0x20) == 0x20) ? "" : "not "); | |
923 | printf ("ISA Bus is %sreseted\n", | |
924 | ((scsirst & 0x40) == 0x40) ? "" : "not "); | |
925 | printf ("Super IO is %sreseted\n", | |
926 | ((scsirst & 0x80) == 0x80) ? "" : "not "); | |
927 | } | |
928 | ||
929 | void user_led0 (unsigned char on) | |
930 | { | |
472d5460 | 931 | if (on == true) |
7d393aed WD |
932 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); |
933 | else | |
934 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); | |
935 | } | |
936 | ||
937 | void user_led1 (unsigned char on) | |
938 | { | |
472d5460 | 939 | if (on == true) |
7d393aed WD |
940 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); |
941 | else | |
942 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); | |
943 | } | |
944 | ||
945 | void ide_set_reset (int idereset) | |
946 | { | |
947 | /* if reset = 1 IDE reset will be asserted */ | |
948 | unsigned char resreg; | |
949 | ||
950 | resreg = in8 (PLD_SCSI_RST_REG); | |
951 | if (idereset == 1) | |
952 | resreg |= 0x20; | |
953 | else { | |
954 | udelay(10000); | |
955 | resreg &= 0xdf; | |
956 | } | |
957 | out8 (PLD_SCSI_RST_REG, resreg); | |
958 | } |