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6c0bbdcc NI |
1 | /* |
2 | * Copyright (C) 2007 | |
3 | * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
61fb15c5 | 4 | * |
6c0bbdcc NI |
5 | * Copyright (C) 2007 |
6 | * Kenati Technologies, Inc. | |
7 | * | |
8 | * board/ms7722se/lowlevel_init.S | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
6c0bbdcc NI |
11 | */ |
12 | ||
13 | #include <config.h> | |
6c0bbdcc NI |
14 | |
15 | #include <asm/processor.h> | |
f7e78f3b | 16 | #include <asm/macro.h> |
6c0bbdcc NI |
17 | |
18 | /* | |
e4430779 JCPV |
19 | * Board specific low level init code, called _very_ early in the |
20 | * startup sequence. Relocation to SDRAM has not happened yet, no | |
21 | * stack is available, bss section has not been initialised, etc. | |
6c0bbdcc | 22 | * |
e4430779 | 23 | * (Note: As no stack is available, no subroutines can be called...). |
6c0bbdcc NI |
24 | */ |
25 | ||
26 | .global lowlevel_init | |
27 | ||
28 | .text | |
29 | .align 2 | |
30 | ||
31 | lowlevel_init: | |
32 | ||
f7e78f3b JCPV |
33 | /* |
34 | * Cache Control Register | |
35 | * Instruction Cache Invalidate | |
36 | */ | |
37 | write32 CCR_A, CCR_D | |
6c0bbdcc | 38 | |
f7e78f3b JCPV |
39 | /* |
40 | * Address of MMU Control Register | |
41 | * TI == TLB Invalidate bit | |
42 | */ | |
43 | write32 MMUCR_A, MMUCR_D | |
6c0bbdcc | 44 | |
b5d10a13 | 45 | /* Address of Power Control Register 0 */ |
f7e78f3b | 46 | write32 MSTPCR0_A, MSTPCR0_D |
6c0bbdcc | 47 | |
b5d10a13 | 48 | /* Address of Power Control Register 2 */ |
f7e78f3b | 49 | write32 MSTPCR2_A, MSTPCR2_D |
6c0bbdcc | 50 | |
f7e78f3b | 51 | write16 SBSCR_A, SBSCR_D |
6c0bbdcc | 52 | |
f7e78f3b | 53 | write16 PSCR_A, PSCR_D |
6c0bbdcc | 54 | |
b5d10a13 | 55 | /* 0xA4520004 (Watchdog Control / Status Register) */ |
f7e78f3b | 56 | ! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */ |
6c0bbdcc | 57 | |
b5d10a13 | 58 | /* 0xA4520000 (Watchdog Count Register) */ |
f7e78f3b | 59 | write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */ |
6c0bbdcc | 60 | |
b5d10a13 | 61 | /* 0xA4520004 (Watchdog Control / Status Register) */ |
f7e78f3b | 62 | write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */ |
6c0bbdcc | 63 | |
b5d10a13 | 64 | /* 0xA4150000 Frequency control register */ |
f7e78f3b | 65 | write32 FRQCR_A, FRQCR_D |
6c0bbdcc | 66 | |
f7e78f3b | 67 | write32 CCR_A, CCR_D_2 |
6c0bbdcc NI |
68 | |
69 | bsc_init: | |
70 | ||
f7e78f3b | 71 | write16 PSELA_A, PSELA_D |
6c0bbdcc | 72 | |
f7e78f3b | 73 | write16 DRVCR_A, DRVCR_D |
6c0bbdcc | 74 | |
f7e78f3b | 75 | write16 PCCR_A, PCCR_D |
6c0bbdcc | 76 | |
f7e78f3b | 77 | write16 PECR_A, PECR_D |
6c0bbdcc | 78 | |
f7e78f3b | 79 | write16 PJCR_A, PJCR_D |
6c0bbdcc | 80 | |
f7e78f3b | 81 | write16 PXCR_A, PXCR_D |
6c0bbdcc | 82 | |
f7e78f3b | 83 | write32 CMNCR_A, CMNCR_D |
6c0bbdcc | 84 | |
f7e78f3b | 85 | write32 CS0BCR_A, CS0BCR_D |
6c0bbdcc | 86 | |
f7e78f3b | 87 | write32 CS2BCR_A, CS2BCR_D |
6c0bbdcc | 88 | |
f7e78f3b | 89 | write32 CS4BCR_A, CS4BCR_D |
6c0bbdcc | 90 | |
f7e78f3b | 91 | write32 CS5ABCR_A, CS5ABCR_D |
6c0bbdcc | 92 | |
f7e78f3b | 93 | write32 CS5BBCR_A, CS5BBCR_D |
6c0bbdcc | 94 | |
f7e78f3b | 95 | write32 CS6ABCR_A, CS6ABCR_D |
6c0bbdcc | 96 | |
f7e78f3b | 97 | write32 CS0WCR_A, CS0WCR_D |
6c0bbdcc | 98 | |
f7e78f3b | 99 | write32 CS2WCR_A, CS2WCR_D |
6c0bbdcc | 100 | |
f7e78f3b | 101 | write32 CS4WCR_A, CS4WCR_D |
6c0bbdcc | 102 | |
f7e78f3b | 103 | write32 CS5AWCR_A, CS5AWCR_D |
6c0bbdcc | 104 | |
f7e78f3b | 105 | write32 CS5BWCR_A, CS5BWCR_D |
6c0bbdcc | 106 | |
f7e78f3b | 107 | write32 CS6AWCR_A, CS6AWCR_D |
6c0bbdcc NI |
108 | |
109 | ! SDRAM initialization | |
f7e78f3b | 110 | write32 SDCR_A, SDCR_D |
6c0bbdcc | 111 | |
f7e78f3b | 112 | write32 SDWCR_A, SDWCR_D |
6c0bbdcc | 113 | |
f7e78f3b | 114 | write32 SDPCR_A, SDPCR_D |
6c0bbdcc | 115 | |
f7e78f3b | 116 | write32 RTCOR_A, RTCOR_D |
6c0bbdcc | 117 | |
f7e78f3b | 118 | write32 RTCSR_A, RTCSR_D |
6c0bbdcc | 119 | |
c9935c99 | 120 | write8 SDMR3_A, SDMR3_D |
6c0bbdcc | 121 | |
e4430779 | 122 | ! BL bit off (init = ON) (?!?) |
6c0bbdcc NI |
123 | |
124 | stc sr, r0 ! BL bit off(init=ON) | |
125 | mov.l SR_MASK_D, r1 | |
126 | and r1, r0 | |
127 | ldc r0, sr | |
128 | ||
129 | rts | |
130 | mov #0, r0 | |
131 | ||
6c0bbdcc NI |
132 | .align 2 |
133 | ||
61fb15c5 | 134 | CCR_A: .long CCR |
6c0bbdcc NI |
135 | MMUCR_A: .long MMUCR |
136 | MSTPCR0_A: .long MSTPCR0 | |
137 | MSTPCR2_A: .long MSTPCR2 | |
138 | SBSCR_A: .long SBSCR | |
139 | PSCR_A: .long PSCR | |
140 | RWTCSR_A: .long RWTCSR | |
141 | RWTCNT_A: .long RWTCNT | |
142 | FRQCR_A: .long FRQCR | |
143 | ||
144 | CCR_D: .long 0x00000800 | |
145 | CCR_D_2: .long 0x00000103 | |
146 | MMUCR_D: .long 0x00000004 | |
147 | MSTPCR0_D: .long 0x00001001 | |
148 | MSTPCR2_D: .long 0xffffffff | |
149 | FRQCR_D: .long 0x07022538 | |
150 | ||
e4430779 JCPV |
151 | PSELA_A: .long 0xa405014E |
152 | PSELA_D: .word 0x0A10 | |
61fb15c5 | 153 | .align 2 |
6c0bbdcc | 154 | |
e4430779 JCPV |
155 | DRVCR_A: .long 0xa405018A |
156 | DRVCR_D: .word 0x0554 | |
6c0bbdcc NI |
157 | .align 2 |
158 | ||
e4430779 JCPV |
159 | PCCR_A: .long 0xa4050104 |
160 | PCCR_D: .word 0x8800 | |
6c0bbdcc NI |
161 | .align 2 |
162 | ||
e4430779 JCPV |
163 | PECR_A: .long 0xa4050108 |
164 | PECR_D: .word 0x0000 | |
6c0bbdcc NI |
165 | .align 2 |
166 | ||
e4430779 JCPV |
167 | PJCR_A: .long 0xa4050110 |
168 | PJCR_D: .word 0x1000 | |
6c0bbdcc NI |
169 | .align 2 |
170 | ||
e4430779 JCPV |
171 | PXCR_A: .long 0xa4050148 |
172 | PXCR_D: .word 0x0AAA | |
6c0bbdcc NI |
173 | .align 2 |
174 | ||
175 | CMNCR_A: .long CMNCR | |
176 | CMNCR_D: .long 0x00000013 | |
177 | CS0BCR_A: .long CS0BCR ! Flash bank 1 | |
178 | CS0BCR_D: .long 0x24920400 | |
179 | CS2BCR_A: .long CS2BCR ! SRAM | |
180 | CS2BCR_D: .long 0x24920400 | |
181 | CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot | |
182 | CS4BCR_D: .long 0x24920400 | |
183 | CS5ABCR_A: .long CS5ABCR ! Ext slot | |
184 | CS5ABCR_D: .long 0x24920400 | |
185 | CS5BBCR_A: .long CS5BBCR ! USB controller | |
186 | CS5BBCR_D: .long 0x24920400 | |
187 | CS6ABCR_A: .long CS6ABCR ! Ethernet | |
188 | CS6ABCR_D: .long 0x24920400 | |
189 | ||
190 | CS0WCR_A: .long CS0WCR | |
191 | CS0WCR_D: .long 0x00000300 | |
192 | CS2WCR_A: .long CS2WCR | |
193 | CS2WCR_D: .long 0x00000300 | |
194 | CS4WCR_A: .long CS4WCR | |
195 | CS4WCR_D: .long 0x00000300 | |
196 | CS5AWCR_A: .long CS5AWCR | |
197 | CS5AWCR_D: .long 0x00000300 | |
198 | CS5BWCR_A: .long CS5BWCR | |
199 | CS5BWCR_D: .long 0x00000300 | |
200 | CS6AWCR_A: .long CS6AWCR | |
201 | CS6AWCR_D: .long 0x00000300 | |
202 | ||
203 | SDCR_A: .long SBSC_SDCR | |
204 | SDCR_D: .long 0x00020809 | |
205 | SDWCR_A: .long SBSC_SDWCR | |
206 | SDWCR_D: .long 0x00164d0d | |
207 | SDPCR_A: .long SBSC_SDPCR | |
208 | SDPCR_D: .long 0x00000087 | |
209 | RTCOR_A: .long SBSC_RTCOR | |
210 | RTCOR_D: .long 0xA55A0034 | |
211 | RTCSR_A: .long SBSC_RTCSR | |
212 | RTCSR_D: .long 0xA55A0010 | |
213 | SDMR3_A: .long 0xFE500180 | |
c9935c99 | 214 | SDMR3_D: .long 0x0 |
6c0bbdcc NI |
215 | |
216 | .align 1 | |
217 | ||
218 | SBSCR_D: .word 0x0040 | |
219 | PSCR_D: .word 0x0000 | |
220 | RWTCSR_D_1: .word 0xA507 | |
221 | RWTCSR_D_2: .word 0xA507 | |
222 | RWTCNT_D: .word 0x5A00 | |
b5d10a13 | 223 | .align 2 |
6c0bbdcc NI |
224 | |
225 | SR_MASK_D: .long 0xEFFFFF0F |