[people/ms/u-boot.git] / board / ms7750se / lowlevel_init.S

/*
 modified from SH-IPL+g
 Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.

 Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R

 Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>

 * SPDX-License-Identifier:	GPL-2.0+
*/

#include <config.h>
#include <version.h>

#include <asm/processor.h>
#include <asm/macro.h>

#ifdef CONFIG_CPU_SH7751
#define BCR2_D_VALUE	0x2FFC		/* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE	0x02770771	/* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#ifdef CONFIG_MARUBUN_PCCARD
#define WCR2_D_VALUE	0xFFFE4FE7	/* A6:15 A6B:7 A5:15 A5B:7 A4:15
					   A3:2  A2:15 A1:15 A0:6  A0B:7  */
#else /* CONFIG_MARUBUN_PCCARD */
#define WCR2_D_VALUE	0x7FFE4FE7	/* A6:3  A6B:7 A5:15 A5B:7 A4:15
					   A3:2  A2:15 A1:15 A0:6  A0B:7  */
#endif /* CONFIG_MARUBUN_PCCARD */
#define WCR3_D_VALUE	0x01777771	/* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
					   A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE	0xA50D		/* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS	0xFF940088	/* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE	0x100901B4	/* SDRAM 32-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE	0x500901B4	/* Same w/MRSET now 1 (mode reg cmd) */
#else /* CONFIG_CPU_SH7751 */
#define BCR2_D_VALUE	0x2E3C		/* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE	0x02720777	/* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE	0xFFFE4FFF	/* A6:15 A6B:7 A5:15 A5B:7 A4:15
					   A3:2  A2:15 A1:15 A0:15 A0B:7  */
#define WCR3_D_VALUE	0x01717771	/* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
					   A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE	0xA510		/* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS	0xFF940110	/* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE	0x8801001C	/* SDRAM 64-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE	0xC801001C	/* Same w/MRSET now 1 (mode reg cmd) */
#endif /* CONFIG_CPU_SH7751 */

	.global lowlevel_init
	.text
	.align	2

lowlevel_init:

	write32	CCR_A, CCR_D_DISABLE

init_bsc:
	write16	FRQCR_A, FRQCR_D

	write32	BCR1_A, BCR1_D

	write16	BCR2_A, BCR2_D

	write32	WCR1_A, WCR1_D

	write32	WCR2_A, WCR2_D

	write32	WCR3_A, WCR3_D

	write32	MCR_A, MCR_D1

	/* Set SDRAM mode */
	write8	SDMR3_A, SDMR3_D

	! Do you need PCMCIA setting?
	! If so, please add the lines here...

	write16	RTCNT_A, RTCNT_D

	write16	RTCOR_A, RTCOR_D

	write16	RTCSR_A, RTCSR_D

	write16	RFCR_A, RFCR_D

	/* Wait DRAM refresh 30 times */
	mov	#30, r3
1:
	mov.w	@r1, r0
	extu.w	r0, r2
	cmp/hi	r3, r2
	bf	1b

	write32	MCR_A, MCR_D2

	/* Set SDRAM mode */
	write8	SDMR3_A, SDMR3_D

	rts
	nop

	.align	2

CCR_A:		 .long	CCR
CCR_D_DISABLE:	.long	0x0808
FRQCR_A:	.long	FRQCR
FRQCR_D:
#ifdef CONFIG_CPU_TYPE_R
		.word	0x0e1a	/* 12:3:3 */
#else	/* CONFIG_CPU_TYPE_R */
#ifdef CONFIG_GOOD_SESH4
		.word	0x00e13	/* 6:2:1 */
#else
		.word	0x00e23	/* 6:1:1 */
#endif
.align 2
#endif	/* CONFIG_CPU_TYPE_R */

BCR1_A:		.long	BCR1
BCR1_D:		.long	0x00000008	/* Area 3 SDRAM */
BCR2_A:		.long	BCR2
BCR2_D:		.long	BCR2_D_VALUE	/* Bus width settings */
WCR1_A:		.long	WCR1
WCR1_D:		.long	WCR1_D_VALUE	/* Inter-area or turnaround wait states */
WCR2_A:		.long	WCR2
WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
WCR3_A:		.long	WCR3
WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
RTCSR_A:	.long	RTCSR
RTCSR_D:	.word	0xA518		/* RTCSR Write Code A5h Data 18h */
.align 2
RTCNT_A:	.long	RTCNT
RTCNT_D:	.word	0xA500		/* RTCNT Write Code A5h Data 00h */
.align 2
RTCOR_A:	.long	RTCOR
RTCOR_D:	.word	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
.align 2
SDMR3_A:	.long	SDMR3_ADDRESS
SDMR3_D:	.long	0x00
MCR_A:		.long	MCR
MCR_D1:		.long	MCR_D1_VALUE
MCR_D2:		.long	MCR_D2_VALUE
RFCR_A:		.long	RFCR
RFCR_D:		.word	0xA400		/* RFCR Write Code A4h Data 00h */
.align 2
Commit	Line	Data
69df3c4d	1	/*
047375bf NI	2	modified from SH-IPL+g
	3	Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
	4
61fb15c5 WD	5	Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
61fb15c5 WD	6
047375bf NI	7	Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
047375bf NI	8
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
69df3c4d NI	10	*/
	11
	12	#include <config.h>
	13	#include <version.h>
	14
	15	#include <asm/processor.h>
f7e78f3b	16	#include <asm/macro.h>
69df3c4d	17
047375bf	18	#ifdef CONFIG_CPU_SH7751
e4430779 JCPV	19	#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
e4430779 JCPV	20	#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
047375bf	21	#ifdef CONFIG_MARUBUN_PCCARD
e4430779 JCPV	22	#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
e4430779 JCPV	23	A3:2 A2:15 A1:15 A0:6 A0B:7 */
047375bf	24	#else /* CONFIG_MARUBUN_PCCARD */
e4430779 JCPV	25	#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
e4430779 JCPV	26	A3:2 A2:15 A1:15 A0:6 A0B:7 */
047375bf	27	#endif /* CONFIG_MARUBUN_PCCARD */
e4430779 JCPV	28	#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
	29	A2: 1-3 A1: 1-3 A0: 0-1 */
	30	#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
	31	#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
	32	#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
	33	#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
047375bf	34	#else /* CONFIG_CPU_SH7751 */
e4430779 JCPV	35	#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
	36	#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
	37	#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
	38	A3:2 A2:15 A1:15 A0:15 A0B:7 */
	39	#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
	40	A2: 1-3 A1: 1-3 A0: 0-1 */
	41	#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
	42	#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
	43	#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
	44	#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
047375bf	45	#endif /* CONFIG_CPU_SH7751 */
69df3c4d NI	46
	47	.global lowlevel_init
	48	.text
e4430779	49	.align 2
69df3c4d NI	50
	51	lowlevel_init:
	52
f7e78f3b	53	write32 CCR_A, CCR_D_DISABLE
69df3c4d NI	54
69df3c4d NI	55	init_bsc:
f7e78f3b	56	write16 FRQCR_A, FRQCR_D
69df3c4d	57
f7e78f3b	58	write32 BCR1_A, BCR1_D
69df3c4d	59
f7e78f3b	60	write16 BCR2_A, BCR2_D
69df3c4d	61
f7e78f3b	62	write32 WCR1_A, WCR1_D
69df3c4d	63
f7e78f3b	64	write32 WCR2_A, WCR2_D
69df3c4d	65
f7e78f3b	66	write32 WCR3_A, WCR3_D
69df3c4d	67
f7e78f3b	68	write32 MCR_A, MCR_D1
69df3c4d	69
f7e78f3b	70	/* Set SDRAM mode */
c9935c99	71	write8 SDMR3_A, SDMR3_D
69df3c4d	72
61fb15c5	73	! Do you need PCMCIA setting?
69df3c4d NI	74	! If so, please add the lines here...
69df3c4d NI	75
f7e78f3b	76	write16 RTCNT_A, RTCNT_D
69df3c4d	77
f7e78f3b	78	write16 RTCOR_A, RTCOR_D
69df3c4d	79
f7e78f3b JCPV	80	write16 RTCSR_A, RTCSR_D
	81
	82	write16 RFCR_A, RFCR_D
69df3c4d	83
69df3c4d	84	/* Wait DRAM refresh 30 times */
e4430779	85	mov #30, r3
69df3c4d	86	1:
e4430779 JCPV	87	mov.w @r1, r0
	88	extu.w r0, r2
	89	cmp/hi r3, r2
69df3c4d NI	90	bf 1b
69df3c4d NI	91
f7e78f3b	92	write32 MCR_A, MCR_D2
69df3c4d	93
f7e78f3b	94	/* Set SDRAM mode */
c9935c99	95	write8 SDMR3_A, SDMR3_D
69df3c4d NI	96
69df3c4d NI	97	rts
e4430779	98	nop
69df3c4d NI	99
	100	.align 2
	101
e4430779 JCPV	102	CCR_A: .long CCR
e4430779 JCPV	103	CCR_D_DISABLE: .long 0x0808
69df3c4d NI	104	FRQCR_A: .long FRQCR
69df3c4d NI	105	FRQCR_D:
047375bf	106	#ifdef CONFIG_CPU_TYPE_R
33971937	107	.word 0x0e1a /* 12:3:3 */
047375bf	108	#else /* CONFIG_CPU_TYPE_R */
69df3c4d	109	#ifdef CONFIG_GOOD_SESH4
33971937	110	.word 0x00e13 /* 6:2:1 */
69df3c4d	111	#else
33971937	112	.word 0x00e23 /* 6:1:1 */
69df3c4d	113	#endif
33971937	114	.align 2
047375bf	115	#endif /* CONFIG_CPU_TYPE_R */
69df3c4d NI	116
	117	BCR1_A: .long BCR1
	118	BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
	119	BCR2_A: .long BCR2
	120	BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
	121	WCR1_A: .long WCR1
	122	WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
	123	WCR2_A: .long WCR2
	124	WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
	125	WCR3_A: .long WCR3
	126	WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
61fb15c5	127	RTCSR_A: .long RTCSR
33971937 NI	128	RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
33971937 NI	129	.align 2
69df3c4d	130	RTCNT_A: .long RTCNT
33971937 NI	131	RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
33971937 NI	132	.align 2
69df3c4d	133	RTCOR_A: .long RTCOR
33971937 NI	134	RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */
33971937 NI	135	.align 2
69df3c4d	136	SDMR3_A: .long SDMR3_ADDRESS
c9935c99	137	SDMR3_D: .long 0x00
69df3c4d NI	138	MCR_A: .long MCR
	139	MCR_D1: .long MCR_D1_VALUE
	140	MCR_D2: .long MCR_D2_VALUE
	141	RFCR_A: .long RFCR
33971937 NI	142	RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */
33971937 NI	143	.align 2