projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 69df3c4d | 1 | /* |
| 047375bf NI |
2 | modified from SH-IPL+g |
| 3 | Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. | |
| 4 | ||
| 61fb15c5 WD |
5 | Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R |
| 6 | ||
| 047375bf NI |
7 | Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org> |
| 8 | ||
| 1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
| 69df3c4d NI |
10 | */ |
| 11 | ||
| 12 | #include <config.h> | |
| 69df3c4d NI |
13 | |
| 14 | #include <asm/processor.h> | |
| f7e78f3b | 15 | #include <asm/macro.h> |
| 69df3c4d | 16 | |
| 047375bf | 17 | #ifdef CONFIG_CPU_SH7751 |
| e4430779 JCPV |
18 | #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ |
| 19 | #define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ | |
| 047375bf | 20 | #ifdef CONFIG_MARUBUN_PCCARD |
| e4430779 JCPV |
21 | #define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 |
| 22 | A3:2 A2:15 A1:15 A0:6 A0B:7 */ | |
| 047375bf | 23 | #else /* CONFIG_MARUBUN_PCCARD */ |
| e4430779 JCPV |
24 | #define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 |
| 25 | A3:2 A2:15 A1:15 A0:6 A0B:7 */ | |
| 047375bf | 26 | #endif /* CONFIG_MARUBUN_PCCARD */ |
| e4430779 JCPV |
27 | #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 |
| 28 | A2: 1-3 A1: 1-3 A0: 0-1 */ | |
| 29 | #define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ | |
| 30 | #define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ | |
| 31 | #define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ | |
| 32 | #define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ | |
| 047375bf | 33 | #else /* CONFIG_CPU_SH7751 */ |
| e4430779 JCPV |
34 | #define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ |
| 35 | #define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ | |
| 36 | #define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 | |
| 37 | A3:2 A2:15 A1:15 A0:15 A0B:7 */ | |
| 38 | #define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 | |
| 39 | A2: 1-3 A1: 1-3 A0: 0-1 */ | |
| 40 | #define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ | |
| 41 | #define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ | |
| 42 | #define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ | |
| 43 | #define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ | |
| 047375bf | 44 | #endif /* CONFIG_CPU_SH7751 */ |
| 69df3c4d NI |
45 | |
| 46 | .global lowlevel_init | |
| 47 | .text | |
| e4430779 | 48 | .align 2 |
| 69df3c4d NI |
49 | |
| 50 | lowlevel_init: | |
| 51 | ||
| f7e78f3b | 52 | write32 CCR_A, CCR_D_DISABLE |
| 69df3c4d NI |
53 | |
| 54 | init_bsc: | |
| f7e78f3b | 55 | write16 FRQCR_A, FRQCR_D |
| 69df3c4d | 56 | |
| f7e78f3b | 57 | write32 BCR1_A, BCR1_D |
| 69df3c4d | 58 | |
| f7e78f3b | 59 | write16 BCR2_A, BCR2_D |
| 69df3c4d | 60 | |
| f7e78f3b | 61 | write32 WCR1_A, WCR1_D |
| 69df3c4d | 62 | |
| f7e78f3b | 63 | write32 WCR2_A, WCR2_D |
| 69df3c4d | 64 | |
| f7e78f3b | 65 | write32 WCR3_A, WCR3_D |
| 69df3c4d | 66 | |
| f7e78f3b | 67 | write32 MCR_A, MCR_D1 |
| 69df3c4d | 68 | |
| f7e78f3b | 69 | /* Set SDRAM mode */ |
| c9935c99 | 70 | write8 SDMR3_A, SDMR3_D |
| 69df3c4d | 71 | |
| 61fb15c5 | 72 | ! Do you need PCMCIA setting? |
| 69df3c4d NI |
73 | ! If so, please add the lines here... |
| 74 | ||
| f7e78f3b | 75 | write16 RTCNT_A, RTCNT_D |
| 69df3c4d | 76 | |
| f7e78f3b | 77 | write16 RTCOR_A, RTCOR_D |
| 69df3c4d | 78 | |
| f7e78f3b JCPV |
79 | write16 RTCSR_A, RTCSR_D |
| 80 | ||
| 81 | write16 RFCR_A, RFCR_D | |
| 69df3c4d | 82 | |
| 69df3c4d | 83 | /* Wait DRAM refresh 30 times */ |
| e4430779 | 84 | mov #30, r3 |
| 69df3c4d | 85 | 1: |
| e4430779 JCPV |
86 | mov.w @r1, r0 |
| 87 | extu.w r0, r2 | |
| 88 | cmp/hi r3, r2 | |
| 69df3c4d NI |
89 | bf 1b |
| 90 | ||
| f7e78f3b | 91 | write32 MCR_A, MCR_D2 |
| 69df3c4d | 92 | |
| f7e78f3b | 93 | /* Set SDRAM mode */ |
| c9935c99 | 94 | write8 SDMR3_A, SDMR3_D |
| 69df3c4d NI |
95 | |
| 96 | rts | |
| e4430779 | 97 | nop |
| 69df3c4d NI |
98 | |
| 99 | .align 2 | |
| 100 | ||
| e4430779 JCPV |
101 | CCR_A: .long CCR |
| 102 | CCR_D_DISABLE: .long 0x0808 | |
| 69df3c4d NI |
103 | FRQCR_A: .long FRQCR |
| 104 | FRQCR_D: | |
| 047375bf | 105 | #ifdef CONFIG_CPU_TYPE_R |
| 33971937 | 106 | .word 0x0e1a /* 12:3:3 */ |
| 047375bf | 107 | #else /* CONFIG_CPU_TYPE_R */ |
| 69df3c4d | 108 | #ifdef CONFIG_GOOD_SESH4 |
| 33971937 | 109 | .word 0x00e13 /* 6:2:1 */ |
| 69df3c4d | 110 | #else |
| 33971937 | 111 | .word 0x00e23 /* 6:1:1 */ |
| 69df3c4d | 112 | #endif |
| 33971937 | 113 | .align 2 |
| 047375bf | 114 | #endif /* CONFIG_CPU_TYPE_R */ |
| 69df3c4d NI |
115 | |
| 116 | BCR1_A: .long BCR1 | |
| 117 | BCR1_D: .long 0x00000008 /* Area 3 SDRAM */ | |
| 118 | BCR2_A: .long BCR2 | |
| 119 | BCR2_D: .long BCR2_D_VALUE /* Bus width settings */ | |
| 120 | WCR1_A: .long WCR1 | |
| 121 | WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ | |
| 122 | WCR2_A: .long WCR2 | |
| 123 | WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ | |
| 124 | WCR3_A: .long WCR3 | |
| 125 | WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ | |
| 61fb15c5 | 126 | RTCSR_A: .long RTCSR |
| 33971937 NI |
127 | RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ |
| 128 | .align 2 | |
| 69df3c4d | 129 | RTCNT_A: .long RTCNT |
| 33971937 NI |
130 | RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ |
| 131 | .align 2 | |
| 69df3c4d | 132 | RTCOR_A: .long RTCOR |
| 33971937 NI |
133 | RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ |
| 134 | .align 2 | |
| 69df3c4d | 135 | SDMR3_A: .long SDMR3_ADDRESS |
| c9935c99 | 136 | SDMR3_D: .long 0x00 |
| 69df3c4d NI |
137 | MCR_A: .long MCR |
| 138 | MCR_D1: .long MCR_D1_VALUE | |
| 139 | MCR_D2: .long MCR_D2_VALUE | |
| 140 | RFCR_A: .long RFCR | |
| 33971937 NI |
141 | RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ |
| 142 | .align 2 |