[people/ms/u-boot.git] / board / munices / munices.c

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#include "mt48lc16m16a2-75.h"

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *            is something else than 0x00000000.
 */

int initdram(void)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR && SDRAM_TAPDELAY
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
	sdram_start(1);
	test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CONFIG_SYS_RAMBOOT */

	gd->ram_size = dramsize + dramsize2;

	return 0;
}

int checkboard (void)
{
	puts ("Board: MUNICes\n");
	return 0;
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
6341d9d7 HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
6341d9d7 HS	6	*/
	7
	8	#include <common.h>
	9	#include <mpc5xxx.h>
	10	#include <pci.h>
	11
	12	#include "mt48lc16m16a2-75.h"
	13
088454cd SG	14	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	15
6d0f6bcf	16	#ifndef CONFIG_SYS_RAMBOOT
6341d9d7 HS	17	static void sdram_start (int hi_addr)
	18	{
	19	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	20
	21	/* unlock mode register */
	22	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	23	__asm__ volatile ("sync");
	24
	25	/* precharge all banks */
	26	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	27	__asm__ volatile ("sync");
	28
	29	#if SDRAM_DDR
	30	/* set mode register: extended mode */
	31	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	32	__asm__ volatile ("sync");
	33
	34	/* set mode register: reset DLL */
	35	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	36	__asm__ volatile ("sync");
	37	#endif
	38
	39	/* precharge all banks */
	40	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	41	__asm__ volatile ("sync");
	42
	43	/* auto refresh */
	44	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	45	__asm__ volatile ("sync");
	46
	47	/* set mode register */
	48	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	49	__asm__ volatile ("sync");
	50
	51	/* normal operation */
	52	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	53	__asm__ volatile ("sync");
	54	}
	55	#endif
	56
	57	/*
	58	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	59	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
6341d9d7 HS	60	* is something else than 0x00000000.
	61	*/
	62
088454cd	63	int initdram(void)
6341d9d7 HS	64	{
	65	ulong dramsize = 0;
	66	ulong dramsize2 = 0;
6d0f6bcf	67	#ifndef CONFIG_SYS_RAMBOOT
6341d9d7 HS	68	ulong test1, test2;
	69
	70	/* setup SDRAM chip selects */
	71	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
	72	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
	73	__asm__ volatile ("sync");
	74
	75	/* setup config registers */
	76	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	77	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	78	__asm__ volatile ("sync");
	79
	80	#if SDRAM_DDR && SDRAM_TAPDELAY
	81	/* set tap delay */
	82	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	83	__asm__ volatile ("sync");
	84	#endif
	85
	86	/* find RAM size using SDRAM CS0 only */
	87	sdram_start(0);
6d0f6bcf	88	test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
6341d9d7	89	sdram_start(1);
6d0f6bcf	90	test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
6341d9d7 HS	91	if (test1 > test2) {
	92	sdram_start(0);
	93	dramsize = test1;
	94	} else {
	95	dramsize = test2;
	96	}
	97
	98	/* memory smaller than 1MB is impossible */
	99	if (dramsize < (1 << 20)) {
	100	dramsize = 0;
	101	}
	102
	103	/* set SDRAM CS0 size according to the amount of RAM found */
	104	if (dramsize > 0) {
	105	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	106	} else {
	107	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	108	}
	109
6d0f6bcf	110	#else /* CONFIG_SYS_RAMBOOT */
6341d9d7 HS	111
	112	/* retrieve size of memory connected to SDRAM CS0 */
	113	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	114	if (dramsize >= 0x13) {
	115	dramsize = (1 << (dramsize - 0x13)) << 20;
	116	} else {
	117	dramsize = 0;
	118	}
	119
	120	/* retrieve size of memory connected to SDRAM CS1 */
	121	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	122	if (dramsize2 >= 0x13) {
	123	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	124	} else {
	125	dramsize2 = 0;
	126	}
	127
6d0f6bcf	128	#endif /* CONFIG_SYS_RAMBOOT */
6341d9d7	129
088454cd SG	130	gd->ram_size = dramsize + dramsize2;
	131
	132	return 0;
6341d9d7 HS	133	}
	134
	135	int checkboard (void)
	136	{
	137	puts ("Board: MUNICes\n");
	138	return 0;
	139	}
	140
	141	#ifdef CONFIG_PCI
	142	static struct pci_controller hose;
	143
	144	extern void pci_mpc5xxx_init(struct pci_controller *);
	145
	146	void pci_init_board(void)
	147	{
	148	pci_mpc5xxx_init(&hose);
	149	}
	150	#endif
	151
7ffe3cd6	152	#ifdef CONFIG_OF_BOARD_SETUP
e895a4b0	153	int ft_board_setup(void blob, bd_t bd)
6341d9d7 HS	154	{
6341d9d7 HS	155	ft_cpu_setup(blob, bd);
e895a4b0 SG	156
e895a4b0 SG	157	return 0;
6341d9d7	158	}
7ffe3cd6	159	#endif /* CONFIG_OF_BOARD_SETUP */