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Commit | Line | Data |
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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <mpc824x.h> | |
10 | #include <pci.h> | |
8ca0b3f9 | 11 | #include <netdev.h> |
c609719b WD |
12 | |
13 | int checkboard (void) | |
14 | { | |
15 | ulong busfreq = get_bus_freq(0); | |
16 | char buf[32]; | |
17 | ||
18 | printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq)); | |
19 | return 0; | |
20 | ||
21 | } | |
22 | ||
53677ef1 | 23 | #if 0 /* NOT USED */ |
c609719b WD |
24 | int checkflash (void) |
25 | { | |
26 | /* TODO: XXX XXX XXX */ | |
27 | printf ("## Test not implemented yet ##\n"); | |
28 | ||
29 | return (0); | |
30 | } | |
31 | #endif | |
32 | ||
9973e3c6 | 33 | phys_size_t initdram (int board_type) |
c609719b | 34 | { |
c83bf6a2 WD |
35 | long size; |
36 | long new_bank0_end; | |
37 | long mear1; | |
38 | long emear1; | |
39 | ||
6d0f6bcf | 40 | size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); |
c83bf6a2 WD |
41 | |
42 | new_bank0_end = size - 1; | |
43 | mear1 = mpc824x_mpc107_getreg(MEAR1); | |
44 | emear1 = mpc824x_mpc107_getreg(EMEAR1); | |
45 | mear1 = (mear1 & 0xFFFFFF00) | | |
46 | ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); | |
47 | emear1 = (emear1 & 0xFFFFFF00) | | |
48 | ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); | |
49 | mpc824x_mpc107_setreg(MEAR1, mear1); | |
50 | mpc824x_mpc107_setreg(EMEAR1, emear1); | |
51 | ||
52 | return (size); | |
c609719b WD |
53 | } |
54 | ||
55 | /* | |
56 | * Initialize PCI Devices | |
57 | */ | |
58 | #ifndef CONFIG_PCI_PNP | |
59 | static struct pci_config_table pci_sandpoint_config_table[] = { | |
60 | #if 0 | |
61 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
62 | 0x0, 0x0, 0x0, /* unknown eth0 divice */ | |
63 | pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, | |
64 | PCI_ENET0_MEMADDR, | |
65 | PCI_COMMAND_IO | | |
66 | PCI_COMMAND_MEMORY | | |
67 | PCI_COMMAND_MASTER }}, | |
68 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
69 | 0x0, 0x0, 0x0, /* unknown eth1 device */ | |
70 | pci_cfgfunc_config_device, { PCI_ENET1_IOADDR, | |
71 | PCI_ENET1_MEMADDR, | |
72 | PCI_COMMAND_IO | | |
73 | PCI_COMMAND_MEMORY | | |
74 | PCI_COMMAND_MASTER }}, | |
75 | #endif | |
76 | { } | |
77 | }; | |
78 | #endif | |
79 | ||
80 | struct pci_controller hose = { | |
81 | #ifndef CONFIG_PCI_PNP | |
82 | config_table: pci_sandpoint_config_table, | |
83 | #endif | |
84 | }; | |
85 | ||
ad10dd9a | 86 | void pci_init_board(void) |
c609719b WD |
87 | { |
88 | pci_mpc824x_init(&hose); | |
89 | } | |
8ca0b3f9 BW |
90 | |
91 | int board_eth_init(bd_t *bis) | |
92 | { | |
93 | return pci_eth_init(bis); | |
94 | } |