[people/ms/u-boot.git] / board / mvblue / mvblue.c

/*
 * GNU General Public License for more details.
 *
 * MATRIX Vision GmbH / June 2002-Nov 2003
 * Andre Schwarz
 */

#include <common.h>
#include <mpc824x.h>
#include <asm/io.h>
#include <ns16550.h>

#ifdef CONFIG_PCI
#include <pci.h>
#endif

u32 get_BoardType (void);

#define PCI_CONFIG(b,d,f,r)    cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
						      | ((d&0x1f)<<11) \
						      | ((f&0x7)<<7)   \
						      | (r&0xfc) )

int mv_pci_read (int bus, int dev, int func, int reg)
{
	*(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
	asm ("sync");
	return cpu_to_le32 (*(u32 *) (0xfee00cfc));
}

u32 get_BoardType ()
{
	return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
}

void init_2nd_DUART (void)
{
	NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
	int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;

	*(u8 *) (0xfc004511) = 0x1;
	NS16550_init (console, clock_divisor);
}
void hw_watchdog_reset (void)
{
	if (get_BoardType () == 0) {
		*(u32 *) (0xff000005) = 0;
		asm ("sync");
	}
}
int checkboard (void)
{
	DECLARE_GLOBAL_DATA_PTR;
	ulong busfreq = get_bus_freq (0);
	char buf[32];
	u32 BoardType = get_BoardType ();
	char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
	char *p;
	bd_t *bd = gd->bd;

	hw_watchdog_reset ();

	printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
	printf ("       Found %s running at %s MHz memory clock.\n",
		BoardName[BoardType], strmhz (buf, busfreq));

	init_2nd_DUART ();

	if ((p = getenv ("console_nr")) != NULL) {
		unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;

		bd->bi_baudrate &= ~3;
		bd->bi_baudrate |= con_nr & 3;
	}
	return 0;
}

long int initdram (int board_type)
{
	int i, cnt;
	volatile uchar *base = CFG_SDRAM_BASE;
	volatile ulong *addr;
	ulong save[32];
	ulong val, ret = 0;

	for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
	     cnt >>= 1) {
		addr = (volatile ulong *) base + cnt;
		save[i++] = *addr;
		*addr = ~cnt;
	}

	addr = (volatile ulong *) base;
	save[i] = *addr;
	*addr = 0;

	if (*addr != 0) {
		*addr = save[i];
		goto Done;
	}

	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
		addr = (volatile ulong *) base + cnt;
		val = *addr;
		*addr = save[--i];
		if (val != ~cnt) {
			ulong new_bank0_end = cnt * sizeof (long) - 1;
			ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
			ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);

			mear1 = (mear1 & 0xFFFFFF00) |
				((new_bank0_end & MICR_ADDR_MASK) >>
				 MICR_ADDR_SHIFT);
			emear1 = (emear1 & 0xFFFFFF00) |
				((new_bank0_end & MICR_ADDR_MASK) >>
				 MICR_EADDR_SHIFT);
			mpc824x_mpc107_setreg (MEAR1, mear1);
			mpc824x_mpc107_setreg (EMEAR1, emear1);
			ret = cnt * sizeof (long);
			goto Done;
		}
	}

	ret = CFG_MAX_RAM_SIZE;
      Done:
	return ret;
}

/* ------------------------------------------------------------------------- */
u8 *dhcp_vendorex_prep (u8 * e)
{
	char *ptr;

	/* DHCP vendor-class-identifier = 60 */
	if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
		*e++ = 60;
		*e++ = strlen (ptr);
		while (*ptr)
			*e++ = *ptr++;
	}
	/* my DHCP_CLIENT_IDENTIFIER = 61 */
	if ((ptr = getenv ("dhcp_client_id"))) {
		*e++ = 61;
		*e++ = strlen (ptr);
		while (*ptr)
			*e++ = *ptr++;
	}
	return e;
}

u8 *dhcp_vendorex_proc (u8 * popt)
{
	return NULL;
}

/* ------------------------------------------------------------------------- */

/*
 * Initialize PCI Devices
 */
#ifdef CONFIG_PCI
void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
{
	u32 cnt;

	printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
		PCI_FUNC (dev));
	for (cnt = 0; cnt < 6; cnt++)
		pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
					     0x0);
	printf ("done\n");
}

void duart_setup (u32 base, u16 divisor)
{
	printf ("duart setup ...");
	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
	out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
	out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
	out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
	out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
	printf ("done\n");
}

void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
					 pci_dev_t bridge, unsigned char irq)
{
	pci_dev_t d;
	unsigned char bus;
	unsigned short vendor, class;

	pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
	for (d = PCI_BDF (bus, 0, 0);
	     d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
			  PCI_MAX_PCI_FUNCTIONS - 1);
	     d += PCI_BDF (0, 0, 1)) {
		pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
		if (vendor != 0xffff && vendor != 0x0000) {
			pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
						   &class);
			if (class == PCI_CLASS_BRIDGE_PCI)
				pci_mvblue_fixup_irq_behind_bridge (hose, d,
								    irq);
			else
				pci_hose_write_config_byte (hose, d,
							    PCI_INTERRUPT_LINE,
							    irq);
		}
	}
}

#define MV_MAX_PCI_BUSSES	3
#define SLOT0_IRQ	3
#define SLOT1_IRQ	4
void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
	unsigned char line = 0xff;
	unsigned short class;

	if (PCI_BUS (dev) == 0) {
		switch (PCI_DEV (dev)) {
		case 0xd:
			if (get_BoardType () == 0) {
				line = 1;
			} else
				/* mvBL */
				line = 2;
			break;
		case 0xe:
			/* mvBB: IDE */
			line = 2;
			pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
			break;
		case 0xf:
			/* mvBB: Slot0 (Grabber) */
			pci_hose_read_config_word (hose, dev,
						   PCI_CLASS_DEVICE, &class);
			if (class == PCI_CLASS_BRIDGE_PCI) {
				pci_mvblue_fixup_irq_behind_bridge (hose, dev,
								    SLOT0_IRQ);
				line = 0xff;
			} else
				line = SLOT0_IRQ;
			break;
		case 0x10:
			/* mvBB: Slot1 */
			pci_hose_read_config_word (hose, dev,
						   PCI_CLASS_DEVICE, &class);
			if (class == PCI_CLASS_BRIDGE_PCI) {
				pci_mvblue_fixup_irq_behind_bridge (hose, dev,
								    SLOT1_IRQ);
				line = 0xff;
			} else
				line = SLOT1_IRQ;
			break;
		default:
			printf ("***pci_scan: illegal dev = 0x%08x\n",
				PCI_DEV (dev));
			line = 0xff;
			break;
		}
		pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
					    line);
	}
}

struct pci_controller hose = {
	fixup_irq:pci_mvblue_fixup_irq
};

void pci_init_board (void)
{
	pci_mpc824x_init (&hose);
}
#endif
Commit	Line	Data
b4676a25 WD	1	/*
	2	* GNU General Public License for more details.
	3	*
	4	* MATRIX Vision GmbH / June 2002-Nov 2003
	5	* Andre Schwarz
	6	*/
	7
	8	#include <common.h>
	9	#include <mpc824x.h>
	10	#include <asm/io.h>
	11	#include <ns16550.h>
	12
	13	#ifdef CONFIG_PCI
d4ca31c4	14	#include <pci.h>
b4676a25 WD	15	#endif
b4676a25 WD	16
d4ca31c4	17	u32 get_BoardType (void);
b4676a25 WD	18
b4676a25 WD	19	#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 \| ((b&0xff)<<16) \
d4ca31c4 WD	20	\| ((d&0x1f)<<11) \
	21	\| ((f&0x7)<<7) \
	22	\| (r&0xfc) )
b4676a25	23
d4ca31c4	24	int mv_pci_read (int bus, int dev, int func, int reg)
b4676a25	25	{
d4ca31c4 WD	26	(u32 ) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
	27	asm ("sync");
	28	return cpu_to_le32 ((u32 ) (0xfee00cfc));
b4676a25	29	}
d4ca31c4 WD	30
	31	u32 get_BoardType ()
	32	{
	33	return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
b4676a25 WD	34	}
b4676a25 WD	35
d4ca31c4	36	void init_2nd_DUART (void)
b4676a25	37	{
d4ca31c4	38	NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
b4676a25	39	int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
d4ca31c4 WD	40
	41	(u8 ) (0xfc004511) = 0x1;
	42	NS16550_init (console, clock_divisor);
b4676a25	43	}
d4ca31c4	44	void hw_watchdog_reset (void)
b4676a25	45	{
d4ca31c4 WD	46	if (get_BoardType () == 0) {
	47	(u32 ) (0xff000005) = 0;
	48	asm ("sync");
b4676a25 WD	49	}
	50	}
	51	int checkboard (void)
	52	{
	53	DECLARE_GLOBAL_DATA_PTR;
d4ca31c4 WD	54	ulong busfreq = get_bus_freq (0);
	55	char buf[32];
	56	u32 BoardType = get_BoardType ();
b4676a25 WD	57	char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
	58	char *p;
	59	bd_t *bd = gd->bd;
	60
d4ca31c4 WD	61	hw_watchdog_reset ();
	62
	63	printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
	64	printf (" Found %s running at %s MHz memory clock.\n",
	65	BoardName[BoardType], strmhz (buf, busfreq));
b4676a25	66
d4ca31c4	67	init_2nd_DUART ();
b4676a25	68
d4ca31c4 WD	69	if ((p = getenv ("console_nr")) != NULL) {
d4ca31c4 WD	70	unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
b4676a25	71
d4ca31c4 WD	72	bd->bi_baudrate &= ~3;
d4ca31c4 WD	73	bd->bi_baudrate \|= con_nr & 3;
b4676a25 WD	74	}
	75	return 0;
	76	}
	77
	78	long int initdram (int board_type)
	79	{
d4ca31c4 WD	80	int i, cnt;
	81	volatile uchar *base = CFG_SDRAM_BASE;
	82	volatile ulong *addr;
	83	ulong save[32];
	84	ulong val, ret = 0;
	85
	86	for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
	87	cnt >>= 1) {
	88	addr = (volatile ulong *) base + cnt;
b4676a25 WD	89	save[i++] = *addr;
	90	*addr = ~cnt;
	91	}
	92
d4ca31c4	93	addr = (volatile ulong *) base;
b4676a25 WD	94	save[i] = *addr;
	95	*addr = 0;
	96
	97	if (*addr != 0) {
	98	*addr = save[i];
	99	goto Done;
	100	}
	101
d4ca31c4 WD	102	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
d4ca31c4 WD	103	addr = (volatile ulong *) base + cnt;
b4676a25 WD	104	val = *addr;
	105	*addr = save[--i];
	106	if (val != ~cnt) {
d4ca31c4 WD	107	ulong new_bank0_end = cnt * sizeof (long) - 1;
	108	ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
	109	ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
	110
	111	mear1 = (mear1 & 0xFFFFFF00) \|
	112	((new_bank0_end & MICR_ADDR_MASK) >>
	113	MICR_ADDR_SHIFT);
b4676a25	114	emear1 = (emear1 & 0xFFFFFF00) \|
d4ca31c4 WD	115	((new_bank0_end & MICR_ADDR_MASK) >>
	116	MICR_EADDR_SHIFT);
	117	mpc824x_mpc107_setreg (MEAR1, mear1);
	118	mpc824x_mpc107_setreg (EMEAR1, emear1);
	119	ret = cnt * sizeof (long);
b4676a25 WD	120	goto Done;
	121	}
	122	}
	123
	124	ret = CFG_MAX_RAM_SIZE;
d4ca31c4	125	Done:
b4676a25 WD	126	return ret;
	127	}
	128
	129	/* ------------------------------------------------------------------------- */
d4ca31c4	130	u8 dhcp_vendorex_prep (u8 e)
b4676a25	131	{
d4ca31c4	132	char *ptr;
b4676a25 WD	133
b4676a25 WD	134	/* DHCP vendor-class-identifier = 60 */
d4ca31c4 WD	135	if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
	136	*e++ = 60;
	137	*e++ = strlen (ptr);
	138	while (*ptr)
	139	e++ = ptr++;
	140	}
b4676a25	141	/* my DHCP_CLIENT_IDENTIFIER = 61 */
d4ca31c4 WD	142	if ((ptr = getenv ("dhcp_client_id"))) {
	143	*e++ = 61;
	144	*e++ = strlen (ptr);
	145	while (*ptr)
	146	e++ = ptr++;
	147	}
	148	return e;
b4676a25	149	}
d4ca31c4 WD	150
d4ca31c4 WD	151	u8 dhcp_vendorex_proc (u8 popt)
b4676a25	152	{
d4ca31c4	153	return NULL;
b4676a25	154	}
d4ca31c4	155
b4676a25 WD	156	/* ------------------------------------------------------------------------- */
	157
	158	/*
	159	* Initialize PCI Devices
	160	*/
	161	#ifdef CONFIG_PCI
d4ca31c4	162	void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
b4676a25 WD	163	{
b4676a25 WD	164	u32 cnt;
d4ca31c4 WD	165
	166	printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
	167	PCI_FUNC (dev));
	168	for (cnt = 0; cnt < 6; cnt++)
	169	pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
	170	0x0);
	171	printf ("done\n");
b4676a25 WD	172	}
b4676a25 WD	173
d4ca31c4	174	void duart_setup (u32 base, u16 divisor)
b4676a25	175	{
d4ca31c4 WD	176	printf ("duart setup ...");
	177	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
	178	out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
	179	out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
	180	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
	181	out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
	182	out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
	183	printf ("done\n");
b4676a25 WD	184	}
b4676a25 WD	185
d4ca31c4 WD	186	void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
d4ca31c4 WD	187	pci_dev_t bridge, unsigned char irq)
b4676a25 WD	188	{
b4676a25 WD	189	pci_dev_t d;
d4ca31c4 WD	190	unsigned char bus;
	191	unsigned short vendor, class;
	192
	193	pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
	194	for (d = PCI_BDF (bus, 0, 0);
	195	d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
	196	PCI_MAX_PCI_FUNCTIONS - 1);
	197	d += PCI_BDF (0, 0, 1)) {
	198	pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
	199	if (vendor != 0xffff && vendor != 0x0000) {
	200	pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
	201	&class);
	202	if (class == PCI_CLASS_BRIDGE_PCI)
	203	pci_mvblue_fixup_irq_behind_bridge (hose, d,
	204	irq);
b4676a25	205	else
d4ca31c4 WD	206	pci_hose_write_config_byte (hose, d,
	207	PCI_INTERRUPT_LINE,
	208	irq);
b4676a25 WD	209	}
	210	}
	211	}
	212
	213	#define MV_MAX_PCI_BUSSES 3
	214	#define SLOT0_IRQ 3
	215	#define SLOT1_IRQ 4
d4ca31c4	216	void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
b4676a25	217	{
d4ca31c4 WD	218	unsigned char line = 0xff;
d4ca31c4 WD	219	unsigned short class;
b4676a25	220
d4ca31c4 WD	221	if (PCI_BUS (dev) == 0) {
	222	switch (PCI_DEV (dev)) {
	223	case 0xd:
	224	if (get_BoardType () == 0) {
b4676a25 WD	225	line = 1;
	226	} else
	227	/* mvBL */
d4ca31c4 WD	228	line = 2;
	229	break;
	230	case 0xe:
b4676a25 WD	231	/* mvBB: IDE */
b4676a25 WD	232	line = 2;
d4ca31c4	233	pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
b4676a25 WD	234	break;
	235	case 0xf:
	236	/* mvBB: Slot0 (Grabber) */
d4ca31c4 WD	237	pci_hose_read_config_word (hose, dev,
	238	PCI_CLASS_DEVICE, &class);
	239	if (class == PCI_CLASS_BRIDGE_PCI) {
	240	pci_mvblue_fixup_irq_behind_bridge (hose, dev,
	241	SLOT0_IRQ);
b4676a25 WD	242	line = 0xff;
	243	} else
	244	line = SLOT0_IRQ;
	245	break;
	246	case 0x10:
	247	/* mvBB: Slot1 */
d4ca31c4 WD	248	pci_hose_read_config_word (hose, dev,
	249	PCI_CLASS_DEVICE, &class);
	250	if (class == PCI_CLASS_BRIDGE_PCI) {
	251	pci_mvblue_fixup_irq_behind_bridge (hose, dev,
	252	SLOT1_IRQ);
b4676a25 WD	253	line = 0xff;
	254	} else
	255	line = SLOT1_IRQ;
	256	break;
d4ca31c4 WD	257	default:
	258	printf ("***pci_scan: illegal dev = 0x%08x\n",
	259	PCI_DEV (dev));
b4676a25 WD	260	line = 0xff;
b4676a25 WD	261	break;
d4ca31c4 WD	262	}
	263	pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
	264	line);
b4676a25 WD	265	}
	266	}
	267
	268	struct pci_controller hose = {
d4ca31c4	269	fixup_irq:pci_mvblue_fixup_irq
b4676a25 WD	270	};
b4676a25 WD	271
d4ca31c4	272	void pci_init_board (void)
b4676a25	273	{
d4ca31c4	274	pci_mpc824x_init (&hose);
b4676a25 WD	275	}
b4676a25 WD	276	#endif