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Commit | Line | Data |
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2d24a3a7 WD |
1 | /* |
2 | * board/mx1ads/mx1ads.c | |
49822e23 | 3 | * |
2d24a3a7 WD |
4 | * (c) Copyright 2004 |
5 | * Techware Information Technology, Inc. | |
6 | * http://www.techware.com.tw/ | |
7 | * | |
8 | * Ming-Len Wu <minglen_wu@techware.com.tw> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
2d24a3a7 WD |
11 | */ |
12 | ||
2d24a3a7 | 13 | #include <common.h> |
b1c0eaac | 14 | #include <netdev.h> |
281e00a3 | 15 | /*#include <mc9328.h>*/ |
86c98882 | 16 | #include <asm/arch/imx-regs.h> |
5076c7ab | 17 | #include <asm/io.h> |
2d24a3a7 | 18 | |
d87080b7 | 19 | DECLARE_GLOBAL_DATA_PTR; |
2d24a3a7 WD |
20 | |
21 | #define FCLK_SPEED 1 | |
22 | ||
23 | #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ | |
24 | #define M_MDIV 0xC3 | |
25 | #define M_PDIV 0x4 | |
26 | #define M_SDIV 0x1 | |
27 | #elif FCLK_SPEED==1 /* Fout = 202.8MHz */ | |
28 | #define M_MDIV 0xA1 | |
29 | #define M_PDIV 0x3 | |
30 | #define M_SDIV 0x1 | |
31 | #endif | |
32 | ||
33 | #define USB_CLOCK 1 | |
34 | ||
35 | #if USB_CLOCK==0 | |
36 | #define U_M_MDIV 0xA1 | |
37 | #define U_M_PDIV 0x3 | |
38 | #define U_M_SDIV 0x1 | |
39 | #elif USB_CLOCK==1 | |
40 | #define U_M_MDIV 0x48 | |
41 | #define U_M_PDIV 0x3 | |
42 | #define U_M_SDIV 0x2 | |
43 | #endif | |
44 | ||
45 | #if 0 | |
46 | ||
d87080b7 WD |
47 | static inline void delay (unsigned long loops) |
48 | { | |
2d24a3a7 | 49 | __asm__ volatile ("1:\n" |
d87080b7 WD |
50 | "subs %0, %1, #1\n" |
51 | "bne 1b":"=r" (loops):"0" (loops)); | |
2d24a3a7 WD |
52 | } |
53 | ||
49822e23 | 54 | #endif |
2d24a3a7 WD |
55 | |
56 | /* | |
57 | * Miscellaneous platform dependent initialisations | |
58 | */ | |
59 | ||
d87080b7 WD |
60 | void SetAsynchMode (void) |
61 | { | |
62 | __asm__ ("mrc p15,0,r0,c1,c0,0 \n" | |
63 | "mov r2, #0xC0000000 \n" | |
64 | "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n"); | |
2d24a3a7 | 65 | } |
49822e23 | 66 | |
2d24a3a7 WD |
67 | static u32 mc9328sid; |
68 | ||
e845f900 | 69 | int board_early_init_f(void) |
d87080b7 | 70 | { |
d87080b7 | 71 | mc9328sid = SIDR; |
2d24a3a7 | 72 | |
d87080b7 | 73 | GPCR = 0x000003AB; /* I/O pad driving strength */ |
2d24a3a7 | 74 | |
53677ef1 WD |
75 | /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ |
76 | /* MX1_CS1L = 0x11110601; */ | |
2d24a3a7 | 77 | |
d87080b7 | 78 | MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ |
2d24a3a7 WD |
79 | |
80 | /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and | |
81 | * BCLK divider to 2 (i.e. BCLK to 48 MHz) | |
82 | */ | |
d87080b7 | 83 | CSCR = 0xAF000403; |
2d24a3a7 | 84 | |
d87080b7 WD |
85 | CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ |
86 | CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ | |
2d24a3a7 WD |
87 | |
88 | /* setup cs4 for cs8900 ethernet */ | |
49822e23 | 89 | |
d87080b7 WD |
90 | CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ |
91 | CS4L = 0x00001501; | |
49822e23 | 92 | |
d87080b7 WD |
93 | GIUS (0) &= 0xFF3FFFFF; |
94 | GPR (0) &= 0xFF3FFFFF; | |
49822e23 | 95 | |
5076c7ab AG |
96 | readl(0x1500000C); |
97 | readl(0x1500000C); | |
2d24a3a7 | 98 | |
d87080b7 | 99 | SetAsynchMode (); |
2d24a3a7 | 100 | |
d87080b7 WD |
101 | icache_enable (); |
102 | dcache_enable (); | |
2d24a3a7 WD |
103 | |
104 | /* set PERCLKs */ | |
d87080b7 | 105 | PCDR = 0x00000055; /* set PERCLKS */ |
49822e23 WD |
106 | |
107 | /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes | |
108 | * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place | |
2d24a3a7 WD |
109 | * all sources selected as normal interrupt |
110 | */ | |
2d24a3a7 | 111 | |
281e00a3 WD |
112 | /* MX1_INTTYPEH = 0; |
113 | MX1_INTTYPEL = 0; | |
114 | */ | |
2d24a3a7 WD |
115 | return 0; |
116 | } | |
117 | ||
e845f900 FE |
118 | int board_init(void) |
119 | { | |
120 | gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; | |
121 | ||
122 | gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
d87080b7 WD |
127 | int board_late_init (void) |
128 | { | |
129 | ||
130 | setenv ("stdout", "serial"); | |
131 | setenv ("stderr", "serial"); | |
132 | ||
133 | switch (mc9328sid) { | |
134 | case 0x0005901d: | |
135 | printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n", | |
136 | mc9328sid); | |
137 | break; | |
138 | case 0x04d4c01d: | |
139 | printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n", | |
140 | mc9328sid); | |
141 | break; | |
142 | case 0x00d4c01d: | |
143 | printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n", | |
144 | mc9328sid); | |
145 | break; | |
146 | ||
147 | default: | |
148 | printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n", | |
149 | mc9328sid); | |
150 | break; | |
2d24a3a7 | 151 | } |
2d24a3a7 | 152 | return 0; |
49822e23 WD |
153 | } |
154 | ||
e845f900 FE |
155 | int dram_init(void) |
156 | { | |
157 | /* dram_init must store complete ramsize in gd->ram_size */ | |
a55d23cc | 158 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, |
e845f900 FE |
159 | PHYS_SDRAM_1_SIZE); |
160 | return 0; | |
161 | } | |
162 | ||
163 | void dram_init_banksize(void) | |
d87080b7 | 164 | { |
2d24a3a7 | 165 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
d87080b7 | 166 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
2d24a3a7 | 167 | } |
b1c0eaac BW |
168 | |
169 | #ifdef CONFIG_CMD_NET | |
170 | int board_eth_init(bd_t *bis) | |
171 | { | |
172 | int rc = 0; | |
173 | #ifdef CONFIG_CS8900 | |
174 | rc = cs8900_initialize(0, CONFIG_CS8900_BASE); | |
175 | #endif | |
176 | return rc; | |
177 | } | |
178 | #endif |