]>
Commit | Line | Data |
---|---|---|
2d24a3a7 WD |
1 | /* |
2 | * board/mx1ads/syncflash.c | |
49822e23 | 3 | * |
2d24a3a7 WD |
4 | * (c) Copyright 2004 |
5 | * Techware Information Technology, Inc. | |
6 | * http://www.techware.com.tw/ | |
7 | * | |
8 | * Ming-Len Wu <minglen_wu@techware.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <mc9328.h> | |
28 | ||
29 | typedef unsigned long * p_u32; | |
30 | ||
31 | /* 4Mx16x2 IAM=0 CSD1 */ | |
32 | ||
33 | flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
34 | ||
35 | /* Following Setting is for CSD1 */ | |
b54d32b4 WD |
36 | #define SFCTL 0x00221004 |
37 | #define reg_SFCTL __REG(SFCTL) | |
2d24a3a7 | 38 | |
b54d32b4 | 39 | #define SYNCFLASH_A10 (0x00100000) |
2d24a3a7 | 40 | |
b54d32b4 WD |
41 | #define CMD_NORMAL (0x81020300) /* Normal Mode */ |
42 | #define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ | |
43 | #define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ | |
44 | #define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ | |
45 | #define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ | |
46 | #define CMD_PROGRAM (CMD_NORMAL + 0x70000000) | |
2d24a3a7 | 47 | |
b54d32b4 | 48 | #define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ |
2d24a3a7 WD |
49 | |
50 | /* LCR Command */ | |
b54d32b4 WD |
51 | #define LCR_READSTATUS (0x0001C000) /* 0x70 */ |
52 | #define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ | |
53 | #define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ | |
54 | #define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ | |
55 | #define LCR_SR_CLEAR (0x00014000) /* 0x50 */ | |
2d24a3a7 WD |
56 | |
57 | ||
58 | /* Get Status register */ | |
59 | u32 SF_SR(void) { | |
60 | u32 tmp,tmp1; | |
61 | ||
62 | reg_SFCTL = CMD_PROGRAM; | |
63 | tmp = __REG(CFG_FLASH_BASE); | |
49822e23 | 64 | |
2d24a3a7 WD |
65 | reg_SFCTL = CMD_NORMAL; |
66 | ||
67 | reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ | |
68 | tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR); | |
69 | ||
70 | return tmp; | |
71 | } | |
72 | ||
73 | /* check if SyncFlash is ready */ | |
74 | u8 SF_Ready(void) { | |
75 | u32 tmp; | |
76 | ||
77 | tmp = SF_SR(); | |
78 | ||
79 | if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { | |
80 | printf ("SyncFlash Error code %08x\n",tmp); | |
81 | }; | |
82 | ||
83 | if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { | |
84 | printf ("SyncFlash Error code %08x\n",tmp); | |
85 | ||
86 | }; | |
87 | ||
88 | if (tmp == 0x00800080) /* Test Bit 7 of SR */ | |
89 | return 1; | |
90 | else | |
91 | return 0; | |
92 | } | |
93 | ||
94 | /* Issue the precharge all command */ | |
95 | void SF_PrechargeAll(void) { | |
96 | ||
97 | u32 tmp; | |
98 | ||
99 | reg_SFCTL = CMD_PREC; /* Set Precharge Command */ | |
49822e23 | 100 | tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ |
2d24a3a7 WD |
101 | |
102 | } | |
103 | ||
104 | /* set SyncFlash to normal mode */ | |
105 | void SF_Normal(void) { | |
106 | ||
107 | SF_PrechargeAll(); | |
49822e23 | 108 | |
2d24a3a7 WD |
109 | reg_SFCTL = CMD_NORMAL; |
110 | } | |
111 | ||
112 | /* Erase SyncFlash */ | |
113 | void SF_Erase(u32 RowAddress) { | |
114 | u32 tmp; | |
115 | ||
116 | reg_SFCTL = CMD_NORMAL; | |
117 | tmp = __REG(RowAddress); | |
118 | ||
119 | reg_SFCTL = CMD_PREC; | |
120 | tmp = __REG(RowAddress); | |
49822e23 | 121 | |
2d24a3a7 WD |
122 | reg_SFCTL = CMD_LCR; /* Set LCR mode */ |
123 | __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ | |
49822e23 | 124 | |
2d24a3a7 WD |
125 | reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ |
126 | __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ | |
127 | ||
128 | while(!SF_Ready()); | |
129 | } | |
130 | ||
131 | ||
132 | void SF_NvmodeErase(void) { | |
133 | SF_PrechargeAll(); | |
134 | ||
135 | reg_SFCTL = CMD_LCR; /* Set to LCR mode */ | |
136 | __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ | |
49822e23 | 137 | |
2d24a3a7 WD |
138 | reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ |
139 | __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ | |
140 | ||
141 | while(!SF_Ready()); | |
142 | } | |
143 | ||
144 | void SF_NvmodeWrite(void) { | |
145 | SF_PrechargeAll(); | |
146 | ||
147 | reg_SFCTL = CMD_LCR; /* Set to LCR mode */ | |
148 | __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ | |
49822e23 | 149 | |
2d24a3a7 WD |
150 | reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ |
151 | __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ | |
152 | ||
153 | } | |
154 | ||
155 | ||
156 | /****************************************************************************************/ | |
157 | ||
158 | ulong flash_init(void) { | |
159 | int i, j; | |
160 | u32 tmp; | |
161 | ||
162 | /* Turn on CSD1 for negating RESETSF of SyncFLash */ | |
163 | ||
164 | reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ | |
165 | udelay(200); | |
166 | ||
167 | reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ | |
168 | tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ | |
169 | ||
170 | SF_Normal(); | |
49822e23 | 171 | |
2d24a3a7 WD |
172 | i = 0; |
173 | ||
174 | flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; | |
49822e23 | 175 | |
2d24a3a7 WD |
176 | flash_info[i].size = FLASH_BANK_SIZE; |
177 | flash_info[i].sector_count = CFG_MAX_FLASH_SECT; | |
178 | ||
179 | memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); | |
180 | ||
181 | for (j = 0; j < flash_info[i].sector_count; j++) { | |
182 | flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000; | |
183 | } | |
49822e23 | 184 | |
2d24a3a7 WD |
185 | flash_protect(FLAG_PROTECT_SET, |
186 | CFG_FLASH_BASE, | |
187 | CFG_FLASH_BASE + monitor_flash_len - 1, | |
188 | &flash_info[0]); | |
189 | ||
190 | flash_protect(FLAG_PROTECT_SET, | |
191 | CFG_ENV_ADDR, | |
192 | CFG_ENV_ADDR + CFG_ENV_SIZE - 1, | |
193 | &flash_info[0]); | |
194 | ||
195 | return FLASH_BANK_SIZE; | |
196 | } | |
197 | ||
198 | ||
199 | void flash_print_info (flash_info_t *info) { | |
200 | ||
201 | int i; | |
202 | ||
203 | switch (info->flash_id & FLASH_VENDMASK) { | |
204 | case (FLASH_MAN_MT & FLASH_VENDMASK): | |
205 | printf("Micron: "); | |
206 | break; | |
207 | default: | |
208 | printf("Unknown Vendor "); | |
209 | break; | |
210 | } | |
49822e23 WD |
211 | |
212 | ||
2d24a3a7 WD |
213 | switch (info->flash_id & FLASH_TYPEMASK) { |
214 | case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): | |
215 | printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); | |
216 | break; | |
217 | default: | |
218 | printf("Unknown Chip Type\n"); | |
219 | return; | |
220 | break; | |
221 | } | |
222 | ||
223 | printf(" Size: %ld MB in %d Sectors\n", | |
224 | info->size >> 20, info->sector_count); | |
225 | ||
226 | printf(" Sector Start Addresses: "); | |
227 | ||
228 | for (i = 0; i < info->sector_count; i++) { | |
49822e23 | 229 | if ((i % 5) == 0) |
2d24a3a7 WD |
230 | printf ("\n "); |
231 | ||
232 | printf (" %08lX%s", info->start[i], | |
233 | info->protect[i] ? " (RO)" : " "); | |
234 | } | |
49822e23 | 235 | |
2d24a3a7 WD |
236 | printf ("\n"); |
237 | } | |
238 | ||
239 | ||
240 | /*-----------------------------------------------------------------------*/ | |
241 | ||
242 | int flash_erase (flash_info_t *info, int s_first, int s_last) { | |
243 | int iflag, cflag, prot, sect; | |
244 | int rc = ERR_OK; | |
245 | ||
246 | /* first look for protection bits */ | |
247 | ||
248 | if (info->flash_id == FLASH_UNKNOWN) | |
249 | return ERR_UNKNOWN_FLASH_TYPE; | |
250 | ||
49822e23 | 251 | if ((s_first < 0) || (s_first > s_last)) |
2d24a3a7 WD |
252 | return ERR_INVAL; |
253 | ||
49822e23 | 254 | if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) |
2d24a3a7 WD |
255 | return ERR_UNKNOWN_FLASH_VENDOR; |
256 | ||
257 | prot = 0; | |
258 | ||
259 | for (sect = s_first; sect <= s_last; ++sect) { | |
49822e23 | 260 | if (info->protect[sect]) |
2d24a3a7 WD |
261 | prot++; |
262 | } | |
49822e23 | 263 | |
2d24a3a7 WD |
264 | if (prot) { |
265 | printf("protected!\n"); | |
266 | return ERR_PROTECTED; | |
267 | } | |
268 | /* | |
269 | * Disable interrupts which might cause a timeout | |
270 | * here. Remember that our exception vectors are | |
271 | * at address 0 in the flash, and we don't want a | |
272 | * (ticker) exception to happen while the flash | |
273 | * chip is in programming mode. | |
274 | */ | |
275 | ||
276 | cflag = icache_status(); | |
277 | icache_disable(); | |
278 | iflag = disable_interrupts(); | |
279 | ||
280 | /* Start erase on unprotected sectors */ | |
281 | for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { | |
49822e23 | 282 | |
2d24a3a7 WD |
283 | printf("Erasing sector %2d ... ", sect); |
284 | ||
285 | /* arm simple, non interrupt dependent timer */ | |
286 | ||
287 | reset_timer_masked(); | |
288 | ||
289 | SF_NvmodeErase(); | |
290 | SF_NvmodeWrite(); | |
291 | ||
292 | SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect)); | |
293 | SF_Normal(); | |
294 | ||
295 | printf("ok.\n"); | |
296 | } | |
297 | ||
298 | if (ctrlc()) | |
299 | printf("User Interrupt!\n"); | |
300 | ||
301 | if (iflag) | |
302 | enable_interrupts(); | |
303 | ||
304 | if (cflag) | |
305 | icache_enable(); | |
306 | ||
307 | return rc; | |
308 | } | |
309 | ||
2d24a3a7 WD |
310 | /*----------------------------------------------------------------------- |
311 | * Copy memory to flash. | |
312 | */ | |
313 | ||
314 | int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { | |
315 | int i; | |
316 | ||
49822e23 | 317 | for(i = 0; i < cnt; i += 4) { |
2d24a3a7 WD |
318 | |
319 | SF_PrechargeAll(); | |
320 | ||
321 | reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ | |
322 | __REG(addr + i) = __REG((u32)src + i); | |
323 | ||
324 | while(!SF_Ready()); | |
325 | } | |
326 | ||
327 | SF_Normal(); | |
49822e23 | 328 | |
2d24a3a7 WD |
329 | return ERR_OK; |
330 | } |