[people/ms/u-boot.git] / board / nc650 / nc650.c

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <config.h>
#include <mpc8xx.h>

/*
 *  Memory Controller Using
 *
 *  CS0 - Flash memory            (0x40000000)
 *  CS3 - SDRAM                   (0x00000000}
 */

/* ------------------------------------------------------------------------- */

#define _not_used_	0xffffffff

const uint sdram_table[] = {
	/* single read. (offset 0 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	0x1ff77c47,

	/* MRS initialization (offset 5) */

	0x1ff77c34, 0xefeabc34, 0x1fb57c35,

	/* burst read. (offset 8 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* single write. (offset 18 in upm RAM) */
	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* burst write. (offset 20 in upm RAM) */
	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* refresh. (offset 30 in upm RAM) */
	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* exception. (offset 3c in upm RAM) */
	0x7ffffc07, _not_used_, _not_used_, _not_used_
};

const uint nand_flash_table[] = {
	/* single read. (offset 0 in upm RAM) */
	0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
	0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,

	/* burst read. (offset 8 in upm RAM) */
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,

	/* single write. (offset 18 in upm RAM) */
	0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
	0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,

	/* burst write. (offset 20 in upm RAM) */
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,

	/* refresh. (offset 30 in upm RAM) */
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,

	/* exception. (offset 3c in upm RAM) */
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
};

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 */

int checkboard (void)
{
	puts ("Board: NC650\n");
	return 0;
}

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size8, size9;
	long int size_b0 = 0;
	unsigned long reg;

	upmconfig (UPMA, (uint *) sdram_table,
			   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;

	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller bank 1 to the SDRAM bank at
	 * preliminary address - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or3 = CFG_OR3_PRELIM;
	memctl->memc_br3 = CFG_BR3_PRELIM;

	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 0 */
	udelay (200);
	memctl->memc_mcr = 0x80006230;	/* SDRAM bank 0 - execute twice */
	udelay (200);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
					   SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
					  SDRAM_MAX_SIZE);

	udelay (1000);

	if (size8 < size9) {
		size_b0 = size9;
	} else {
		size_b0 = size8;
		memctl->memc_mamr = CFG_MAMR_8COL;
		udelay (500);
	}

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks.
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if ((size_b0 < 0x02000000)) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
		udelay (1000);
	}

	/*
	 * Final mapping
	 */

	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

	/* adjust refresh rate depending on SDRAM type, one bank */
	reg = memctl->memc_mptpr;
	reg >>= 1;					/* reduce to CFG_MPTPR_1BK_8K / _4K */
	memctl->memc_mptpr = reg;

	udelay (10000);

	/* Configure UPMB for NAND flash access */
	upmconfig (UPMB, (uint *) nand_flash_table,
			   sizeof (nand_flash_table) / sizeof (uint));

	memctl->memc_mbmr = CFG_MBMR_NAND;

	return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size(base, maxsize));
}

#if (CONFIG_COMMANDS & CFG_CMD_NAND)
void nand_init(void)
{
	extern unsigned long nand_probe(unsigned long physadr);

	unsigned long totlen = nand_probe(CFG_NAND_BASE);

	printf ("%4lu MB\n", totlen >> 20);
}
#endif
Commit	Line	Data
7ca202f5 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <config.h>
	26	#include <mpc8xx.h>
	27
	28	/*
	29	* Memory Controller Using
	30	*
	31	* CS0 - Flash memory (0x40000000)
	32	* CS3 - SDRAM (0x00000000}
	33	*/
	34
	35	/* ------------------------------------------------------------------------- */
	36
	37	#define _not_used_ 0xffffffff
	38
	39	const uint sdram_table[] = {
	40	/* single read. (offset 0 in upm RAM) */
	41	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	42	0x1ff77c47,
	43
	44	/* MRS initialization (offset 5) */
	45
	46	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
	47
	48	/* burst read. (offset 8 in upm RAM) */
	49	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	50	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	51	_not_used_, _not_used_, _not_used_, _not_used_,
	52	_not_used_, _not_used_, _not_used_, _not_used_,
	53
	54	/* single write. (offset 18 in upm RAM) */
	55	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	56	_not_used_, _not_used_, _not_used_, _not_used_,
	57
	58	/* burst write. (offset 20 in upm RAM) */
	59	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	60	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	61	_not_used_, _not_used_, _not_used_, _not_used_,
	62	_not_used_, _not_used_, _not_used_, _not_used_,
	63
	64	/* refresh. (offset 30 in upm RAM) */
65	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
66	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
67	_not_used_, _not_used_, _not_used_, _not_used_,
68
69	/* exception. (offset 3c in upm RAM) */
70	0x7ffffc07, _not_used_, _not_used_, _not_used_
71	};
72
c3fafecf WD	73	const uint nand_flash_table[] = {
	74	/* single read. (offset 0 in upm RAM) */
	75	0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
	76	0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
	77
	78	/* burst read. (offset 8 in upm RAM) */
	79	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	80	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	81	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	82	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	83
	84	/* single write. (offset 18 in upm RAM) */
	85	0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
	86	0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
	87
	88	/* burst write. (offset 20 in upm RAM) */
	89	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	90	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	91	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	92	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	93
	94	/* refresh. (offset 30 in upm RAM) */
	95	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	96	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	97	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	98
	99	/* exception. (offset 3c in upm RAM) */
	100	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
	101	};
	102
7ca202f5 WD	103	/* ------------------------------------------------------------------------- */
	104
	105	/*
	106	* Check Board Identity:
	107	*/
	108
	109	int checkboard (void)
	110	{
	111	puts ("Board: NC650\n");
	112	return 0;
	113	}
	114
	115	/* ------------------------------------------------------------------------- */
	116
	117	static long int dram_size (long int, long int *, long int);
	118
	119	/* ------------------------------------------------------------------------- */
	120
	121	long int initdram (int board_type)
	122	{
	123	volatile immap_t immap = (immap_t ) CFG_IMMR;
	124	volatile memctl8xx_t *memctl = &immap->im_memctl;
	125	long int size8, size9;
	126	long int size_b0 = 0;
	127	unsigned long reg;
	128
	129	upmconfig (UPMA, (uint *) sdram_table,
	130	sizeof (sdram_table) / sizeof (uint));
	131
	132	/*
	133	* Preliminary prescaler for refresh (depends on number of
	134	* banks): This value is selected for four cycles every 62.4 us
	135	* with two SDRAM banks or four cycles every 31.2 us with one
	136	* bank. It will be adjusted after memory sizing.
	137	*/
	138	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
	139
	140	memctl->memc_mar = 0x00000088;
	141
	142	/*
	143	* Map controller bank 1 to the SDRAM bank at
	144	* preliminary address - these have to be modified after the
	145	* SDRAM size has been determined.
	146	*/
	147	memctl->memc_or3 = CFG_OR3_PRELIM;
	148	memctl->memc_br3 = CFG_BR3_PRELIM;
	149
	150	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
	151
	152	udelay (200);
	153
	154	/* perform SDRAM initializsation sequence */
	155
	156	memctl->memc_mcr = 0x80006105; /* SDRAM bank 0 */
	157	udelay (200);
	158	memctl->memc_mcr = 0x80006230; /* SDRAM bank 0 - execute twice */
	159	udelay (200);
	160
	161	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	162
	163	udelay (1000);
	164
	165	/*
	166	* Check Bank 0 Memory Size for re-configuration
167	*
168	* try 8 column mode
169	*/
170	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
171	SDRAM_MAX_SIZE);
172
173	udelay (1000);
174
175	/*
176	* try 9 column mode
177	*/
178	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
179	SDRAM_MAX_SIZE);
180
181	udelay (1000);
182
183	if (size8 < size9) {
184	size_b0 = size9;
185	} else {
186	size_b0 = size8;
187	memctl->memc_mamr = CFG_MAMR_8COL;
188	udelay (500);
189	}
190
191	/*
192	* Adjust refresh rate depending on SDRAM type, both banks.
193	* For types > 128 MBit leave it at the current (fast) rate
194	*/
195	if ((size_b0 < 0x02000000)) {
196	/* reduce to 15.6 us (62.4 us / quad) */
197	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
198	udelay (1000);
199	}
200
201	/*
202	* Final mapping
203	*/
204
205	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
206	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
207
208	/* adjust refresh rate depending on SDRAM type, one bank */
209	reg = memctl->memc_mptpr;
210	reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
211	memctl->memc_mptpr = reg;
212
213	udelay (10000);
214
c3fafecf WD	215	/* Configure UPMB for NAND flash access */
	216	upmconfig (UPMB, (uint *) nand_flash_table,
	217	sizeof (nand_flash_table) / sizeof (uint));
	218
	219	memctl->memc_mbmr = CFG_MBMR_NAND;
	220
7ca202f5 WD	221	return (size_b0);
	222	}
	223
	224	/* ------------------------------------------------------------------------- */
	225
	226	/*
	227	* Check memory range for valid RAM. A simple memory test determines
	228	* the actually available RAM size between addresses `base' and
	229	* `base + maxsize'. Some (not all) hardware errors are detected:
	230	* - short between address lines
	231	* - short between data lines
	232	*/
	233
8b74bf31	234	static long int dram_size (long int mamr_value, long int *base, long int maxsize)
7ca202f5 WD	235	{
	236	volatile immap_t immap = (immap_t ) CFG_IMMR;
	237	volatile memctl8xx_t *memctl = &immap->im_memctl;
	238
	239	memctl->memc_mamr = mamr_value;
	240
	241	return (get_ram_size(base, maxsize));
	242	}
4cfaf55e WD	243
	244	#if (CONFIG_COMMANDS & CFG_CMD_NAND)
	245	void nand_init(void)
	246	{
8b74bf31 WD	247	extern unsigned long nand_probe(unsigned long physadr);
8b74bf31 WD	248
4cfaf55e WD	249	unsigned long totlen = nand_probe(CFG_NAND_BASE);
	250
	251	printf ("%4lu MB\n", totlen >> 20);
	252	}
	253	#endif