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* Modify KUP4X board configuration to use SL811 driver for USB memory
[people/ms/u-boot.git] / board / netphone / netphone.c
CommitLineData
04a85b3b
WD		 1/*
2 * (C) Copyright 2000-2004
c26e454d 3 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
04a85b3b
WD		 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
27 * U-Boot port on NetTA4 board
28 */
29
30#include <common.h>
31#include <miiphy.h>
32#include <sed156x.h>
5cf91d6b 33#include <status_led.h>
04a85b3b
WD		 34
35#include "mpc8xx.h"
36
37#ifdef CONFIG_HW_WATCHDOG
38#include <watchdog.h>
39#endif
40
41/****************************************************************/
42
43/* some sane bit macros */
44#define _BD(_b) (1U << (31-(_b)))
45#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
46
47#define _BW(_b) (1U << (15-(_b)))
48#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
49
50#define _BB(_b) (1U << (7-(_b)))
51#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
52
53#define _B(_b) _BD(_b)
54#define _BR(_l, _h) _BDR(_l, _h)
55
56/****************************************************************/
57
58/*
59 * Check Board Identity:
60 *
61 * Return 1 always.
62 */
63
64int checkboard(void)
65{
c26e454d 66 printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
04a85b3b
WD		 67 return (0);
68}
69
70/****************************************************************/
71
72#define _NOT_USED_ 0xFFFFFFFF
73
74/****************************************************************/
75
76#define CS_0000 0x00000000
77#define CS_0001 0x10000000
78#define CS_0010 0x20000000
79#define CS_0011 0x30000000
80#define CS_0100 0x40000000
81#define CS_0101 0x50000000
82#define CS_0110 0x60000000
83#define CS_0111 0x70000000
84#define CS_1000 0x80000000
85#define CS_1001 0x90000000
86#define CS_1010 0xA0000000
87#define CS_1011 0xB0000000
88#define CS_1100 0xC0000000
89#define CS_1101 0xD0000000
90#define CS_1110 0xE0000000
91#define CS_1111 0xF0000000
92
93#define BS_0000 0x00000000
94#define BS_0001 0x01000000
95#define BS_0010 0x02000000
96#define BS_0011 0x03000000
97#define BS_0100 0x04000000
98#define BS_0101 0x05000000
99#define BS_0110 0x06000000
100#define BS_0111 0x07000000
101#define BS_1000 0x08000000
102#define BS_1001 0x09000000
103#define BS_1010 0x0A000000
104#define BS_1011 0x0B000000
105#define BS_1100 0x0C000000
106#define BS_1101 0x0D000000
107#define BS_1110 0x0E000000
108#define BS_1111 0x0F000000
109
c26e454d
WD		 110#define GPL0_AAAA 0x00000000
111#define GPL0_AAA0 0x00200000
112#define GPL0_AAA1 0x00300000
113#define GPL0_000A 0x00800000
114#define GPL0_0000 0x00A00000
115#define GPL0_0001 0x00B00000
116#define GPL0_111A 0x00C00000
117#define GPL0_1110 0x00E00000
118#define GPL0_1111 0x00F00000
119
120#define GPL1_0000 0x00000000
121#define GPL1_0001 0x00040000
122#define GPL1_1110 0x00080000
123#define GPL1_1111 0x000C0000
124
125#define GPL2_0000 0x00000000
126#define GPL2_0001 0x00010000
127#define GPL2_1110 0x00020000
128#define GPL2_1111 0x00030000
129
130#define GPL3_0000 0x00000000
131#define GPL3_0001 0x00004000
132#define GPL3_1110 0x00008000
133#define GPL3_1111 0x0000C000
04a85b3b
WD		 134
135#define GPL4_0000 0x00000000
136#define GPL4_0001 0x00001000
137#define GPL4_1110 0x00002000
138#define GPL4_1111 0x00003000
139
140#define GPL5_0000 0x00000000
141#define GPL5_0001 0x00000400
142#define GPL5_1110 0x00000800
143#define GPL5_1111 0x00000C00
144#define LOOP 0x00000080
145
146#define EXEN 0x00000040
147
148#define AMX_COL 0x00000000
149#define AMX_ROW 0x00000020
150#define AMX_MAR 0x00000030
151
152#define NA 0x00000008
153
154#define UTA 0x00000004
155
156#define TODT 0x00000002
157
158#define LAST 0x00000001
159
c26e454d
WD		 160#define A10_AAAA GPL0_AAAA
161#define A10_AAA0 GPL0_AAA0
162#define A10_AAA1 GPL0_AAA1
163#define A10_000A GPL0_000A
164#define A10_0000 GPL0_0000
165#define A10_0001 GPL0_0001
166#define A10_111A GPL0_111A
167#define A10_1110 GPL0_1110
168#define A10_1111 GPL0_1111
169
170#define RAS_0000 GPL1_0000
171#define RAS_0001 GPL1_0001
172#define RAS_1110 GPL1_1110
173#define RAS_1111 GPL1_1111
174
175#define CAS_0000 GPL2_0000
176#define CAS_0001 GPL2_0001
177#define CAS_1110 GPL2_1110
178#define CAS_1111 GPL2_1111
179
180#define WE_0000 GPL3_0000
181#define WE_0001 GPL3_0001
182#define WE_1110 GPL3_1110
183#define WE_1111 GPL3_1111
184
04a85b3b
WD		 185/* #define CAS_LATENCY 3 */
186#define CAS_LATENCY 2
187
188const uint sdram_table[0x40] = {
189
190#if CAS_LATENCY == 3
191 /* RSS */
192 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
193 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
194 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
195 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
196 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
197 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
198 _NOT_USED_, _NOT_USED_,
199
200 /* RBS */
201 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
202 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
203 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
204 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
205 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
206 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
207 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
208 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
209 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
210 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
211
212 /* WSS */
213 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
214 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
215 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
216 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
217 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
218 _NOT_USED_, _NOT_USED_, _NOT_USED_,
219
220 /* WBS */
221 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
222 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
223 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
224 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
225 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
226 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
227 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
228 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
229 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
230 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
231 _NOT_USED_, _NOT_USED_, _NOT_USED_,
232#endif
233
234#if CAS_LATENCY == 2
235 /* RSS */
236 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
237 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
238 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
239 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
240 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
241 _NOT_USED_,
242 _NOT_USED_, _NOT_USED_,
243
244 /* RBS */
245 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
246 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
247 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
248 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
249 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
250 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
251 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
252 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
253 _NOT_USED_,
254 _NOT_USED_, _NOT_USED_, _NOT_USED_,
255 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
256
257 /* WSS */
258 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
259 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
260 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
261 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
262 _NOT_USED_,
263 _NOT_USED_, _NOT_USED_,
264 _NOT_USED_,
265
266 /* WBS */
267 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
268 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
269 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
270 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
271 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
272 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
273 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
274 _NOT_USED_,
275 _NOT_USED_, _NOT_USED_, _NOT_USED_,
276 _NOT_USED_, _NOT_USED_, _NOT_USED_,
277 _NOT_USED_, _NOT_USED_,
278
279#endif
280
281 /* UPT */
282 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
283 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
284 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
285 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
286 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
287 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
288 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
289 _NOT_USED_, _NOT_USED_,
290
291 /* EXC */
292 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
293 _NOT_USED_,
294
295 /* REG */
296 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
297 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
298};
299
c26e454d
WD		 300#if CONFIG_NETPHONE_VERSION == 2
301static const uint nandcs_table[0x40] = {
302 /* RSS */
303 CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
304 CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
305 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
306 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
307 CS_0000 | GPL4_0000 | GPL5_1111,
308 CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
309 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
310 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
311
312 /* RBS */
313 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
314 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
315 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
316 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
317
318 /* WSS */
319 CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
320 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
321 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
322 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
323 CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
324 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
325 CS_0000 | GPL4_1111 | GPL5_1111,
326 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
327
328 /* WBS */
329 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
330 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
331 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
332 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
333
334 /* UPT */
335 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
336 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
337 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
338
339 /* EXC */
340 CS_0001 | LAST,
341 _NOT_USED_,
342
343 /* REG */
344 CS_1110 ,
345 CS_0001 | LAST,
346};
347#endif
348
04a85b3b
WD		 349/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
350/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
351#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
352
353/* 8 */
354#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
355 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
356 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
357
358void check_ram(unsigned int addr, unsigned int size)
359{
360 unsigned int i, j, v, vv;
361 volatile unsigned int *p;
362 unsigned int pv;
363
364 p = (unsigned int *)addr;
365 pv = (unsigned int)p;
366 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
367 *p++ = pv;
368
369 p = (unsigned int *)addr;
370 for (i = 0; i < size / sizeof(unsigned int); i++) {
371 v = (unsigned int)p;
372 vv = *p;
373 if (vv != v) {
374 printf("%p: read %08x instead of %08x\n", p, vv, v);
375 hang();
376 }
377 p++;
378 }
379
380 for (j = 0; j < 5; j++) {
381 switch (j) {
382 case 0: v = 0x00000000; break;
383 case 1: v = 0xffffffff; break;
384 case 2: v = 0x55555555; break;
385 case 3: v = 0xaaaaaaaa; break;
386 default:v = 0xdeadbeef; break;
387 }
388 p = (unsigned int *)addr;
389 for (i = 0; i < size / sizeof(unsigned int); i++) {
390 *p = v;
391 vv = *p;
392 if (vv != v) {
393 printf("%p: read %08x instead of %08x\n", p, vv, v);
394 hang();
395 }
396 *p = ~v;
397 p++;
398 }
399 }
400}
401
402long int initdram(int board_type)
403{
404 volatile immap_t *immap = (immap_t *) CFG_IMMR;
405 volatile memctl8xx_t *memctl = &immap->im_memctl;
406 long int size;
407
c26e454d 408 upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
04a85b3b
WD		 409
410 /*
411 * Preliminary prescaler for refresh
412 */
413 memctl->memc_mptpr = MPTPR_PTP_DIV8;
414
415 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
416
417 /*
418 * Map controller bank 3 to the SDRAM bank at preliminary address.
419 */
420 memctl->memc_or3 = CFG_OR3_PRELIM;
421 memctl->memc_br3 = CFG_BR3_PRELIM;
422
423 memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
424
425 udelay(200);
426
427 /* perform SDRAM initialisation sequence */
428 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
429 udelay(1);
430
431 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
432 udelay(1);
433
434 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
435 udelay(1);
436
437 memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
438
439 udelay(10000);
440
441 {
442 u32 d1, d2;
443
444 d1 = 0xAA55AA55;
445 *(volatile u32 *)0 = d1;
446 d2 = *(volatile u32 *)0;
447 if (d1 != d2) {
448 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
449 hang();
450 }
451
452 d1 = 0x55AA55AA;
453 *(volatile u32 *)0 = d1;
454 d2 = *(volatile u32 *)0;
455 if (d1 != d2) {
456 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
457 hang();
458 }
459 }
460
461 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
462
04a85b3b
WD		 463 if (size == 0) {
464 printf("SIZE is zero: LOOP on 0\n");
465 for (;;) {
466 *(volatile u32 *)0 = 0;
467 (void)*(volatile u32 *)0;
468 }
469 }
470
471 return size;
472}
473
474/* ------------------------------------------------------------------------- */
475
476void reset_phys(void)
477{
478 int phyno;
479 unsigned short v;
480
481 udelay(10000);
482 /* reset the damn phys */
483 mii_init();
484
485 for (phyno = 0; phyno < 32; ++phyno) {
486 miiphy_read(phyno, PHY_PHYIDR1, &v);
487 if (v == 0xFFFF)
488 continue;
489 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
490 udelay(10000);
491 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
492 udelay(10000);
493 }
494}
495
496/* ------------------------------------------------------------------------- */
497
498/* GP = general purpose, SP = special purpose (on chip peripheral) */
499
500/* bits that can have a special purpose or can be configured as inputs/outputs */
501#define PA_GP_INMASK 0
502#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
503#define PA_SP_MASK 0
504#define PA_ODR_VAL 0
505#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
506#define PA_SP_DIRVAL 0
507
508#define PB_GP_INMASK _B(28)
509#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
510#define PB_SP_MASK (_BR(22, 25))
511#define PB_ODR_VAL 0
512#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
513#define PB_SP_DIRVAL 0
514
c26e454d 515#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 516#define PC_GP_INMASK _BW(12)
517#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
c26e454d
WD		 518#elif CONFIG_NETPHONE_VERSION == 2
519#define PC_GP_INMASK (_BW(13) | _BW(15))
520#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
521#endif
04a85b3b
WD		 522#define PC_SP_MASK 0
523#define PC_SOVAL 0
524#define PC_INTVAL 0
525#define PC_GP_OUTVAL (_BW(10) | _BW(11))
526#define PC_SP_DIRVAL 0
527
c26e454d 528#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 529#define PE_GP_INMASK _B(31)
530#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
c26e454d
WD		 531#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
532#elif CONFIG_NETPHONE_VERSION == 2
533#define PE_GP_INMASK _BR(28, 31)
534#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
535#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
536#endif
04a85b3b
WD		 537#define PE_SP_MASK 0
538#define PE_ODR_VAL 0
04a85b3b
WD		 539#define PE_SP_DIRVAL 0
540
541int board_early_init_f(void)
542{
543 volatile immap_t *immap = (immap_t *) CFG_IMMR;
544 volatile iop8xx_t *ioport = &immap->im_ioport;
545 volatile cpm8xx_t *cpm = &immap->im_cpm;
546 volatile memctl8xx_t *memctl = &immap->im_memctl;
547
548 /* NAND chip select */
c26e454d 549#if CONFIG_NETPHONE_VERSION == 1
04a85b3b
WD		 550 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
551 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
c26e454d
WD		 552#elif CONFIG_NETPHONE_VERSION == 2
553 upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
554 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
555 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
556 memctl->memc_mamr = 0; /* all clear */
557#endif
04a85b3b
WD		 558
559 /* DSP chip select */
560 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
561 memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
562
c26e454d
WD		 563#if CONFIG_NETPHONE_VERSION == 1
564 memctl->memc_br4 &= ~BR_V;
565#endif
04a85b3b
WD		 566 memctl->memc_br5 &= ~BR_V;
567 memctl->memc_br6 &= ~BR_V;
568 memctl->memc_br7 &= ~BR_V;
569
570 ioport->iop_padat = PA_GP_OUTVAL;
571 ioport->iop_paodr = PA_ODR_VAL;
572 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
573 ioport->iop_papar = PA_SP_MASK;
574
575 cpm->cp_pbdat = PB_GP_OUTVAL;
576 cpm->cp_pbodr = PB_ODR_VAL;
577 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
578 cpm->cp_pbpar = PB_SP_MASK;
579
580 ioport->iop_pcdat = PC_GP_OUTVAL;
581 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
582 ioport->iop_pcso = PC_SOVAL;
583 ioport->iop_pcint = PC_INTVAL;
584 ioport->iop_pcpar = PC_SP_MASK;
585
586 cpm->cp_pedat = PE_GP_OUTVAL;
587 cpm->cp_peodr = PE_ODR_VAL;
588 cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
589 cpm->cp_pepar = PE_SP_MASK;
590
591 return 0;
592}
593
594#if (CONFIG_COMMANDS & CFG_CMD_NAND)
595
596#include <linux/mtd/nand.h>
597
598extern ulong nand_probe(ulong physadr);
599extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
600
601void nand_init(void)
602{
603 unsigned long totlen;
604
605 totlen = nand_probe(CFG_NAND_BASE);
606 printf ("%4lu MB\n", totlen >> 20);
607}
608#endif
609
610#ifdef CONFIG_HW_WATCHDOG
611
612void hw_watchdog_reset(void)
613{
614 /* XXX add here the really funky stuff */
615}
616
617#endif
618
619#ifdef CONFIG_SHOW_ACTIVITY
620
621static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */
622
623/* called from timer interrupt every 1/CFG_HZ sec */
624void board_show_activity(ulong timestamp)
625{
626 if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
627 --left_to_poll;
628}
629
630extern void phone_console_do_poll(void);
631
632static void do_poll(void)
633{
634 unsigned int base;
635
636 while (left_to_poll <= 0) {
637 phone_console_do_poll();
638 base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
639 do {
640 left_to_poll = base;
641 } while (base != left_to_poll);
642 }
643}
644
645/* called when looping */
646void show_activity(int arg)
647{
648 do_poll();
649}
650
651#endif
652
653#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
654int overwrite_console(void)
655{
656 /* printf("overwrite_console called\n"); */
657 return 0;
658}
659#endif
660
661extern int drv_phone_init(void);
662extern int drv_phone_use_me(void);
5cf91d6b 663extern int drv_phone_is_idle(void);
04a85b3b
WD		 664
665int misc_init_r(void)
666{
667 return drv_phone_init();
668}
669
670int last_stage_init(void)
671{
672 int i;
673
c26e454d
WD		 674#if CONFIG_NETPHONE_VERSION == 2
675 /* assert peripheral reset */
676 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
677 for (i = 0; i < 10; i++)
678 udelay(1000);
679 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12);
680#endif
04a85b3b
WD		 681 reset_phys();
682
683 /* check in order to enable the local console */
684 left_to_poll = PHONE_CONSOLE_POLL_HZ;
685 i = CFG_HZ * 2;
686 while (i > 0) {
687
688 if (tstc()) {
689 getc();
690 break;
691 }
692
693 do_poll();
694
695 if (drv_phone_use_me()) {
5cf91d6b
WD		 696 status_led_set(0, STATUS_LED_ON);
697 while (!drv_phone_is_idle()) {
698 do_poll();
699 udelay(1000000 / CFG_HZ);
700 }
701
04a85b3b
WD		 702 console_assign(stdin, "phone");
703 console_assign(stdout, "phone");
704 console_assign(stderr, "phone");
705 setenv("bootdelay", "-1");
706 break;
707 }
708
709 udelay(1000000 / CFG_HZ);
710 i--;
711 left_to_poll--;
712 }
713 left_to_poll = PHONE_CONSOLE_POLL_HZ;
714
715 return 0;
716}
"Das U-Boot" Source Tree