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f01b631f | 1 | /* |
8ca79b2f | 2 | * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
f01b631f | 3 | * |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
f01b631f TW |
5 | */ |
6 | ||
7 | #ifndef _PINMUX_CONFIG_CARDHU_H_ | |
8 | #define _PINMUX_CONFIG_CARDHU_H_ | |
9 | ||
dfb42fc9 | 10 | #define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ |
f01b631f | 11 | { \ |
803d01ed | 12 | .pingrp = PMUX_PINGRP_##_pingrp, \ |
f01b631f TW |
13 | .func = PMUX_FUNC_##_mux, \ |
14 | .pull = PMUX_PULL_##_pull, \ | |
15 | .tristate = PMUX_TRI_##_tri, \ | |
16 | .io = PMUX_PIN_##_io, \ | |
17 | .lock = PMUX_PIN_LOCK_DEFAULT, \ | |
18 | .od = PMUX_PIN_OD_DEFAULT, \ | |
19 | .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ | |
20 | } | |
21 | ||
dfb42fc9 | 22 | #define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ |
f01b631f | 23 | { \ |
803d01ed | 24 | .pingrp = PMUX_PINGRP_##_pingrp, \ |
f01b631f TW |
25 | .func = PMUX_FUNC_##_mux, \ |
26 | .pull = PMUX_PULL_##_pull, \ | |
27 | .tristate = PMUX_TRI_##_tri, \ | |
28 | .io = PMUX_PIN_##_io, \ | |
29 | .lock = PMUX_PIN_LOCK_##_lock, \ | |
30 | .od = PMUX_PIN_OD_##_od, \ | |
31 | .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ | |
32 | } | |
33 | ||
dfb42fc9 | 34 | #define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ |
f01b631f | 35 | { \ |
803d01ed | 36 | .pingrp = PMUX_PINGRP_##_pingrp, \ |
f01b631f TW |
37 | .func = PMUX_FUNC_##_mux, \ |
38 | .pull = PMUX_PULL_##_pull, \ | |
39 | .tristate = PMUX_TRI_##_tri, \ | |
40 | .io = PMUX_PIN_##_io, \ | |
41 | .lock = PMUX_PIN_LOCK_##_lock, \ | |
42 | .od = PMUX_PIN_OD_DEFAULT, \ | |
43 | .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ | |
44 | } | |
45 | ||
dfb42fc9 | 46 | #define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ |
8ca79b2f | 47 | { \ |
803d01ed | 48 | .drvgrp = PMUX_DRVGRP_##_drvgrp, \ |
8ca79b2f TW |
49 | .slwf = _slwf, \ |
50 | .slwr = _slwr, \ | |
51 | .drvup = _drvup, \ | |
52 | .drvdn = _drvdn, \ | |
dfb42fc9 SW |
53 | .lpmd = PMUX_LPMD_##_lpmd, \ |
54 | .schmt = PMUX_SCHMT_##_schmt, \ | |
55 | .hsm = PMUX_HSM_##_hsm, \ | |
8ca79b2f TW |
56 | } |
57 | ||
dfb42fc9 | 58 | static struct pmux_pingrp_config tegra3_pinmux_common[] = { |
f01b631f | 59 | /* SDMMC1 pinmux */ |
803d01ed SW |
60 | DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), |
61 | DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), | |
62 | DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), | |
63 | DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), | |
64 | DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), | |
65 | DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), | |
f01b631f TW |
66 | |
67 | /* SDMMC3 pinmux */ | |
803d01ed SW |
68 | DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), |
69 | DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), | |
70 | DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), | |
71 | DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), | |
72 | DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), | |
73 | DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), | |
74 | DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT), | |
75 | DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT), | |
f01b631f TW |
76 | |
77 | /* SDMMC4 pinmux */ | |
803d01ed SW |
78 | LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
79 | LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
80 | LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
81 | LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
82 | LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
83 | LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
84 | LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
85 | LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
86 | LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
87 | LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
88 | LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), | |
f01b631f TW |
89 | |
90 | /* I2C1 pinmux */ | |
803d01ed SW |
91 | I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
92 | I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), | |
f01b631f TW |
93 | |
94 | /* I2C2 pinmux */ | |
803d01ed SW |
95 | I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
96 | I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), | |
f01b631f TW |
97 | |
98 | /* I2C3 pinmux */ | |
803d01ed SW |
99 | I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
100 | I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), | |
f01b631f TW |
101 | |
102 | /* I2C4 pinmux */ | |
803d01ed SW |
103 | I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
104 | I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), | |
f01b631f TW |
105 | |
106 | /* Power I2C pinmux */ | |
803d01ed SW |
107 | I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
108 | I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), | |
f01b631f | 109 | |
803d01ed SW |
110 | DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), |
111 | DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT), | |
112 | DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), | |
113 | DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), | |
114 | DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), | |
115 | DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), | |
116 | DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), | |
117 | DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), | |
118 | DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), | |
119 | DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), | |
120 | DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), | |
121 | DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), | |
122 | DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), | |
123 | DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), | |
124 | DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), | |
125 | DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), | |
126 | DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT), | |
127 | DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT), | |
128 | DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), | |
129 | DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), | |
130 | DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), | |
131 | DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT), | |
132 | DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), | |
133 | DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), | |
134 | DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), | |
135 | DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), | |
136 | DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), | |
137 | DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), | |
138 | DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), | |
139 | DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), | |
140 | DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), | |
141 | DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), | |
142 | DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), | |
143 | DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), | |
144 | DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), | |
145 | DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), | |
146 | DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), | |
147 | DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), | |
148 | DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), | |
149 | DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), | |
150 | DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), | |
151 | DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), | |
152 | DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), | |
153 | DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), | |
154 | DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), | |
155 | DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), | |
156 | DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), | |
157 | DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), | |
158 | DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), | |
159 | DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), | |
160 | DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), | |
161 | DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), | |
162 | DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), | |
163 | DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), | |
164 | DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), | |
165 | DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), | |
166 | DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), | |
167 | DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), | |
168 | DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), | |
169 | DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), | |
170 | DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), | |
171 | DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), | |
172 | LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
173 | LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
174 | LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
175 | LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
176 | LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), | |
177 | LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
178 | LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
179 | LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
180 | LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE), | |
181 | DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), | |
182 | DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), | |
183 | DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT), | |
184 | DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), | |
185 | DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), | |
186 | DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), | |
187 | DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), | |
188 | DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), | |
189 | DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), | |
190 | DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT), | |
191 | DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), | |
192 | DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT), | |
193 | DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), | |
194 | DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), | |
195 | DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT), | |
196 | DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), | |
197 | DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), | |
198 | DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), | |
199 | DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), | |
200 | DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), | |
201 | DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT), | |
202 | DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT), | |
203 | DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */ | |
204 | DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */ | |
205 | DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */ | |
206 | DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT), | |
207 | DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT), | |
208 | DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT), | |
209 | DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT), | |
210 | DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT), | |
211 | DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT), | |
212 | DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT), | |
213 | DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT), | |
214 | DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT), | |
215 | DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT), | |
216 | DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT), | |
217 | DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT), | |
218 | DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), | |
f01b631f TW |
219 | |
220 | /* KBC keys */ | |
803d01ed SW |
221 | DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), |
222 | DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), | |
223 | DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), | |
224 | DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT), | |
225 | DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT), | |
226 | DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT), | |
227 | DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT), | |
228 | DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT), | |
229 | DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), | |
230 | DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT), | |
231 | DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT), | |
232 | DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT), | |
233 | DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT), | |
234 | DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), | |
235 | DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT), | |
236 | DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT), | |
237 | DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), | |
238 | DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), | |
239 | DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), | |
240 | DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), | |
241 | DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), | |
242 | DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), | |
243 | DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), | |
244 | DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), | |
245 | DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), | |
f01b631f | 246 | |
803d01ed SW |
247 | DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT), |
248 | DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), | |
f01b631f | 249 | DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), |
803d01ed SW |
250 | DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), |
251 | DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), | |
252 | DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), | |
253 | DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), | |
254 | DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT), | |
255 | DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), | |
256 | DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), | |
257 | DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), | |
258 | DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), | |
259 | DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), | |
260 | DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), | |
261 | DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), | |
f01b631f | 262 | |
803d01ed SW |
263 | DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT), |
264 | DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), | |
265 | DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), | |
266 | DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), | |
267 | DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), | |
268 | DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), | |
269 | DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), | |
270 | DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), | |
271 | DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), | |
272 | DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), | |
273 | DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), | |
274 | DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), | |
275 | DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), | |
276 | DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), | |
277 | DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), | |
278 | DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), | |
279 | DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), | |
f01b631f TW |
280 | |
281 | /* GPIOs */ | |
282 | /* SDMMC1 CD gpio */ | |
803d01ed | 283 | DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), |
f01b631f | 284 | /* SDMMC1 WP gpio */ |
803d01ed | 285 | LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE), |
f01b631f TW |
286 | |
287 | /* Touch panel GPIO */ | |
288 | /* Touch IRQ */ | |
803d01ed | 289 | DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT), |
f01b631f TW |
290 | |
291 | /* Touch RESET */ | |
803d01ed | 292 | DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT), |
f01b631f TW |
293 | |
294 | /* Power rails GPIO */ | |
803d01ed SW |
295 | DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), |
296 | DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT), | |
297 | DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), | |
298 | DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), | |
299 | DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), | |
f01b631f | 300 | |
803d01ed SW |
301 | LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), |
302 | LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
303 | LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
304 | LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE), | |
305 | LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
306 | LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), | |
f01b631f TW |
307 | }; |
308 | ||
dfb42fc9 | 309 | static struct pmux_pingrp_config unused_pins_lowpower[] = { |
803d01ed SW |
310 | DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT), |
311 | DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), | |
312 | DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), | |
313 | DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT), | |
314 | DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), | |
315 | DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), | |
316 | DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), | |
317 | DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), | |
318 | DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), | |
319 | DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT), | |
320 | DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT), | |
321 | DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), | |
322 | DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), | |
323 | DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), | |
324 | DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), | |
325 | DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT), | |
326 | DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), | |
327 | DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), | |
328 | DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), | |
f01b631f TW |
329 | }; |
330 | ||
dfb42fc9 SW |
331 | static struct pmux_drvgrp_config cardhu_padctrl[] = { |
332 | /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ | |
8ca79b2f TW |
333 | DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ |
334 | SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), | |
335 | }; | |
336 | #endif /* _PINMUX_CONFIG_CARDHU_H_ */ |