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3f82b1d3 TW |
1 | /* |
2 | * (C) Copyright 2010,2011 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
3f82b1d3 TW |
6 | */ |
7 | ||
8 | #include <common.h> | |
0521f984 | 9 | #include <dm.h> |
3f82b1d3 | 10 | #include <ns16550.h> |
c5b34a29 | 11 | #include <linux/compiler.h> |
3f82b1d3 | 12 | #include <asm/io.h> |
b4ba2be8 | 13 | #include <asm/arch/clock.h> |
6d6c0bae | 14 | #ifdef CONFIG_LCD |
1b24a50b | 15 | #include <asm/arch/display.h> |
6d6c0bae | 16 | #endif |
c0720afb | 17 | #include <asm/arch/funcmux.h> |
3f82b1d3 | 18 | #include <asm/arch/pinmux.h> |
8723626d | 19 | #include <asm/arch/pmu.h> |
6d6c0bae | 20 | #ifdef CONFIG_PWM_TEGRA |
e1ae0d1f | 21 | #include <asm/arch/pwm.h> |
6d6c0bae | 22 | #endif |
150c2493 | 23 | #include <asm/arch/tegra.h> |
73c38934 | 24 | #include <asm/arch-tegra/ap.h> |
150c2493 TW |
25 | #include <asm/arch-tegra/board.h> |
26 | #include <asm/arch-tegra/clk_rst.h> | |
27 | #include <asm/arch-tegra/pmc.h> | |
28 | #include <asm/arch-tegra/sys_proto.h> | |
29 | #include <asm/arch-tegra/uart.h> | |
30 | #include <asm/arch-tegra/warmboot.h> | |
6d6c0bae TW |
31 | #ifdef CONFIG_TEGRA_CLOCK_SCALING |
32 | #include <asm/arch/emc.h> | |
33 | #endif | |
34 | #ifdef CONFIG_USB_EHCI_TEGRA | |
7ae18f37 | 35 | #include <asm/arch-tegra/usb.h> |
16297cfb | 36 | #include <usb.h> |
6d6c0bae | 37 | #endif |
c9aa831e | 38 | #ifdef CONFIG_TEGRA_MMC |
190be1f9 | 39 | #include <asm/arch-tegra/tegra_mmc.h> |
c9aa831e TW |
40 | #include <asm/arch-tegra/mmc.h> |
41 | #endif | |
79c7a90f | 42 | #include <asm/arch-tegra/xusb-padctl.h> |
cb445fb4 | 43 | #include <i2c.h> |
6d6c0bae | 44 | #include <spi.h> |
c5b34a29 | 45 | #include "emc.h" |
3f82b1d3 TW |
46 | |
47 | DECLARE_GLOBAL_DATA_PTR; | |
48 | ||
0521f984 SG |
49 | #ifdef CONFIG_SPL_BUILD |
50 | /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ | |
51 | U_BOOT_DEVICE(tegra_gpios) = { | |
52 | "gpio_tegra" | |
53 | }; | |
54 | #endif | |
55 | ||
29f3e3f2 TW |
56 | const struct tegra_sysinfo sysinfo = { |
57 | CONFIG_TEGRA_BOARD_STRING | |
3f82b1d3 TW |
58 | }; |
59 | ||
19d7bf3d JH |
60 | __weak void pinmux_init(void) {} |
61 | __weak void pin_mux_usb(void) {} | |
62 | __weak void pin_mux_spi(void) {} | |
63 | __weak void gpio_early_init_uart(void) {} | |
64 | __weak void pin_mux_display(void) {} | |
0cd10c7a | 65 | |
dcd12518 | 66 | #if defined(CONFIG_TEGRA_NAND) |
19d7bf3d | 67 | __weak void pin_mux_nand(void) |
c0720afb LS |
68 | { |
69 | funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); | |
70 | } | |
dcd12518 | 71 | #endif |
c0720afb | 72 | |
5aff021c WN |
73 | /* |
74 | * Routine: power_det_init | |
75 | * Description: turn off power detects | |
76 | */ | |
77 | static void power_det_init(void) | |
78 | { | |
00a2749d | 79 | #if defined(CONFIG_TEGRA20) |
29f3e3f2 | 80 | struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
5aff021c WN |
81 | |
82 | /* turn off power detects */ | |
83 | writel(0, &pmc->pmc_pwr_det_latch); | |
84 | writel(0, &pmc->pmc_pwr_det); | |
85 | #endif | |
86 | } | |
87 | ||
3f82b1d3 TW |
88 | /* |
89 | * Routine: board_init | |
90 | * Description: Early hardware init. | |
91 | */ | |
92 | int board_init(void) | |
93 | { | |
c5b34a29 JZ |
94 | __maybe_unused int err; |
95 | ||
a04eba99 | 96 | /* Do clocks and UART first so that printf() works */ |
4ed59e70 SG |
97 | clock_init(); |
98 | clock_verify(); | |
99 | ||
fda6fac3 | 100 | #ifdef CONFIG_TEGRA_SPI |
e0284948 | 101 | pin_mux_spi(); |
e1ae0d1f | 102 | #endif |
b19f5749 | 103 | |
e1ae0d1f SG |
104 | #ifdef CONFIG_PWM_TEGRA |
105 | if (pwm_init(gd->fdt_blob)) | |
106 | debug("%s: Failed to init pwm\n", __func__); | |
1b24a50b SG |
107 | #endif |
108 | #ifdef CONFIG_LCD | |
716d9439 | 109 | pin_mux_display(); |
1b24a50b | 110 | tegra_lcd_check_next_stage(gd->fdt_blob, 0); |
9112ef8d | 111 | #endif |
3f82b1d3 TW |
112 | /* boot param addr */ |
113 | gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); | |
5aff021c WN |
114 | |
115 | power_det_init(); | |
116 | ||
1f2ba722 | 117 | #ifdef CONFIG_SYS_I2C_TEGRA |
8723626d SG |
118 | # ifdef CONFIG_TEGRA_PMU |
119 | if (pmu_set_nominal()) | |
120 | debug("Failed to select nominal voltages\n"); | |
c5b34a29 JZ |
121 | # ifdef CONFIG_TEGRA_CLOCK_SCALING |
122 | err = board_emc_init(); | |
123 | if (err) | |
124 | debug("Memory controller init failed: %d\n", err); | |
125 | # endif | |
126 | # endif /* CONFIG_TEGRA_PMU */ | |
1f2ba722 | 127 | #endif /* CONFIG_SYS_I2C_TEGRA */ |
3f82b1d3 | 128 | |
f10393e5 SG |
129 | #ifdef CONFIG_USB_EHCI_TEGRA |
130 | pin_mux_usb(); | |
16297cfb | 131 | usb_process_devicetree(gd->fdt_blob); |
f10393e5 | 132 | #endif |
16297cfb | 133 | |
1b24a50b SG |
134 | #ifdef CONFIG_LCD |
135 | tegra_lcd_check_next_stage(gd->fdt_blob, 0); | |
136 | #endif | |
f10393e5 | 137 | |
c0720afb LS |
138 | #ifdef CONFIG_TEGRA_NAND |
139 | pin_mux_nand(); | |
140 | #endif | |
141 | ||
79c7a90f TR |
142 | tegra_xusb_padctl_init(gd->fdt_blob); |
143 | ||
29f3e3f2 | 144 | #ifdef CONFIG_TEGRA_LP0 |
a49716aa AM |
145 | /* save Sdram params to PMC 2, 4, and 24 for WB0 */ |
146 | warmboot_save_sdram_params(); | |
147 | ||
67ac5797 SG |
148 | /* prepare the WB code to LP0 location */ |
149 | warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); | |
150 | #endif | |
151 | ||
3f82b1d3 TW |
152 | return 0; |
153 | } | |
21ef6a10 | 154 | |
3e00dbdf | 155 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
cb7a1cf3 TR |
156 | static void __gpio_early_init(void) |
157 | { | |
158 | } | |
159 | ||
160 | void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); | |
161 | ||
3e00dbdf SG |
162 | int board_early_init_f(void) |
163 | { | |
6d6c0bae | 164 | pinmux_init(); |
f46a9456 | 165 | board_init_uart_f(); |
3e00dbdf SG |
166 | |
167 | /* Initialize periph GPIOs */ | |
cb7a1cf3 | 168 | gpio_early_init(); |
a04eba99 | 169 | gpio_early_init_uart(); |
1b24a50b SG |
170 | #ifdef CONFIG_LCD |
171 | tegra_lcd_early_init(gd->fdt_blob); | |
172 | #endif | |
0cd10c7a | 173 | |
3e00dbdf SG |
174 | return 0; |
175 | } | |
176 | #endif /* EARLY_INIT */ | |
1b24a50b SG |
177 | |
178 | int board_late_init(void) | |
179 | { | |
180 | #ifdef CONFIG_LCD | |
181 | /* Make sure we finish initing the LCD */ | |
182 | tegra_lcd_check_next_stage(gd->fdt_blob, 1); | |
73c38934 SW |
183 | #endif |
184 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) | |
185 | if (tegra_cpu_is_non_secure()) { | |
186 | printf("CPU is in NS mode\n"); | |
187 | setenv("cpu_ns_mode", "1"); | |
188 | } else { | |
189 | setenv("cpu_ns_mode", ""); | |
190 | } | |
1b24a50b SG |
191 | #endif |
192 | return 0; | |
193 | } | |
c9aa831e TW |
194 | |
195 | #if defined(CONFIG_TEGRA_MMC) | |
19d7bf3d | 196 | __weak void pin_mux_mmc(void) |
c9aa831e TW |
197 | { |
198 | } | |
199 | ||
c9aa831e TW |
200 | /* this is a weak define that we are overriding */ |
201 | int board_mmc_init(bd_t *bd) | |
202 | { | |
203 | debug("%s called\n", __func__); | |
204 | ||
205 | /* Enable muxes, etc. for SDMMC controllers */ | |
206 | pin_mux_mmc(); | |
207 | ||
208 | debug("%s: init MMC\n", __func__); | |
209 | tegra_mmc_init(); | |
210 | ||
211 | return 0; | |
212 | } | |
190be1f9 TW |
213 | |
214 | void pad_init_mmc(struct mmc_host *host) | |
215 | { | |
216 | #if defined(CONFIG_TEGRA30) | |
217 | enum periph_id id = host->mmc_id; | |
218 | u32 val; | |
219 | ||
220 | debug("%s: sdmmc address = %08x, id = %d\n", __func__, | |
221 | (unsigned int)host->reg, id); | |
222 | ||
223 | /* Set the pad drive strength for SDMMC1 or 3 only */ | |
224 | if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { | |
225 | debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", | |
226 | __func__); | |
227 | return; | |
228 | } | |
229 | ||
230 | val = readl(&host->reg->sdmemcmppadctl); | |
231 | val &= 0xFFFFFFF0; | |
232 | val |= MEMCOMP_PADCTRL_VREF; | |
233 | writel(val, &host->reg->sdmemcmppadctl); | |
234 | ||
235 | val = readl(&host->reg->autocalcfg); | |
236 | val &= 0xFFFF0000; | |
237 | val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; | |
238 | writel(val, &host->reg->autocalcfg); | |
239 | #endif /* T30 */ | |
240 | } | |
241 | #endif /* MMC */ |