[people/ms/u-boot.git] / board / omap1510inn / platform.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2003
 * Texas Instruments, <www.ti.com>
 *
 * -- Some bits of code used from rrload's head_OMAP1510.s --
 * Copyright (C) 2002 RidgeRun, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>

#if defined(CONFIG_OMAP1510)
#include <./configs/omap1510.h>
#endif

#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))


_TEXT_BASE:
	.word	TEXT_BASE        /* sdram load addr from config.mk */

.globl platformsetup
platformsetup:

	/*
	 * Configure 1510 pins functions to match our board.
	 */
	ldr     r0, REG_PULL_DWN_CTRL_0
	ldr     r1, VAL_PULL_DWN_CTRL_0
	str     r1, [r0]
	ldr     r0, REG_PULL_DWN_CTRL_1
	ldr     r1, VAL_PULL_DWN_CTRL_1
	str     r1, [r0]
	ldr     r0, REG_PULL_DWN_CTRL_2
	ldr     r1, VAL_PULL_DWN_CTRL_2
	str     r1, [r0]
	ldr     r0, REG_PULL_DWN_CTRL_3
	ldr     r1, VAL_PULL_DWN_CTRL_3
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_4
	ldr     r1, VAL_FUNC_MUX_CTRL_4
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_5
	ldr     r1, VAL_FUNC_MUX_CTRL_5
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_6
	ldr     r1, VAL_FUNC_MUX_CTRL_6
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_7
	ldr     r1, VAL_FUNC_MUX_CTRL_7
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_8
	ldr     r1, VAL_FUNC_MUX_CTRL_8
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_9
	ldr     r1, VAL_FUNC_MUX_CTRL_9
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_A
	ldr     r1, VAL_FUNC_MUX_CTRL_A
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_B
	ldr     r1, VAL_FUNC_MUX_CTRL_B
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_C
	ldr     r1, VAL_FUNC_MUX_CTRL_C
	str     r1, [r0]
	ldr     r0, REG_FUNC_MUX_CTRL_D
	ldr     r1, VAL_FUNC_MUX_CTRL_D
	str     r1, [r0]
	ldr     r0, REG_VOLTAGE_CTRL_0
	ldr     r1, VAL_VOLTAGE_CTRL_0
	str     r1, [r0]
	ldr     r0, REG_TEST_DBG_CTRL_0
	ldr     r1, VAL_TEST_DBG_CTRL_0
	str     r1, [r0]
	ldr     r0, REG_MOD_CONF_CTRL_0
	ldr     r1, VAL_MOD_CONF_CTRL_0
	str     r1, [r0]

	/* Move to 1510 mode */
	ldr     r0, REG_COMP_MODE_CTRL_0
	ldr     r1, VAL_COMP_MODE_CTRL_0
	str     r1, [r0]

	/* Set up Traffic Ctlr*/
	ldr r0, REG_TC_IMIF_PRIO
	mov r1, #0x0
	str r1, [r0]
	ldr r0, REG_TC_EMIFS_PRIO
	str r1, [r0]
	ldr r0, REG_TC_EMIFF_PRIO
	str r1, [r0]

	ldr r0, REG_TC_EMIFS_CONFIG
	ldr r1, [r0]
	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
	str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */

	/* Setup some clock domains */
	ldr r1, =OMAP1510_CLKS
	ldr r0, REG_ARM_IDLECT2
	strh r1, [r0]  /* CLKM, Clock domain control. */

	mov r1, #0x01  /* PER_EN bit */
	ldr r0, REG_ARM_RSTCT2
	strh r1, [r0]  /* CLKM; Peripheral reset. */

	/* Set CLKM to Sync-Scalable  */
	/* I supposidly need to enable the dsp clock before switching */
	mov r1, #0x1000
	ldr r0, REG_ARM_SYSST
	strh r1, [r0]
	mov r0, #0x400
1:
	subs r0, r0, #0x1   /* wait for any bubbles to finish */
	bne 1b

	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
	ldr r0, REG_ARM_CKCTL
	strh r1, [r0]

	/* setup DPLL 1 */
	ldr r1, VAL_DPLL1_CTL
	ldr r0, REG_DPLL1_CTL
	strh r1, [r0]
	ands r1, r1, #0x10  /* Check if PLL is enabled. */
	beq lock_end        /* Do not look for lock if BYPASS selected */
2:
	ldrh r1, [r0]
	ands r1, r1, #0x01  /* Check the LOCK bit. */
	beq 2b              /* ...loop until bit goes hi. */
lock_end:

	/* Set memory timings corresponding to the new clock speed */

	/* Check execution location to determine current execution location
	 * and branch to appropriate initialization code.
	 */
	mov r0, #0x10000000                 /* Load physical SDRAM base. */
	mov r1, pc                          /* Get current execution location. */
	cmp r1, r0                          /* Compare. */
	bge skip_sdram                      /* Skip over EMIF-fast initialization if running from SDRAM. */

	/*
	 * Delay for SDRAM initialization.
	 */
	mov r3, #0x1800                        /* value should be checked */
3:
	subs r3, r3, #0x1                     /* Decrement count */
	bne 3b

	/*
	 * Set SDRAM control values. Disable refresh before MRS command.
	 */
	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
	bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
	orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
	orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
	str r3, [r2]                        /* Store the passed value with AR disabled. */

	ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
	ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
	str r1, [r2]                        /* Store the passed value.*/

	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
	str r0, [r2]                        /* Store the passed value. */

	/*
	 * Delay for SDRAM initialization.
	 */
	mov r3, #0x1800
4:
	subs r3, r3, #1                     /* Decrement count. */
	bne 4b

skip_sdram:

	/* slow interface */
	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
	ldr r0, REG_TC_EMIFS_CS0_CONFIG
	str r1, [r0] /* Chip Select 0 */
	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
	ldr r0, REG_TC_EMIFS_CS1_CONFIG
	str r1, [r0] /* Chip Select 1 */
	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
	ldr r0, REG_TC_EMIFS_CS2_CONFIG
	str r1, [r0] /* Chip Select 2 */
	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
	ldr r0, REG_TC_EMIFS_CS3_CONFIG
	str r1, [r0] /* Chip Select 3 */

 /* Next, Enable the RS232 Line Drivers in the FPGA. */
 /* Also, power on the audio CODEC's amplifier here, */
 /* which will make a noise on the audio output. */
 /* This is done here instead of in the kernel so there */
 /* isn't a loud popping noise at the start of each */
 /* song. */
 /* Also, disable the CODEC's clocks. */
 /* omap1510-HelenP1 [specific] */

	ldr r0, REG_FPGA_POWER
	mov r1, #0
	ldr r2, REG_FPGA_DIP_SWITCH
	ldrb r3, [r2]
	cmp r3, #0x8
	movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
	strb r1, [r0]
	ldr r0, REG_FPGA_AUDIO
	mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
	strb r1, [r0]

	/* back to arch calling code */
	mov	pc, lr

/* the literal pools origin */
	.ltorg

/* OMAP configuration registers */
REG_FUNC_MUX_CTRL_0:		/* 32 bits */
	.word 0xfffe1000
REG_FUNC_MUX_CTRL_1:		/* 32 bits */
	.word 0xfffe1004
REG_FUNC_MUX_CTRL_2:		/* 32 bits */
	.word 0xfffe1008
REG_COMP_MODE_CTRL_0:		/* 32 bits */
	.word 0xfffe100c
REG_FUNC_MUX_CTRL_3:		/* 32 bits */
	.word 0xfffe1010
REG_FUNC_MUX_CTRL_4:		/* 32 bits */
	.word 0xfffe1014
REG_FUNC_MUX_CTRL_5:		/* 32 bits */
	.word 0xfffe1018
REG_FUNC_MUX_CTRL_6:		/* 32 bits */
	.word 0xfffe101c
REG_FUNC_MUX_CTRL_7:		/* 32 bits */
	.word 0xfffe1020
REG_FUNC_MUX_CTRL_8:		/* 32 bits */
	.word 0xfffe1024
REG_FUNC_MUX_CTRL_9:		/* 32 bits */
	.word 0xfffe1028
REG_FUNC_MUX_CTRL_A:		/* 32 bits */
	.word 0xfffe102C
REG_FUNC_MUX_CTRL_B:		/* 32 bits */
	.word 0xfffe1030
REG_FUNC_MUX_CTRL_C:		/* 32 bits */
	.word 0xfffe1034
REG_FUNC_MUX_CTRL_D:		/* 32 bits */
	.word 0xfffe1038
REG_PULL_DWN_CTRL_0:		/* 32 bits */
	.word 0xfffe1040
REG_PULL_DWN_CTRL_1:		/* 32 bits */
	.word 0xfffe1044
REG_PULL_DWN_CTRL_2:		/* 32 bits */
	.word 0xfffe1048
REG_PULL_DWN_CTRL_3:		/* 32 bits */
	.word 0xfffe104c
REG_VOLTAGE_CTRL_0:		/* 32 bits */
	.word 0xfffe1060
REG_TEST_DBG_CTRL_0:		/* 32 bits */
	.word 0xfffe1070
REG_MOD_CONF_CTRL_0:		/* 32 bits */
	.word 0xfffe1080
REG_TC_IMIF_PRIO:		/* 32 bits */
	.word 0xfffecc00
REG_TC_EMIFS_PRIO:		/* 32 bits */
	.word 0xfffecc04
REG_TC_EMIFF_PRIO:		/* 32 bits */
	.word 0xfffecc08
REG_TC_EMIFS_CONFIG:		/* 32 bits */
	.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
	.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
	.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
	.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
	.word 0xfffecc1c
REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
	.word 0xfffecc20
REG_TC_EMIFF_MRS:		/* 32 bits */
	.word 0xfffecc24
/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL:			/* 16 bits */
	.word 0xfffece00
REG_ARM_IDLECT2:		/* 16 bits */
	.word 0xfffece08
REG_ARM_RSTCT2:			/* 16 bits */
	.word 0xfffece14
REG_ARM_SYSST:			/* 16 bits */
	.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL:			/* 16 bits */
	.word 0xfffecf00
/* identification code register */
REG_IDCODE:			/* 32 bits */
	.word 0xfffed404

/* Innovator specific */
REG_FPGA_LED_DIGIT:		/* 8 bits (not used on Innovator) */
	.word 0x08000003
REG_FPGA_POWER:			/* 8 bits */
	.word 0x08000005
REG_FPGA_AUDIO:			/* 8 bits (not used on Innovator) */
	.word 0x0800000c
REG_FPGA_DIP_SWITCH:		/* 8 bits (not used on Innovator) */
	.word 0x0800000e

VAL_COMP_MODE_CTRL_0:
	.word 0x0000eaef
VAL_FUNC_MUX_CTRL_4:
	.word 0x00000000
VAL_FUNC_MUX_CTRL_5:
	.word 0x00000000
VAL_FUNC_MUX_CTRL_6:
	.word 0x00000001
VAL_FUNC_MUX_CTRL_7:
	.word 0x00000000
VAL_FUNC_MUX_CTRL_8:
	.word 0x10001200
VAL_FUNC_MUX_CTRL_9:
	.word 0x01201012
VAL_FUNC_MUX_CTRL_A:
	.word 0x00000248
VAL_FUNC_MUX_CTRL_B:
	.word 0x00000248
VAL_FUNC_MUX_CTRL_C:
	.word 0x09000000
VAL_FUNC_MUX_CTRL_D:
	.word 0x00000000
VAL_PULL_DWN_CTRL_0:
	.word 0x11a10000
VAL_PULL_DWN_CTRL_1:
	.word 0x2e047fff
VAL_PULL_DWN_CTRL_2:
	.word 0xffd603a6
VAL_PULL_DWN_CTRL_3:
	.word 0x00003e03
VAL_VOLTAGE_CTRL_0:
	.word 0x00000007
VAL_TEST_DBG_CTRL_0:
	/*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
	 *   This slows down internal SRAM accesses.
	 */
	.word 0x00000007
VAL_MOD_CONF_CTRL_0:
	.word 0x0b000008
VAL_ARM_CKCTL:
	.word 0x010f
VAL_DPLL1_CTL:
	.word 0x2710
VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
	.word 0x00001149
VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
	.word 0x00004158
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x0000f559
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x00003331
VAL_TC_EMIFF_SDRAM_CONFIG:
	.word 0x010290fc
VAL_TC_EMIFF_MRS:
	.word 0x00000027
Commit	Line	Data
2e5983d2 WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2003
	5	* Texas Instruments, <www.ti.com>
	6	*
	7	* -- Some bits of code used from rrload's head_OMAP1510.s --
	8	* Copyright (C) 2002 RidgeRun, Inc.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <config.h>
	30	#include <version.h>
	31
	32	#if defined(CONFIG_OMAP1510)
	33	#include <./configs/omap1510.h>
	34	#endif
	35
	36	#define OMAP1510_CLKS ((1<<EN_XORPCK)\|(1<<EN_PERCK)\|(1<<EN_TIMCK)\|(1<<EN_GPIOCK))
	37
	38
	39	_TEXT_BASE:
	40	.word TEXT_BASE /* sdram load addr from config.mk */
	41
	42	.globl platformsetup
	43	platformsetup:
	44
945af8d7 WD	45	/*
	46	* Configure 1510 pins functions to match our board.
	47	*/
	48	ldr r0, REG_PULL_DWN_CTRL_0
	49	ldr r1, VAL_PULL_DWN_CTRL_0
	50	str r1, [r0]
	51	ldr r0, REG_PULL_DWN_CTRL_1
	52	ldr r1, VAL_PULL_DWN_CTRL_1
	53	str r1, [r0]
	54	ldr r0, REG_PULL_DWN_CTRL_2
	55	ldr r1, VAL_PULL_DWN_CTRL_2
	56	str r1, [r0]
	57	ldr r0, REG_PULL_DWN_CTRL_3
	58	ldr r1, VAL_PULL_DWN_CTRL_3
	59	str r1, [r0]
	60	ldr r0, REG_FUNC_MUX_CTRL_4
	61	ldr r1, VAL_FUNC_MUX_CTRL_4
	62	str r1, [r0]
	63	ldr r0, REG_FUNC_MUX_CTRL_5
	64	ldr r1, VAL_FUNC_MUX_CTRL_5
	65	str r1, [r0]
	66	ldr r0, REG_FUNC_MUX_CTRL_6
	67	ldr r1, VAL_FUNC_MUX_CTRL_6
	68	str r1, [r0]
	69	ldr r0, REG_FUNC_MUX_CTRL_7
	70	ldr r1, VAL_FUNC_MUX_CTRL_7
	71	str r1, [r0]
	72	ldr r0, REG_FUNC_MUX_CTRL_8
	73	ldr r1, VAL_FUNC_MUX_CTRL_8
	74	str r1, [r0]
	75	ldr r0, REG_FUNC_MUX_CTRL_9
	76	ldr r1, VAL_FUNC_MUX_CTRL_9
	77	str r1, [r0]
	78	ldr r0, REG_FUNC_MUX_CTRL_A
	79	ldr r1, VAL_FUNC_MUX_CTRL_A
	80	str r1, [r0]
	81	ldr r0, REG_FUNC_MUX_CTRL_B
	82	ldr r1, VAL_FUNC_MUX_CTRL_B
	83	str r1, [r0]
	84	ldr r0, REG_FUNC_MUX_CTRL_C
	85	ldr r1, VAL_FUNC_MUX_CTRL_C
	86	str r1, [r0]
6f21347d WD	87	ldr r0, REG_FUNC_MUX_CTRL_D
	88	ldr r1, VAL_FUNC_MUX_CTRL_D
	89	str r1, [r0]
945af8d7 WD	90	ldr r0, REG_VOLTAGE_CTRL_0
	91	ldr r1, VAL_VOLTAGE_CTRL_0
	92	str r1, [r0]
	93	ldr r0, REG_TEST_DBG_CTRL_0
	94	ldr r1, VAL_TEST_DBG_CTRL_0
	95	str r1, [r0]
	96	ldr r0, REG_MOD_CONF_CTRL_0
	97	ldr r1, VAL_MOD_CONF_CTRL_0
	98	str r1, [r0]
2e5983d2	99
945af8d7 WD	100	/* Move to 1510 mode */
	101	ldr r0, REG_COMP_MODE_CTRL_0
	102	ldr r1, VAL_COMP_MODE_CTRL_0
	103	str r1, [r0]
2e5983d2	104
945af8d7 WD	105	/* Set up Traffic Ctlr*/
	106	ldr r0, REG_TC_IMIF_PRIO
	107	mov r1, #0x0
	108	str r1, [r0]
	109	ldr r0, REG_TC_EMIFS_PRIO
	110	str r1, [r0]
	111	ldr r0, REG_TC_EMIFF_PRIO
	112	str r1, [r0]
2e5983d2	113
945af8d7 WD	114	ldr r0, REG_TC_EMIFS_CONFIG
	115	ldr r1, [r0]
	116	bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */
	117	bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */
	118	str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */
2e5983d2	119
945af8d7 WD	120	/* Setup some clock domains */
	121	ldr r1, =OMAP1510_CLKS
	122	ldr r0, REG_ARM_IDLECT2
	123	strh r1, [r0] /* CLKM, Clock domain control. */
2e5983d2	124
945af8d7 WD	125	mov r1, #0x01 /* PER_EN bit */
	126	ldr r0, REG_ARM_RSTCT2
	127	strh r1, [r0] /* CLKM; Peripheral reset. */
2e5983d2	128
945af8d7 WD	129	/* Set CLKM to Sync-Scalable */
	130	/* I supposidly need to enable the dsp clock before switching */
	131	mov r1, #0x1000
	132	ldr r0, REG_ARM_SYSST
	133	strh r1, [r0]
	134	mov r0, #0x400
2e5983d2	135	1:
945af8d7 WD	136	subs r0, r0, #0x1 /* wait for any bubbles to finish */
945af8d7 WD	137	bne 1b
2e5983d2	138
945af8d7 WD	139	ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
	140	ldr r0, REG_ARM_CKCTL
	141	strh r1, [r0]
2e5983d2	142
945af8d7 WD	143	/* setup DPLL 1 */
	144	ldr r1, VAL_DPLL1_CTL
	145	ldr r0, REG_DPLL1_CTL
	146	strh r1, [r0]
	147	ands r1, r1, #0x10 /* Check if PLL is enabled. */
	148	beq lock_end /* Do not look for lock if BYPASS selected */
2e5983d2	149	2:
945af8d7 WD	150	ldrh r1, [r0]
	151	ands r1, r1, #0x01 /* Check the LOCK bit. */
	152	beq 2b /* ...loop until bit goes hi. */
2e5983d2 WD	153	lock_end:
2e5983d2 WD	154
945af8d7	155	/* Set memory timings corresponding to the new clock speed */
2e5983d2	156
945af8d7 WD	157	/* Check execution location to determine current execution location
	158	* and branch to appropriate initialization code.
	159	*/
	160	mov r0, #0x10000000 /* Load physical SDRAM base. */
	161	mov r1, pc /* Get current execution location. */
	162	cmp r1, r0 /* Compare. */
	163	bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
2e5983d2	164
945af8d7 WD	165	/*
	166	* Delay for SDRAM initialization.
	167	*/
	168	mov r3, #0x1800 /* value should be checked */
2e5983d2	169	3:
945af8d7 WD	170	subs r3, r3, #0x1 /* Decrement count */
945af8d7 WD	171	bne 3b
2e5983d2	172
945af8d7 WD	173	/*
	174	* Set SDRAM control values. Disable refresh before MRS command.
	175	*/
	176	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */
	177	bic r3, r0, #0xC /* (BIT3\|BIT2) ulConfig with auto-refresh disabled. */
	178	orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */
	179	orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */
	180	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
	181	str r3, [r2] /* Store the passed value with AR disabled. */
2e5983d2	182
945af8d7 WD	183	ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */
	184	ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */
	185	str r1, [r2] /* Store the passed value.*/
2e5983d2	186
945af8d7 WD	187	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
945af8d7 WD	188	str r0, [r2] /* Store the passed value. */
2e5983d2	189
945af8d7 WD	190	/*
	191	* Delay for SDRAM initialization.
	192	*/
	193	mov r3, #0x1800
2e5983d2	194	4:
945af8d7 WD	195	subs r3, r3, #1 /* Decrement count. */
945af8d7 WD	196	bne 4b
2e5983d2 WD	197
	198	skip_sdram:
	199
945af8d7 WD	200	/* slow interface */
	201	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
	202	ldr r0, REG_TC_EMIFS_CS0_CONFIG
	203	str r1, [r0] /* Chip Select 0 */
	204	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
	205	ldr r0, REG_TC_EMIFS_CS1_CONFIG
	206	str r1, [r0] /* Chip Select 1 */
	207	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
	208	ldr r0, REG_TC_EMIFS_CS2_CONFIG
	209	str r1, [r0] /* Chip Select 2 */
	210	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
	211	ldr r0, REG_TC_EMIFS_CS3_CONFIG
	212	str r1, [r0] /* Chip Select 3 */
2e5983d2 WD	213
	214	/* Next, Enable the RS232 Line Drivers in the FPGA. */
	215	/* Also, power on the audio CODEC's amplifier here, */
	216	/* which will make a noise on the audio output. */
	217	/* This is done here instead of in the kernel so there */
	218	/* isn't a loud popping noise at the start of each */
	219	/* song. */
	220	/* Also, disable the CODEC's clocks. */
	221	/* omap1510-HelenP1 [specific] */
	222
945af8d7 WD	223	ldr r0, REG_FPGA_POWER
	224	mov r1, #0
	225	ldr r2, REG_FPGA_DIP_SWITCH
	226	ldrb r3, [r2]
	227	cmp r3, #0x8
	228	movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */
	229	strb r1, [r0]
	230	ldr r0, REG_FPGA_AUDIO
	231	mov r1, #0x0 /* Disable sound driver (CODEC clocks) */
	232	strb r1, [r0]
2e5983d2	233
945af8d7	234	/* back to arch calling code */
2e5983d2 WD	235	mov pc, lr
	236
	237	/* the literal pools origin */
945af8d7	238	.ltorg
2e5983d2 WD	239
	240	/* OMAP configuration registers */
	241	REG_FUNC_MUX_CTRL_0: /* 32 bits */
	242	.word 0xfffe1000
	243	REG_FUNC_MUX_CTRL_1: /* 32 bits */
	244	.word 0xfffe1004
	245	REG_FUNC_MUX_CTRL_2: /* 32 bits */
	246	.word 0xfffe1008
	247	REG_COMP_MODE_CTRL_0: /* 32 bits */
	248	.word 0xfffe100c
	249	REG_FUNC_MUX_CTRL_3: /* 32 bits */
	250	.word 0xfffe1010
	251	REG_FUNC_MUX_CTRL_4: /* 32 bits */
	252	.word 0xfffe1014
	253	REG_FUNC_MUX_CTRL_5: /* 32 bits */
	254	.word 0xfffe1018
	255	REG_FUNC_MUX_CTRL_6: /* 32 bits */
	256	.word 0xfffe101c
	257	REG_FUNC_MUX_CTRL_7: /* 32 bits */
	258	.word 0xfffe1020
	259	REG_FUNC_MUX_CTRL_8: /* 32 bits */
	260	.word 0xfffe1024
	261	REG_FUNC_MUX_CTRL_9: /* 32 bits */
	262	.word 0xfffe1028
	263	REG_FUNC_MUX_CTRL_A: /* 32 bits */
	264	.word 0xfffe102C
	265	REG_FUNC_MUX_CTRL_B: /* 32 bits */
	266	.word 0xfffe1030
	267	REG_FUNC_MUX_CTRL_C: /* 32 bits */
	268	.word 0xfffe1034
	269	REG_FUNC_MUX_CTRL_D: /* 32 bits */
	270	.word 0xfffe1038
	271	REG_PULL_DWN_CTRL_0: /* 32 bits */
	272	.word 0xfffe1040
	273	REG_PULL_DWN_CTRL_1: /* 32 bits */
	274	.word 0xfffe1044
	275	REG_PULL_DWN_CTRL_2: /* 32 bits */
	276	.word 0xfffe1048
	277	REG_PULL_DWN_CTRL_3: /* 32 bits */
	278	.word 0xfffe104c
	279	REG_VOLTAGE_CTRL_0: /* 32 bits */
	280	.word 0xfffe1060
	281	REG_TEST_DBG_CTRL_0: /* 32 bits */
	282	.word 0xfffe1070
	283	REG_MOD_CONF_CTRL_0: /* 32 bits */
	284	.word 0xfffe1080
	285	REG_TC_IMIF_PRIO: /* 32 bits */
	286	.word 0xfffecc00
	287	REG_TC_EMIFS_PRIO: /* 32 bits */
	288	.word 0xfffecc04
	289	REG_TC_EMIFF_PRIO: /* 32 bits */
	290	.word 0xfffecc08
	291	REG_TC_EMIFS_CONFIG: /* 32 bits */
	292	.word 0xfffecc0c
	293	REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
945af8d7	294	.word 0xfffecc10
2e5983d2	295	REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
945af8d7	296	.word 0xfffecc14
2e5983d2	297	REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
945af8d7	298	.word 0xfffecc18
2e5983d2	299	REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
945af8d7	300	.word 0xfffecc1c
2e5983d2 WD	301	REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
	302	.word 0xfffecc20
	303	REG_TC_EMIFF_MRS: /* 32 bits */
	304	.word 0xfffecc24
	305	/* MPU clock/reset/power mode control registers */
	306	REG_ARM_CKCTL: /* 16 bits */
	307	.word 0xfffece00
	308	REG_ARM_IDLECT2: /* 16 bits */
945af8d7	309	.word 0xfffece08
2e5983d2	310	REG_ARM_RSTCT2: /* 16 bits */
945af8d7	311	.word 0xfffece14
2e5983d2	312	REG_ARM_SYSST: /* 16 bits */
945af8d7	313	.word 0xfffece18
2e5983d2 WD	314	/* DPLL control registers */
	315	REG_DPLL1_CTL: /* 16 bits */
	316	.word 0xfffecf00
	317	/* identification code register */
	318	REG_IDCODE: /* 32 bits */
945af8d7	319	.word 0xfffed404
2e5983d2 WD	320
	321	/* Innovator specific */
	322	REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */
945af8d7	323	.word 0x08000003
2e5983d2	324	REG_FPGA_POWER: /* 8 bits */
945af8d7	325	.word 0x08000005
2e5983d2 WD	326	REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */
	327	.word 0x0800000c
	328	REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */
945af8d7	329	.word 0x0800000e
2e5983d2 WD	330
	331	VAL_COMP_MODE_CTRL_0:
	332	.word 0x0000eaef
	333	VAL_FUNC_MUX_CTRL_4:
	334	.word 0x00000000
	335	VAL_FUNC_MUX_CTRL_5:
	336	.word 0x00000000
	337	VAL_FUNC_MUX_CTRL_6:
	338	.word 0x00000001
	339	VAL_FUNC_MUX_CTRL_7:
	340	.word 0x00000000
	341	VAL_FUNC_MUX_CTRL_8:
	342	.word 0x10001200
	343	VAL_FUNC_MUX_CTRL_9:
	344	.word 0x01201012
	345	VAL_FUNC_MUX_CTRL_A:
	346	.word 0x00000248
	347	VAL_FUNC_MUX_CTRL_B:
	348	.word 0x00000248
	349	VAL_FUNC_MUX_CTRL_C:
	350	.word 0x09000000
	351	VAL_FUNC_MUX_CTRL_D:
	352	.word 0x00000000
	353	VAL_PULL_DWN_CTRL_0:
	354	.word 0x11a10000
	355	VAL_PULL_DWN_CTRL_1:
	356	.word 0x2e047fff
	357	VAL_PULL_DWN_CTRL_2:
6f21347d	358	.word 0xffd603a6
2e5983d2	359	VAL_PULL_DWN_CTRL_3:
6f21347d	360	.word 0x00003e03
2e5983d2 WD	361	VAL_VOLTAGE_CTRL_0:
	362	.word 0x00000007
	363	VAL_TEST_DBG_CTRL_0:
	364	/* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
945af8d7 WD	365	* This slows down internal SRAM accesses.
945af8d7 WD	366	*/
2e5983d2 WD	367	.word 0x00000007
	368	VAL_MOD_CONF_CTRL_0:
	369	.word 0x0b000008
	370	VAL_ARM_CKCTL:
	371	.word 0x010f
	372	VAL_DPLL1_CTL:
	373	.word 0x2710
	374	VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
	375	.word 0x00001149
	376	VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
	377	.word 0x00004158
	378	VAL_TC_EMIFS_CS0_CONFIG:
	379	.word 0x002130b0
	380	VAL_TC_EMIFS_CS1_CONFIG:
	381	.word 0x0000f559
	382	VAL_TC_EMIFS_CS2_CONFIG:
	383	.word 0x000055f0
	384	VAL_TC_EMIFS_CS3_CONFIG:
	385	.word 0x00003331
	386	VAL_TC_EMIFF_SDRAM_CONFIG:
	387	.word 0x010290fc
	388	VAL_TC_EMIFF_MRS:
	389	.word 0x00000027