[people/ms/u-boot.git] / board / omap1610inn / platform.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2003
 * Texas Instruments, <www.ti.com>
 * Kshitij Gupta <Kshitij@ti.com>
 *
 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>

#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#endif


_TEXT_BASE:
	.word	TEXT_BASE	/* sdram load addr from config.mk */

.globl platformsetup
platformsetup:


	/*------------------------------------------------------*
	 *mask all IRQs by setting all bits in the INTMR default*
	 *------------------------------------------------------*/
	mov	r1, #0xffffffff
	ldr	r0, =REG_IHL1_MIR
	str	r1, [r0]
	ldr	r0, =REG_IHL2_MIR
	str	r1, [r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT1)                   *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT1
	ldr	r1,	VAL_ARM_IDLECT1
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT2)  		        *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT2
	ldr	r1,	VAL_ARM_IDLECT2
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT3)		        *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT3
	ldr	r1,	VAL_ARM_IDLECT3
	str	r1,	[r0]


	mov	r1,	#0x01		/* PER_EN bit */
	ldr	r0,	REG_ARM_RSTCT2
	strh	r1,	[r0]		/* CLKM; Peripheral reset. */

	/* Set CLKM to Sync-Scalable	*/
	/* I supposedly need to enable the dsp clock before switching */
	mov	r1,	#0x0000
	ldr	r0,	REG_ARM_SYSST
	strh	r1,	[r0]
	mov	r0,	#0x400
1:
	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
	bne	1b
	ldr	r1,	VAL_ARM_CKCTL
	ldr	r0,	REG_ARM_CKCTL
	strh	r1,	[r0]

	/* a few nops to let settle */
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

	/* setup DPLL 1 */
	/* Ramp up the clock to 96Mhz */
	ldr	r1,	VAL_DPLL1_CTL
	ldr	r0,	REG_DPLL1_CTL
	strh	r1,	[r0]
	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
	beq	lock_end	/* Do not look for lock if BYPASS selected */
2:
	ldrh	r1,	[r0]
	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
	beq 2b			/*	loop until bit goes hi. */
lock_end:


	/*------------------------------------------------------*
	 * Turn off the watchdog during init...			*
 	 *------------------------------------------------------*/
	ldr	r0,	REG_WATCHDOG
	ldr	r1,	WATCHDOG_VAL1
	str	r1,	[r0]
	ldr	r1,	WATCHDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL1
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG

watch1Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch1Wait

	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG
watch2Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch2Wait


	/* Set memory timings corresponding to the new clock speed */

	/* Check execution location to determine current execution location
	 * and branch to appropriate initialization code.
	 */
	/* Load physical SDRAM base. */
	mov 	r0, 	#0x10000000
	/* Get current execution location. */
	mov 	r1, 	pc
	/* Compare. */
	cmp 	r1, 	r0
	/* Skip over EMIF-fast initialization if running from SDRAM. */
	bge 	skip_sdram

	/*
	* Delay for SDRAM initialization.
	*/
	mov	r3,	#0x1800		/* value should be checked */
3:
	subs	r3,	r3,	#0x1	/* Decrement count */
	bne 	3b


	/*
	 * Set SDRAM control values. Disable refresh before MRS command.
	 */

	/* mobile ddr operation */
	ldr	r0,	REG_SDRAM_OPERATION
	mov	r2,	#07
	str	r2,	[r0]

	/* config register */
	ldr	r0,	REG_SDRAM_CONFIG
	ldr	r1,	SDRAM_CONFIG_VAL
	str	r1,	[r0]

	/* manual command register */
	ldr	r0,	REG_SDRAM_MANUAL_CMD
	/* issue set cke high */
	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
	str	r1,	[r0]
	/* issue nop */
	mov	r1,	#CMD_SDRAM_NOP
	str	r1,	[r0]

	mov	r2,	#0x0100
waitMDDR1:
	subs	r2,	r2,	 #1
	bne	waitMDDR1	/* delay loop */

	/* issue precharge */
	mov	r1,	#CMD_SDRAM_PRECHARGE
	str	r1,	[r0]

	/* issue autorefresh x 2 */
	mov	r1,	#CMD_SDRAM_AUTOREFRESH
	str	r1,	[r0]
	str	r1,	[r0]

	/* mrs register ddr mobile */
	ldr	r0,	REG_SDRAM_MRS
	mov	r1,	#0x33
	str	r1,	[r0]

	/* emrs1 low-power register */
	ldr	r0,	REG_SDRAM_EMRS1
	/* self refresh on all banks */
	mov	r1,	#0
	str	r1,	[r0]

	ldr	r0,	REG_DLL_URD_CONTROL
	ldr	r1,	DLL_URD_CONTROL_VAL
	str	r1,	[r0]

	ldr	r0,	REG_DLL_LRD_CONTROL
	ldr	r1,	DLL_LRD_CONTROL_VAL
	str	r1,	[r0]

	ldr	r0,	REG_DLL_WRT_CONTROL
	ldr	r1,	DLL_WRT_CONTROL_VAL
	str	r1,	[r0]

	/* delay loop */
	mov	r2,	#0x0100
waitMDDR2:
	subs	r2,	r2,	#1
	bne	waitMDDR2

	/*
	 * Delay for SDRAM initialization.
	 */
	mov	r3,	#0x1800
4:
	subs	r3,	r3,	#1	/* Decrement count. */
	bne	4b
	b	common_tc

skip_sdram:

	ldr	r0,	REG_SDRAM_CONFIG
	ldr	r1,	SDRAM_CONFIG_VAL
	str	r1,	[r0]

common_tc:
	/* slow interface */
	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
	str	r1,	[r0] /* Chip Select 0 */

	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
	str	r1,	[r0] /* Chip Select 1 */
	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
	str	r1,	[r0] /* Chip Select 3 */

#ifdef CONFIG_H2_OMAP1610
	/* inserting additional 2 clock cycle hold time for LAN */
	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
	str     r1,     [r0]
#endif
	/* Start MPU Timer 1 */
	ldr	r0,	REG_MPU_LOAD_TIMER
	ldr	r1,	VAL_MPU_LOAD_TIMER
	str	r1,	[r0]

	ldr	r0,	REG_MPU_CNTL_TIMER
	ldr	r1,	VAL_MPU_CNTL_TIMER
	str	r1,	[r0]

	/* back to arch calling code */
	mov	pc,	lr

	/* the literal pools origin */
	.ltorg


REG_TC_EMIFS_CONFIG:		/* 32 bits */
	.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
	.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
	.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
	.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
	.word 0xfffecc1c

#ifdef CONFIG_H2_OMAP1610
REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
	.word 0xfffecc54
#endif

/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL:			/* 16 bits */
	.word 0xfffece00

REG_ARM_IDLECT3:		/* 16 bits */
	.word 0xfffece24
REG_ARM_IDLECT2:		/* 16 bits */
	.word 0xfffece08
REG_ARM_IDLECT1:		/* 16 bits */
	.word 0xfffece04

REG_ARM_RSTCT2:			/* 16 bits */
	.word 0xfffece14
REG_ARM_SYSST:			/* 16 bits */
	.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL:			/* 16 bits */
	.word 0xfffecf00

/* Watch Dog register */
/* secure watchdog stop */
REG_WSPRDOG:
	.word 0xfffeb048
/* watchdog write pending */
REG_WWPSDOG:
	.word 0xfffeb034

WSPRDOG_VAL1:
	.word 0x0000aaaa
WSPRDOG_VAL2:
	.word 0x00005555

/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
 counter @8192 rows, 10 ns, 8 burst */
REG_SDRAM_CONFIG:
	.word 0xfffecc20

/* Operation register */
REG_SDRAM_OPERATION:
	.word 0xfffecc80

/* Manual command register */
REG_SDRAM_MANUAL_CMD:
	.word 0xfffecc84

/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
REG_SDRAM_MRS:
	.word 0xfffecc70

/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
REG_SDRAM_EMRS1:
	.word 0xfffecc78

/* WRT DLL register */
REG_DLL_WRT_CONTROL:
	.word 0xfffecc68
DLL_WRT_CONTROL_VAL:
	.word 0x03f00002

/* URD DLL register */
REG_DLL_URD_CONTROL:
	.word 0xfffeccc0
DLL_URD_CONTROL_VAL:
	.word 0x00800002

/* LRD DLL register */
REG_DLL_LRD_CONTROL:
	.word 0xfffecccc

REG_WATCHDOG:
	.word 0xfffec808

REG_MPU_LOAD_TIMER:
	.word 0xfffec600
REG_MPU_CNTL_TIMER:
	.word 0xfffec500

/* 96 MHz Samsung Mobile DDR */
SDRAM_CONFIG_VAL:
	.word 0x001200f4

DLL_LRD_CONTROL_VAL:
	.word 0x00800002

VAL_ARM_CKCTL:
	.word 0x3000
VAL_DPLL1_CTL:
	.word 0x2830

#ifdef CONFIG_INNOVATOROMAP1610
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x00001131
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x88011131
#endif

#ifdef CONFIG_H2_OMAP1610
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x00203331
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x8180fff3
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0xf800f22a
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x88011131
VAL_TC_EMIFS_CS1_ADVANCED:
	.word 0x00000022
#endif

VAL_TC_EMIFF_SDRAM_CONFIG:
	.word 0x010290fc
VAL_TC_EMIFF_MRS:
	.word 0x00000027

VAL_ARM_IDLECT1:
	.word 0x00000400

VAL_ARM_IDLECT2:
	.word 0x00000886
VAL_ARM_IDLECT3:
	.word 0x00000015

WATCHDOG_VAL1:
	.word 0x000000f5
WATCHDOG_VAL2:
	.word 0x000000a0

VAL_MPU_LOAD_TIMER:
	.word 0xffffffff
VAL_MPU_CNTL_TIMER:
	.word 0xffffffa1

/* command values */
.equ CMD_SDRAM_NOP,		0x00000000
.equ CMD_SDRAM_PRECHARGE,	0x00000001
.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007
Commit	Line	Data
6f21347d WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2003
	5	* Texas Instruments, <www.ti.com>
	6	* Kshitij Gupta <Kshitij@ti.com>
	7	*
63e73c9a	8	* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
028ab6b5	9	*
6f21347d WD	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <config.h>
	30	#include <version.h>
	31
	32	#if defined(CONFIG_OMAP1610)
	33	#include <./configs/omap1510.h>
	34	#endif
	35
	36
	37	_TEXT_BASE:
	38	.word TEXT_BASE /* sdram load addr from config.mk */
	39
	40	.globl platformsetup
	41	platformsetup:
	42
	43
80885a9d WD	44	/------------------------------------------------------
	45	mask all IRQs by setting all bits in the INTMR default
	46	------------------------------------------------------/
0c852a28 WD	47	mov r1, #0xffffffff
	48	ldr r0, =REG_IHL1_MIR
	49	str r1, [r0]
	50	ldr r0, =REG_IHL2_MIR
	51	str r1, [r0]
80885a9d	52
6f21347d WD	53	/------------------------------------------------------
	54	* Set up ARM CLM registers (IDLECT1) *
	55	------------------------------------------------------/
	56	ldr r0, REG_ARM_IDLECT1
	57	ldr r1, VAL_ARM_IDLECT1
	58	str r1, [r0]
	59
	60	/------------------------------------------------------
	61	* Set up ARM CLM registers (IDLECT2) *
	62	------------------------------------------------------/
	63	ldr r0, REG_ARM_IDLECT2
	64	ldr r1, VAL_ARM_IDLECT2
	65	str r1, [r0]
	66
	67	/------------------------------------------------------
	68	* Set up ARM CLM registers (IDLECT3) *
	69	------------------------------------------------------/
	70	ldr r0, REG_ARM_IDLECT3
	71	ldr r1, VAL_ARM_IDLECT3
	72	str r1, [r0]
	73
	74
	75	mov r1, #0x01 /* PER_EN bit */
	76	ldr r0, REG_ARM_RSTCT2
	77	strh r1, [r0] /* CLKM; Peripheral reset. */
	78
	79	/* Set CLKM to Sync-Scalable */
	80	/* I supposedly need to enable the dsp clock before switching */
	81	mov r1, #0x0000
	82	ldr r0, REG_ARM_SYSST
	83	strh r1, [r0]
	84	mov r0, #0x400
	85	1:
	86	subs r0, r0, #0x1 /* wait for any bubbles to finish */
	87	bne 1b
	88	ldr r1, VAL_ARM_CKCTL
	89	ldr r0, REG_ARM_CKCTL
	90	strh r1, [r0]
	91
	92	/* a few nops to let settle */
	93	nop
	94	nop
	95	nop
	96	nop
	97	nop
	98	nop
	99	nop
	100	nop
	101	nop
	102	nop
	103
	104	/* setup DPLL 1 */
	105	/* Ramp up the clock to 96Mhz */
	106	ldr r1, VAL_DPLL1_CTL
	107	ldr r0, REG_DPLL1_CTL
	108	strh r1, [r0]
	109	ands r1, r1, #0x10 /* Check if PLL is enabled. */
	110	beq lock_end /* Do not look for lock if BYPASS selected */
	111	2:
	112	ldrh r1, [r0]
	113	ands r1, r1, #0x01 /* Check the LOCK bit.*/
	114	beq 2b /* loop until bit goes hi. */
	115	lock_end:
	116
117
118	/------------------------------------------------------
119	* Turn off the watchdog during init... *
120	------------------------------------------------------/
121	ldr r0, REG_WATCHDOG
122	ldr r1, WATCHDOG_VAL1
123	str r1, [r0]
124	ldr r1, WATCHDOG_VAL2
125	str r1, [r0]
126	ldr r0, REG_WSPRDOG
127	ldr r1, WSPRDOG_VAL1
128	str r1, [r0]
129	ldr r0, REG_WWPSDOG
130
131	watch1Wait:
132	ldr r1, [r0]
133	tst r1, #0x10
134	bne watch1Wait
135
136	ldr r0, REG_WSPRDOG
137	ldr r1, WSPRDOG_VAL2
138	str r1, [r0]
139	ldr r0, REG_WWPSDOG
140	watch2Wait:
141	ldr r1, [r0]
142	tst r1, #0x10
143	bne watch2Wait
144
145
6f21347d WD	146	/* Set memory timings corresponding to the new clock speed */
	147
	148	/* Check execution location to determine current execution location
	149	* and branch to appropriate initialization code.
	150	*/
	151	/* Load physical SDRAM base. */
	152	mov r0, #0x10000000
	153	/* Get current execution location. */
	154	mov r1, pc
	155	/* Compare. */
	156	cmp r1, r0
	157	/* Skip over EMIF-fast initialization if running from SDRAM. */
	158	bge skip_sdram
	159
	160	/*
	161	* Delay for SDRAM initialization.
	162	*/
	163	mov r3, #0x1800 /* value should be checked */
	164	3:
	165	subs r3, r3, #0x1 /* Decrement count */
	166	bne 3b
	167
	168
	169	/*
	170	* Set SDRAM control values. Disable refresh before MRS command.
	171	*/
	172
	173	/* mobile ddr operation */
	174	ldr r0, REG_SDRAM_OPERATION
	175	mov r2, #07
	176	str r2, [r0]
	177
	178	/* config register */
	179	ldr r0, REG_SDRAM_CONFIG
	180	ldr r1, SDRAM_CONFIG_VAL
	181	str r1, [r0]
	182
	183	/* manual command register */
	184	ldr r0, REG_SDRAM_MANUAL_CMD
	185	/* issue set cke high */
	186	mov r1, #CMD_SDRAM_CKE_SET_HIGH
	187	str r1, [r0]
	188	/* issue nop */
	189	mov r1, #CMD_SDRAM_NOP
	190	str r1, [r0]
	191
	192	mov r2, #0x0100
	193	waitMDDR1:
	194	subs r2, r2, #1
	195	bne waitMDDR1 /* delay loop */
	196
	197	/* issue precharge */
	198	mov r1, #CMD_SDRAM_PRECHARGE
	199	str r1, [r0]
	200
	201	/* issue autorefresh x 2 */
	202	mov r1, #CMD_SDRAM_AUTOREFRESH
	203	str r1, [r0]
	204	str r1, [r0]
	205
	206	/* mrs register ddr mobile */
	207	ldr r0, REG_SDRAM_MRS
	208	mov r1, #0x33
	209	str r1, [r0]
210
211	/* emrs1 low-power register */
212	ldr r0, REG_SDRAM_EMRS1
213	/* self refresh on all banks */
214	mov r1, #0
215	str r1, [r0]
216
217	ldr r0, REG_DLL_URD_CONTROL
218	ldr r1, DLL_URD_CONTROL_VAL
219	str r1, [r0]
220
221	ldr r0, REG_DLL_LRD_CONTROL
222	ldr r1, DLL_LRD_CONTROL_VAL
223	str r1, [r0]
224
225	ldr r0, REG_DLL_WRT_CONTROL
226	ldr r1, DLL_WRT_CONTROL_VAL
227	str r1, [r0]
228
229	/* delay loop */
230	mov r2, #0x0100
231	waitMDDR2:
232	subs r2, r2, #1
233	bne waitMDDR2
234
235	/*
236	* Delay for SDRAM initialization.
237	*/
238	mov r3, #0x1800
239	4:
240	subs r3, r3, #1 /* Decrement count. */
241	bne 4b
242	b common_tc
243
244	skip_sdram:
245
246	ldr r0, REG_SDRAM_CONFIG
247	ldr r1, SDRAM_CONFIG_VAL
248	str r1, [r0]
249
250	common_tc:
251	/* slow interface */
252	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
253	ldr r0, REG_TC_EMIFS_CS0_CONFIG
254	str r1, [r0] /* Chip Select 0 */
255
256	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
257	ldr r0, REG_TC_EMIFS_CS1_CONFIG
258	str r1, [r0] /* Chip Select 1 */
259	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
260	ldr r0, REG_TC_EMIFS_CS3_CONFIG
261	str r1, [r0] /* Chip Select 3 */
63e73c9a	262
028ab6b5	263	#ifdef CONFIG_H2_OMAP1610
63e73c9a WD	264	/* inserting additional 2 clock cycle hold time for LAN */
	265	ldr r0, REG_TC_EMIFS_CS1_ADVANCED
	266	ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
	267	str r1, [r0]
	268	#endif
	269	/* Start MPU Timer 1 */
	270	ldr r0, REG_MPU_LOAD_TIMER
	271	ldr r1, VAL_MPU_LOAD_TIMER
	272	str r1, [r0]
	273
	274	ldr r0, REG_MPU_CNTL_TIMER
	275	ldr r1, VAL_MPU_CNTL_TIMER
	276	str r1, [r0]
	277
6f21347d WD	278	/* back to arch calling code */
	279	mov pc, lr
	280
	281	/* the literal pools origin */
	282	.ltorg
	283
	284
	285	REG_TC_EMIFS_CONFIG: /* 32 bits */
	286	.word 0xfffecc0c
	287	REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
	288	.word 0xfffecc10
	289	REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
	290	.word 0xfffecc14
	291	REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
	292	.word 0xfffecc18
	293	REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
	294	.word 0xfffecc1c
	295
63e73c9a WD	296	#ifdef CONFIG_H2_OMAP1610
	297	REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
	298	.word 0xfffecc54
	299	#endif
	300
6f21347d WD	301	/* MPU clock/reset/power mode control registers */
	302	REG_ARM_CKCTL: /* 16 bits */
	303	.word 0xfffece00
	304
	305	REG_ARM_IDLECT3: /* 16 bits */
	306	.word 0xfffece24
	307	REG_ARM_IDLECT2: /* 16 bits */
42d1f039	308	.word 0xfffece08
6f21347d WD	309	REG_ARM_IDLECT1: /* 16 bits */
	310	.word 0xfffece04
	311
	312	REG_ARM_RSTCT2: /* 16 bits */
	313	.word 0xfffece14
	314	REG_ARM_SYSST: /* 16 bits */
	315	.word 0xfffece18
	316	/* DPLL control registers */
	317	REG_DPLL1_CTL: /* 16 bits */
	318	.word 0xfffecf00
	319
	320	/* Watch Dog register */
	321	/* secure watchdog stop */
	322	REG_WSPRDOG:
	323	.word 0xfffeb048
	324	/* watchdog write pending */
	325	REG_WWPSDOG:
42d1f039	326	.word 0xfffeb034
6f21347d WD	327
	328	WSPRDOG_VAL1:
	329	.word 0x0000aaaa
	330	WSPRDOG_VAL2:
	331	.word 0x00005555
	332
	333	/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
	334	counter @8192 rows, 10 ns, 8 burst */
	335	REG_SDRAM_CONFIG:
	336	.word 0xfffecc20
	337
	338	/* Operation register */
	339	REG_SDRAM_OPERATION:
	340	.word 0xfffecc80
	341
	342	/* Manual command register */
	343	REG_SDRAM_MANUAL_CMD:
	344	.word 0xfffecc84
	345
	346	/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
	347	REG_SDRAM_MRS:
	348	.word 0xfffecc70
	349
	350	/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
	351	REG_SDRAM_EMRS1:
	352	.word 0xfffecc78
	353
	354	/* WRT DLL register */
	355	REG_DLL_WRT_CONTROL:
	356	.word 0xfffecc68
	357	DLL_WRT_CONTROL_VAL:
	358	.word 0x03f00002
	359
	360	/* URD DLL register */
	361	REG_DLL_URD_CONTROL:
	362	.word 0xfffeccc0
	363	DLL_URD_CONTROL_VAL:
	364	.word 0x00800002
	365
	366	/* LRD DLL register */
	367	REG_DLL_LRD_CONTROL:
	368	.word 0xfffecccc
	369
	370	REG_WATCHDOG:
	371	.word 0xfffec808
	372
63e73c9a WD	373	REG_MPU_LOAD_TIMER:
	374	.word 0xfffec600
	375	REG_MPU_CNTL_TIMER:
	376	.word 0xfffec500
	377
6f21347d WD	378	/* 96 MHz Samsung Mobile DDR */
6f21347d WD	379	SDRAM_CONFIG_VAL:
42d1f039	380	.word 0x001200f4
6f21347d WD	381
	382	DLL_LRD_CONTROL_VAL:
	383	.word 0x00800002
	384
	385	VAL_ARM_CKCTL:
	386	.word 0x3000
	387	VAL_DPLL1_CTL:
	388	.word 0x2830
	389
63e73c9a	390	#ifdef CONFIG_INNOVATOROMAP1610
6f21347d WD	391	VAL_TC_EMIFS_CS0_CONFIG:
	392	.word 0x002130b0
	393	VAL_TC_EMIFS_CS1_CONFIG:
	394	.word 0x00001131
	395	VAL_TC_EMIFS_CS2_CONFIG:
	396	.word 0x000055f0
	397	VAL_TC_EMIFS_CS3_CONFIG:
	398	.word 0x88011131
63e73c9a WD	399	#endif
	400
	401	#ifdef CONFIG_H2_OMAP1610
	402	VAL_TC_EMIFS_CS0_CONFIG:
	403	.word 0x00203331
	404	VAL_TC_EMIFS_CS1_CONFIG:
	405	.word 0x8180fff3
	406	VAL_TC_EMIFS_CS2_CONFIG:
	407	.word 0xf800f22a
	408	VAL_TC_EMIFS_CS3_CONFIG:
	409	.word 0x88011131
	410	VAL_TC_EMIFS_CS1_ADVANCED:
	411	.word 0x00000022
	412	#endif
	413
6f21347d WD	414	VAL_TC_EMIFF_SDRAM_CONFIG:
	415	.word 0x010290fc
	416	VAL_TC_EMIFF_MRS:
	417	.word 0x00000027
	418
	419	VAL_ARM_IDLECT1:
	420	.word 0x00000400
	421
	422	VAL_ARM_IDLECT2:
	423	.word 0x00000886
	424	VAL_ARM_IDLECT3:
	425	.word 0x00000015
	426
	427	WATCHDOG_VAL1:
	428	.word 0x000000f5
	429	WATCHDOG_VAL2:
	430	.word 0x000000a0
	431
63e73c9a WD	432	VAL_MPU_LOAD_TIMER:
	433	.word 0xffffffff
	434	VAL_MPU_CNTL_TIMER:
	435	.word 0xffffffa1
	436
6f21347d WD	437	/* command values */
	438	.equ CMD_SDRAM_NOP, 0x00000000
	439	.equ CMD_SDRAM_PRECHARGE, 0x00000001
	440	.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
	441	.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007