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413ab5b0 TM |
1 | /****************************************************************************** |
2 | * | |
3 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | *****************************************************************************/ | |
7 | ||
8 | #ifdef __cplusplus | |
9 | extern "C" { | |
10 | #endif | |
11 | ||
12 | #define OPCODE_EXIT 0U | |
13 | #define OPCODE_CLEAR 1U | |
14 | #define OPCODE_WRITE 2U | |
15 | #define OPCODE_MASKWRITE 3U | |
16 | #define OPCODE_MASKPOLL 4U | |
17 | #define OPCODE_MASKDELAY 5U | |
18 | ||
19 | /* Encode number of arguments in last nibble */ | |
20 | #define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) | |
21 | #define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val | |
22 | #define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) ,\ | |
23 | addr, mask, val | |
24 | #define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) ,\ | |
25 | addr, mask | |
26 | #define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) ,\ | |
27 | addr, mask | |
28 | ||
29 | /* Returns codes of PS7_Init */ | |
30 | #define PS7_INIT_SUCCESS (0) | |
31 | #define PS7_INIT_CORRUPT (1) | |
32 | #define PS7_INIT_TIMEOUT (2) | |
33 | #define PS7_POLL_FAILED_DDR_INIT (3) | |
34 | #define PS7_POLL_FAILED_DMA (4) | |
35 | #define PS7_POLL_FAILED_PLL (5) | |
36 | ||
37 | /* Freq of all peripherals */ | |
38 | ||
39 | #define APU_FREQ 650000000 | |
40 | #define DDR_FREQ 525000000 | |
41 | #define DCI_FREQ 10096154 | |
42 | #define QSPI_FREQ 200000000 | |
43 | #define SMC_FREQ 10000000 | |
44 | #define ENET0_FREQ 125000000 | |
45 | #define ENET1_FREQ 10000000 | |
46 | #define USB0_FREQ 60000000 | |
47 | #define USB1_FREQ 60000000 | |
48 | #define SDIO_FREQ 100000000 | |
49 | #define UART_FREQ 100000000 | |
50 | #define SPI_FREQ 10000000 | |
51 | #define I2C_FREQ 108333336 | |
52 | #define WDT_FREQ 108333336 | |
53 | #define TTC_FREQ 50000000 | |
54 | #define CAN_FREQ 10000000 | |
55 | #define PCAP_FREQ 200000000 | |
56 | #define TPIU_FREQ 200000000 | |
57 | #define FPGA0_FREQ 50000000 | |
58 | #define FPGA1_FREQ 10000000 | |
59 | #define FPGA2_FREQ 10000000 | |
60 | #define FPGA3_FREQ 10000000 | |
61 | ||
62 | ||
63 | /* For delay calculation using global registers*/ | |
64 | #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 | |
65 | #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 | |
66 | #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 | |
67 | #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 | |
68 | ||
69 | int ps7_config(unsigned long *); | |
70 | int ps7_init(void); | |
71 | int ps7_post_config(void); | |
413ab5b0 TM |
72 | |
73 | void perf_start_clock(void); | |
74 | void perf_disable_clock(void); | |
75 | void perf_reset_clock(void); | |
76 | void perf_reset_and_start_timer(void); | |
77 | int get_number_of_cycles_for_delay(unsigned int delay); | |
78 | #ifdef __cplusplus | |
79 | } | |
80 | #endif |