[people/ms/u-boot.git] / board / pb1x00 / pb1x00.c

/*
 * (C) Copyright 2003
 * Thomas.Lange@corelatus.se
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <mach/au1x00.h>
#include <asm/mipsregs.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

int initdram(void)
{
	/* Sdram is setup by assembler code */
	/* If memory could be changed, we should return the true value here */
	gd->ram_size = 64 * 1024 * 1024;

	return 0;
}

#define BCSR_PCMCIA_PC0DRVEN		0x0010
#define BCSR_PCMCIA_PC0RST		0x0080

/* In arch/mips/cpu/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );

int checkboard (void)
{
#if defined(CONFIG_IDE_PCMCIA) && 0
	u16 status;
#endif
	/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
	u32 proc_id;

	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */

	proc_id = read_c0_prid();

	switch (proc_id >> 24) {
	case 0:
		puts ("Board: Pb1000\n");
		printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
		break;
	case 1:
		puts ("Board: Pb1500\n");
		printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
		break;
	case 2:
		puts ("Board: Pb1100\n");
		printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
		break;
	default:
		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
	}

	set_io_port_base(0);

#if defined(CONFIG_IDE_PCMCIA) && 0
	/* Enable 3.3 V on slot 0 ( VCC )
	   No 5V */
	status = 4;
	*pcmcia_bcsr = status;

	status |= BCSR_PCMCIA_PC0DRVEN;
	*pcmcia_bcsr = status;
	au_sync();

	udelay(300*1000);

	status |= BCSR_PCMCIA_PC0RST;
	*pcmcia_bcsr = status;
	au_sync();

	udelay(100*1000);

	/* PCMCIA is on a 36 bit physical address.
	   We need to map it into a 32 bit addresses */

#if 0
	/* We dont need theese unless we run whole pcmcia package */
	write_one_tlb(20,                 /* index */
		      0x01ffe000,         /* Pagemask, 16 MB pages */
		      CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
		      0x3C000017,         /* Lo0 */
		      0x3C200017);        /* Lo1 */

	write_one_tlb(21,                   /* index */
		      0x01ffe000,           /* Pagemask, 16 MB pages */
		      CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
		      0x3D000017,           /* Lo0 */
		      0x3D200017);          /* Lo1 */
#endif	/* 0 */
	write_one_tlb(22,                   /* index */
		      0x01ffe000,           /* Pagemask, 16 MB pages */
		      CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
		      0x3E000017,           /* Lo0 */
		      0x3E200017);          /* Lo1 */
#endif	/* CONFIG_IDE_PCMCIA */

	return 0;
}
Commit	Line	Data
265817c7 WD	1	/*
	2	* (C) Copyright 2003
	3	* Thomas.Lange@corelatus.se
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
265817c7 WD	6	*/
	7
	8	#include <common.h>
	9	#include <command.h>
76ada5f8	10	#include <mach/au1x00.h>
265817c7	11	#include <asm/mipsregs.h>
5c15010e	12	#include <asm/io.h>
265817c7	13
088454cd SG	14	DECLARE_GLOBAL_DATA_PTR;
	15
	16	int initdram(void)
265817c7 WD	17	{
	18	/* Sdram is setup by assembler code */
	19	/* If memory could be changed, we should return the true value here */
088454cd SG	20	gd->ram_size = 64 * 1024 * 1024;
	21
	22	return 0;
265817c7 WD	23	}
	24
	25	#define BCSR_PCMCIA_PC0DRVEN 0x0010
	26	#define BCSR_PCMCIA_PC0RST 0x0080
	27
1e3827d9	28	/* In arch/mips/cpu/cpu.c */
265817c7 WD	29	void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
	30
	31	int checkboard (void)
	32	{
6073f61e	33	#if defined(CONFIG_IDE_PCMCIA) && 0
265817c7	34	u16 status;
6073f61e	35	#endif
265817c7 WD	36	/* volatile u32 pcmcia_bcsr = (u32)(DB1000_BCSR_ADDR+0x10); */
	37	volatile u32 sys_counter = (volatile u32)SYS_COUNTER_CNTRL;
	38	u32 proc_id;
	39
	40	sys_counter = 0x100; / Enable 32 kHz oscillator for RTC/TOY */
	41
e2ad8426	42	proc_id = read_c0_prid();
265817c7 WD	43
	44	switch (proc_id >> 24) {
	45	case 0:
	46	puts ("Board: Pb1000\n");
	47	printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
	48	(proc_id >> 8) & 0xFF, proc_id & 0xFF);
	49	break;
	50	case 1:
	51	puts ("Board: Pb1500\n");
	52	printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
	53	(proc_id >> 8) & 0xFF, proc_id & 0xFF);
	54	break;
	55	case 2:
	56	puts ("Board: Pb1100\n");
	57	printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
	58	(proc_id >> 8) & 0xFF, proc_id & 0xFF);
	59	break;
	60	default:
	61	printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
	62	}
5c15010e JCPV	63
	64	set_io_port_base(0);
	65
265817c7 WD	66	#if defined(CONFIG_IDE_PCMCIA) && 0
	67	/* Enable 3.3 V on slot 0 ( VCC )
	68	No 5V */
	69	status = 4;
	70	*pcmcia_bcsr = status;
	71
	72	status \|= BCSR_PCMCIA_PC0DRVEN;
	73	*pcmcia_bcsr = status;
	74	au_sync();
	75
	76	udelay(300*1000);
	77
	78	status \|= BCSR_PCMCIA_PC0RST;
	79	*pcmcia_bcsr = status;
	80	au_sync();
	81
	82	udelay(100*1000);
	83
	84	/* PCMCIA is on a 36 bit physical address.
	85	We need to map it into a 32 bit addresses */
	86
	87	#if 0
	88	/* We dont need theese unless we run whole pcmcia package */
	89	write_one_tlb(20, /* index */
	90	0x01ffe000, /* Pagemask, 16 MB pages */
6d0f6bcf	91	CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
265817c7 WD	92	0x3C000017, /* Lo0 */
	93	0x3C200017); /* Lo1 */
	94
	95	write_one_tlb(21, /* index */
	96	0x01ffe000, /* Pagemask, 16 MB pages */
6d0f6bcf	97	CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
265817c7 WD	98	0x3D000017, /* Lo0 */
	99	0x3D200017); /* Lo1 */
	100	#endif /* 0 */
	101	write_one_tlb(22, /* index */
	102	0x01ffe000, /* Pagemask, 16 MB pages */
6d0f6bcf	103	CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
265817c7 WD	104	0x3E000017, /* Lo0 */
	105	0x3E200017); /* Lo1 */
	106	#endif /* CONFIG_IDE_PCMCIA */
	107
	108	return 0;
	109	}