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a3921eef AG |
1 | /* |
2 | * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de> | |
3 | * | |
4 | * (C) Copyright 2009-2010 | |
5 | * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <asm/bitops.h> | |
29 | #include <command.h> | |
30 | #include <asm/io.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/mpc512x.h> | |
33 | #include <fdt_support.h> | |
34 | #include <flash.h> | |
35 | #ifdef CONFIG_MISC_INIT_R | |
36 | #include <i2c.h> | |
37 | #endif | |
38 | #include <serial.h> | |
39 | #include <jffs2/load_kernel.h> | |
40 | #include <mtd_node.h> | |
41 | ||
42 | DECLARE_GLOBAL_DATA_PTR; | |
43 | ||
44 | extern flash_info_t flash_info[]; | |
45 | ulong flash_get_size (phys_addr_t base, int banknum); | |
46 | ||
47 | /* Clocks in use */ | |
48 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ | |
49 | CLOCK_SCCR1_LPC_EN | \ | |
50 | CLOCK_SCCR1_NFC_EN | \ | |
51 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ | |
52 | CLOCK_SCCR1_PSCFIFO_EN | \ | |
53 | CLOCK_SCCR1_DDR_EN | \ | |
54 | CLOCK_SCCR1_FEC_EN | \ | |
55 | CLOCK_SCCR1_TPR_EN) | |
56 | ||
57 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ | |
58 | CLOCK_SCCR2_SPDIF_EN | \ | |
59 | CLOCK_SCCR2_DIU_EN | \ | |
60 | CLOCK_SCCR2_I2C_EN) | |
61 | ||
62 | int board_early_init_f(void) | |
63 | { | |
64 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
65 | ||
66 | /* | |
67 | * Initialize Local Window for FLASH-Bank1 access (CS1) | |
68 | */ | |
69 | out_be32(&im->sysconf.lpcs1aw, | |
70 | CSAW_START(CONFIG_SYS_FLASH1_BASE) | | |
71 | CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE) | |
72 | ); | |
73 | out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); | |
74 | ||
75 | /* | |
76 | * Local Window for MRAM access (CS2) | |
77 | */ | |
78 | out_be32(&im->sysconf.lpcs2aw, | |
79 | CSAW_START(CONFIG_SYS_MRAM_BASE) | | |
80 | CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE) | |
81 | ); | |
82 | out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); | |
83 | ||
84 | sync_law(&im->sysconf.lpcs2aw); | |
85 | ||
86 | /* | |
87 | * Configure Flash Speed | |
88 | */ | |
89 | out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); | |
90 | out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); | |
91 | ||
92 | /* | |
93 | * Enable clocks | |
94 | */ | |
95 | out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); | |
96 | out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); | |
97 | #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) | |
98 | setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); | |
99 | #endif | |
100 | ||
101 | return 0; | |
102 | } | |
103 | ||
104 | sdram_conf_t mddrc_config[] = { | |
105 | { | |
106 | (512 << 20), /* 512 MB RAM configuration */ | |
107 | { | |
108 | CONFIG_SYS_MDDRC_SYS_CFG, | |
109 | CONFIG_SYS_MDDRC_TIME_CFG0, | |
110 | CONFIG_SYS_MDDRC_TIME_CFG1, | |
111 | CONFIG_SYS_MDDRC_TIME_CFG2 | |
112 | } | |
113 | }, | |
114 | { | |
115 | (128 << 20), /* 128 MB RAM configuration */ | |
116 | { | |
117 | CONFIG_SYS_MDDRC_SYS_CFG_ALT1, | |
118 | CONFIG_SYS_MDDRC_TIME_CFG0_ALT1, | |
119 | CONFIG_SYS_MDDRC_TIME_CFG1_ALT1, | |
120 | CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 | |
121 | } | |
122 | }, | |
123 | }; | |
124 | ||
125 | phys_size_t initdram (int board_type) | |
126 | { | |
127 | int i; | |
128 | u32 msize = 0; | |
129 | u32 pdm360ng_init_seq[] = { | |
130 | CONFIG_SYS_DDRCMD_NOP, | |
131 | CONFIG_SYS_DDRCMD_NOP, | |
132 | CONFIG_SYS_DDRCMD_NOP, | |
133 | CONFIG_SYS_DDRCMD_NOP, | |
134 | CONFIG_SYS_DDRCMD_NOP, | |
135 | CONFIG_SYS_DDRCMD_NOP, | |
136 | CONFIG_SYS_DDRCMD_NOP, | |
137 | CONFIG_SYS_DDRCMD_NOP, | |
138 | CONFIG_SYS_DDRCMD_NOP, | |
139 | CONFIG_SYS_DDRCMD_NOP, | |
140 | CONFIG_SYS_DDRCMD_PCHG_ALL, | |
141 | CONFIG_SYS_DDRCMD_NOP, | |
142 | CONFIG_SYS_DDRCMD_RFSH, | |
143 | CONFIG_SYS_DDRCMD_NOP, | |
144 | CONFIG_SYS_DDRCMD_RFSH, | |
145 | CONFIG_SYS_DDRCMD_NOP, | |
146 | CONFIG_SYS_MICRON_INIT_DEV_OP, | |
147 | CONFIG_SYS_DDRCMD_NOP, | |
148 | CONFIG_SYS_DDRCMD_EM2, | |
149 | CONFIG_SYS_DDRCMD_NOP, | |
150 | CONFIG_SYS_DDRCMD_PCHG_ALL, | |
151 | CONFIG_SYS_DDRCMD_EM2, | |
152 | CONFIG_SYS_DDRCMD_EM3, | |
153 | CONFIG_SYS_DDRCMD_EN_DLL, | |
154 | CONFIG_SYS_DDRCMD_RES_DLL, | |
155 | CONFIG_SYS_DDRCMD_PCHG_ALL, | |
156 | CONFIG_SYS_DDRCMD_RFSH, | |
157 | CONFIG_SYS_DDRCMD_RFSH, | |
158 | CONFIG_SYS_MICRON_INIT_DEV_OP, | |
159 | CONFIG_SYS_DDRCMD_OCD_DEFAULT, | |
160 | CONFIG_SYS_DDRCMD_OCD_EXIT, | |
161 | CONFIG_SYS_DDRCMD_PCHG_ALL, | |
162 | CONFIG_SYS_DDRCMD_NOP | |
163 | }; | |
164 | ||
165 | for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) { | |
166 | msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq, | |
167 | ARRAY_SIZE(pdm360ng_init_seq)); | |
168 | if (msize == mddrc_config[i].size) | |
169 | break; | |
170 | } | |
171 | ||
172 | return msize; | |
173 | } | |
174 | ||
175 | #if defined(CONFIG_SERIAL_MULTI) | |
176 | static int set_lcd_brightness(char *); | |
177 | #endif | |
178 | ||
179 | int misc_init_r(void) | |
180 | { | |
181 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
182 | ||
183 | /* | |
184 | * Re-configure flash setup using auto-detected info | |
185 | */ | |
186 | if (flash_info[1].size > 0) { | |
187 | out_be32(&im->sysconf.lpcs1aw, | |
188 | CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) | | |
189 | CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size, | |
190 | flash_info[1].size)); | |
191 | sync_law(&im->sysconf.lpcs1aw); | |
192 | /* | |
193 | * Re-check to get correct base address | |
194 | */ | |
195 | flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1); | |
196 | } else { | |
197 | /* Disable Bank 1 */ | |
198 | out_be32(&im->sysconf.lpcs1aw, 0x01000100); | |
199 | sync_law(&im->sysconf.lpcs1aw); | |
200 | } | |
201 | ||
202 | out_be32(&im->sysconf.lpcs0aw, | |
203 | CSAW_START(gd->bd->bi_flashstart) | | |
204 | CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size)); | |
205 | sync_law(&im->sysconf.lpcs0aw); | |
206 | ||
207 | /* | |
208 | * Re-check to get correct base address | |
209 | */ | |
210 | flash_get_size (gd->bd->bi_flashstart, 0); | |
211 | ||
212 | /* | |
213 | * Re-do flash protection upon new addresses | |
214 | */ | |
215 | flash_protect (FLAG_PROTECT_CLEAR, | |
216 | gd->bd->bi_flashstart, 0xffffffff, | |
217 | &flash_info[0]); | |
218 | ||
219 | /* Monitor protection ON by default */ | |
220 | flash_protect (FLAG_PROTECT_SET, | |
221 | CONFIG_SYS_MONITOR_BASE, | |
222 | CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, | |
223 | &flash_info[0]); | |
224 | ||
225 | /* Environment protection ON by default */ | |
226 | flash_protect (FLAG_PROTECT_SET, | |
227 | CONFIG_ENV_ADDR, | |
228 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, | |
229 | &flash_info[0]); | |
230 | ||
231 | #ifdef CONFIG_ENV_ADDR_REDUND | |
232 | /* Redundant environment protection ON by default */ | |
233 | flash_protect (FLAG_PROTECT_SET, | |
234 | CONFIG_ENV_ADDR_REDUND, | |
235 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, | |
236 | &flash_info[0]); | |
237 | #endif | |
238 | ||
239 | #ifdef CONFIG_FSL_DIU_FB | |
240 | # if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) | |
241 | mpc5121_diu_init(); | |
242 | #endif | |
243 | #if defined(CONFIG_SERIAL_MULTI) | |
244 | set_lcd_brightness(0); | |
245 | #endif | |
246 | /* Switch LCD-Backlight and LVDS-Interface on */ | |
247 | setbits_be32(&im->gpio.gpdir, 0x01040000); | |
248 | clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000); | |
249 | #endif | |
250 | ||
251 | #if defined(CONFIG_HARD_I2C) | |
252 | if (!getenv("ethaddr")) { | |
253 | uchar buf[6]; | |
254 | uchar ifm_oui[3] = { 0, 2, 1, }; | |
255 | int ret; | |
256 | ||
257 | /* I2C-0 for on-board eeprom */ | |
258 | i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM); | |
259 | ||
260 | /* Read ethaddr from EEPROM */ | |
261 | ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, | |
262 | CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6); | |
263 | if (ret != 0) { | |
264 | printf("Error: Unable to read MAC from I2C" | |
265 | " EEPROM at address %02X:%02X\n", | |
266 | CONFIG_SYS_I2C_EEPROM_ADDR, | |
267 | CONFIG_SYS_I2C_EEPROM_MAC_OFFSET); | |
268 | return 1; | |
269 | } | |
270 | ||
271 | /* Owned by IFM ? */ | |
272 | if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) { | |
273 | printf("Illegal MAC address in EEPROM: %pM\n", buf); | |
274 | return 1; | |
275 | } | |
276 | ||
277 | eth_setenv_enetaddr("ethaddr", buf); | |
278 | } | |
279 | #endif /* defined(CONFIG_HARD_I2C) */ | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
284 | static iopin_t ioregs_init[] = { | |
285 | /* FUNC1=LPC_CS4 */ | |
286 | { | |
287 | offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0, | |
288 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) | | |
289 | IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
290 | }, | |
291 | /* FUNC3=GPIO10 */ | |
292 | { | |
293 | offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0, | |
294 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
295 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
296 | }, | |
297 | /* FUNC1=CAN3_TX */ | |
298 | { | |
299 | offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0, | |
300 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
301 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
302 | }, | |
303 | /* FUNC3=GPIO14 */ | |
304 | { | |
305 | offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0, | |
306 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
307 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
308 | }, | |
309 | /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */ | |
310 | /* DIU_LD22-DIU_LD23 */ | |
311 | { | |
312 | offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0, | |
313 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
314 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) | |
315 | }, | |
316 | /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */ | |
317 | /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */ | |
318 | { | |
319 | offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0, | |
320 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
321 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) | |
322 | }, | |
323 | /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */ | |
324 | /* VIU_DATA0-VIU_DATA2 */ | |
325 | { | |
326 | offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0, | |
327 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
328 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) | |
329 | }, | |
330 | /* FUNC2=FEC_TXD_0 */ | |
331 | { | |
332 | offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0, | |
333 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
334 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) | |
335 | }, | |
336 | /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */ | |
337 | /* VIU_DATA3, VIU_DATA4 */ | |
338 | { | |
339 | offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0, | |
340 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
341 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) | |
342 | }, | |
343 | /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */ | |
344 | /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */ | |
345 | /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */ | |
346 | { | |
347 | offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0, | |
348 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
349 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) | |
350 | }, | |
351 | /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */ | |
352 | /* DIU_LD00-DIU_LD21 */ | |
353 | { | |
354 | offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0, | |
355 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
356 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) | |
357 | }, | |
358 | /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */ | |
359 | /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */ | |
360 | { | |
361 | offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, | |
362 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
363 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
364 | }, | |
365 | /* FUNC2=CAN3_RX */ | |
366 | { | |
367 | offsetof(struct ioctrl512x, io_control_irq1), 1, 0, | |
368 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
369 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
370 | }, | |
371 | /* Sets lowest slew on 2 CAN_TX Pins*/ | |
372 | { | |
373 | offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0, | |
374 | IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
375 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
376 | }, | |
377 | /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */ | |
378 | /* CAN4_TX, CAN4_RX */ | |
379 | { | |
380 | offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0, | |
381 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
382 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
383 | }, | |
384 | /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */ | |
385 | /* GPIO8, GPIO9 */ | |
386 | { | |
387 | offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0, | |
388 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
389 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
390 | }, | |
391 | /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */ | |
392 | /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */ | |
393 | { | |
394 | offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0, | |
395 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
396 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
397 | }, | |
398 | /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */ | |
399 | /* FEC_RXD_3, FEC_RXD_2 */ | |
400 | { | |
401 | offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0, | |
402 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
403 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
404 | }, | |
405 | /* FUNC3=GPIO17 */ | |
406 | { | |
407 | offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0, | |
408 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
409 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
410 | }, | |
411 | /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */ | |
412 | /* GPIO2, GPIO20, GPIO21 */ | |
413 | { | |
414 | offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0, | |
415 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
416 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
417 | }, | |
418 | /* FUNC2=VIU_PIX_CLK */ | |
419 | { | |
420 | offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0, | |
421 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
422 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
423 | }, | |
424 | /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */ | |
425 | /* GPIO24, GPIO25 */ | |
426 | { | |
427 | offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0, | |
428 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
429 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
430 | }, | |
431 | /* FUNC1=NFC_CE2 */ | |
432 | { | |
433 | offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0, | |
434 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) | | |
435 | IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
436 | }, | |
437 | /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */ | |
438 | /* VIU_DATA5-VIU_DATA9 */ | |
439 | { | |
440 | offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0, | |
441 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
442 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
443 | }, | |
444 | /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */ | |
445 | /* LPC_TSIZ1-LPC_TSIZ2 */ | |
446 | { | |
447 | offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0, | |
448 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
449 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
450 | }, | |
451 | /* FUNC1=LPC_TS */ | |
452 | { | |
453 | offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0, | |
454 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
455 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
456 | }, | |
457 | /* FUNC3=GPIO16 */ | |
458 | { | |
459 | offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0, | |
460 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
461 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
462 | }, | |
463 | /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */ | |
464 | /* GPIO18-GPIO19, GPT7/GPIO7 */ | |
465 | { | |
466 | offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0, | |
467 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
468 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
469 | }, | |
470 | /* FUNC3=GPIO0/GPT0 */ | |
471 | { | |
472 | offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0, | |
473 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
474 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
475 | }, | |
476 | /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */ | |
477 | /* GPIO11, GPIO2, GPIO12, GPIO13 */ | |
478 | { | |
479 | offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0, | |
480 | IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
481 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) | |
482 | }, | |
483 | /* FUNC2=DIU_DE */ | |
484 | { | |
485 | offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0, | |
486 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | | |
487 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) | |
488 | } | |
489 | }; | |
490 | ||
491 | int checkboard (void) | |
492 | { | |
493 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
494 | ||
495 | puts("Board: PDM360NG\n"); | |
496 | ||
497 | /* initialize function mux & slew rate IO inter alia on IO Pins */ | |
498 | ||
499 | iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); | |
500 | ||
501 | /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */ | |
502 | setbits_be32(&im->io_ctrl.io_control_gp, | |
503 | (1 << 0) | /* GP_MUX7->GPIO7 */ | |
504 | (1 << 5)); /* GP_MUX2->GPIO2 */ | |
505 | ||
506 | /* configure GPIO24 (VIU_CE), output/high */ | |
507 | setbits_be32(&im->gpio.gpdir, 0x80); | |
508 | setbits_be32(&im->gpio.gpdat, 0x80); | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
513 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
514 | #ifdef CONFIG_FDT_FIXUP_PARTITIONS | |
515 | struct node_info nodes[] = { | |
516 | { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, }, | |
517 | { "cfi-flash", MTD_DEV_TYPE_NOR, }, | |
518 | }; | |
519 | #endif | |
520 | ||
521 | void ft_board_setup(void *blob, bd_t *bd) | |
522 | { | |
523 | u32 val[8]; | |
524 | int rc, i = 0; | |
525 | ||
526 | ft_cpu_setup(blob, bd); | |
527 | fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); | |
528 | #ifdef CONFIG_FDT_FIXUP_PARTITIONS | |
529 | fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); | |
530 | #endif | |
531 | ||
532 | /* Fixup NOR FLASH mapping */ | |
533 | val[i++] = 0; /* chip select number */ | |
534 | val[i++] = 0; /* always 0 */ | |
535 | val[i++] = gd->bd->bi_flashstart; | |
536 | val[i++] = gd->bd->bi_flashsize; | |
537 | ||
538 | /* Fixup MRAM mapping */ | |
539 | val[i++] = 2; /* chip select number */ | |
540 | val[i++] = 0; /* always 0 */ | |
541 | val[i++] = CONFIG_SYS_MRAM_BASE; | |
542 | val[i++] = CONFIG_SYS_MRAM_SIZE; | |
543 | ||
544 | rc = fdt_find_and_setprop(blob, "/localbus", "ranges", | |
545 | val, i * sizeof(u32), 1); | |
546 | if (rc) | |
547 | printf("Unable to update localbus ranges, err=%s\n", | |
548 | fdt_strerror(rc)); | |
549 | ||
550 | /* Fixup reg property in NOR Flash node */ | |
551 | i = 0; | |
552 | val[i++] = 0; /* always 0 */ | |
553 | val[i++] = 0; /* start at offset 0 */ | |
554 | val[i++] = flash_info[0].size; /* size of Bank 0 */ | |
555 | ||
556 | /* Second Bank available? */ | |
557 | if (flash_info[1].size > 0) { | |
558 | val[i++] = 0; /* always 0 */ | |
559 | val[i++] = flash_info[0].size; /* offset of Bank 1 */ | |
560 | val[i++] = flash_info[1].size; /* size of Bank 1 */ | |
561 | } | |
562 | ||
563 | rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg", | |
564 | val, i * sizeof(u32), 1); | |
565 | if (rc) | |
566 | printf("Unable to update flash reg property, err=%s\n", | |
567 | fdt_strerror(rc)); | |
568 | } | |
569 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ | |
570 | ||
571 | #if defined(CONFIG_SERIAL_MULTI) | |
572 | /* | |
573 | * If argument is NULL, set the LCD brightness to the | |
574 | * value from "brightness" environment variable. Set | |
575 | * the LCD brightness to the value specified by the | |
576 | * argument otherwise. Default brightness is zero. | |
577 | */ | |
578 | #define MAX_BRIGHTNESS 99 | |
579 | static int set_lcd_brightness(char *brightness) | |
580 | { | |
581 | struct stdio_dev *cop_port; | |
582 | char *env; | |
583 | char cmd_buf[20]; | |
584 | int val = 0; | |
585 | int cs = 0; | |
586 | int len, i; | |
587 | ||
588 | if (brightness) { | |
589 | val = simple_strtol(brightness, NULL, 10); | |
590 | } else { | |
591 | env = getenv("brightness"); | |
592 | if (env) | |
593 | val = simple_strtol(env, NULL, 10); | |
594 | } | |
595 | ||
596 | if (val < 0) | |
597 | val = 0; | |
598 | ||
599 | if (val > MAX_BRIGHTNESS) | |
600 | val = MAX_BRIGHTNESS; | |
601 | ||
602 | sprintf(cmd_buf, "$SB;%04d;", val); | |
603 | ||
604 | len = strlen(cmd_buf); | |
605 | for (i = 1; i <= len; i++) | |
606 | cs += cmd_buf[i]; | |
607 | ||
608 | cs = (~cs + 1) & 0xff; | |
609 | sprintf(cmd_buf + len, "%02X\n", cs); | |
610 | ||
611 | /* IO Coprocessor communication */ | |
612 | cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE); | |
613 | if (!cop_port) { | |
614 | printf("Error: Can't open IO Coprocessor port.\n"); | |
615 | return -1; | |
616 | } | |
617 | ||
618 | debug("%s: cmd: %s", __func__, cmd_buf); | |
619 | write_port(cop_port, cmd_buf); | |
620 | /* | |
621 | * Wait for transmission and maybe response data | |
622 | * before closing the port. | |
623 | */ | |
624 | udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY); | |
625 | memset(cmd_buf, 0, sizeof(cmd_buf)); | |
626 | len = read_port(cop_port, cmd_buf, sizeof(cmd_buf)); | |
627 | if (len) | |
628 | printf("Error: %s\n", cmd_buf); | |
629 | ||
630 | close_port(4); | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag, | |
54841ab5 | 636 | int argc, char * const argv[]) |
a3921eef AG |
637 | { |
638 | if (argc < 2) { | |
639 | cmd_usage(cmdtp); | |
640 | return 1; | |
641 | } | |
642 | ||
643 | return set_lcd_brightness(argv[1]); | |
644 | } | |
645 | ||
646 | U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness, | |
647 | "set LCD brightness", | |
648 | "<brightness> - set LCD backlight level to <brightness>.\n" | |
649 | ); | |
650 | #endif /* CONFIG_SERIAL_MULTI */ |