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c9969947 JS |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
8 | * (C) Copyright 2006 | |
9 | * Eric Schumann, Phytec Messtechnik GmbH | |
10 | * | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
c9969947 JS |
12 | */ |
13 | ||
14 | #include <common.h> | |
15 | #include <mpc5xxx.h> | |
16 | #include <pci.h> | |
61f2b38a | 17 | #include <asm/io.h> |
c9969947 JS |
18 | |
19 | #include "mt46v32m16-75.h" | |
20 | ||
088454cd SG |
21 | DECLARE_GLOBAL_DATA_PTR; |
22 | ||
c9969947 JS |
23 | #ifndef CONFIG_SYS_RAMBOOT |
24 | static void sdram_start(int hi_addr) | |
25 | { | |
26 | volatile struct mpc5xxx_cdm *cdm = | |
27 | (struct mpc5xxx_cdm *)MPC5XXX_CDM; | |
28 | volatile struct mpc5xxx_sdram *sdram = | |
29 | (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; | |
30 | ||
31 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
32 | ||
33 | /* unlock mode register */ | |
34 | out_be32 (&sdram->ctrl, | |
35 | (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); | |
36 | ||
37 | /* precharge all banks */ | |
38 | out_be32 (&sdram->ctrl, | |
39 | (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); | |
40 | ||
41 | #ifdef SDRAM_DDR | |
42 | /* set mode register: extended mode */ | |
43 | out_be32 (&sdram->mode, (SDRAM_EMODE)); | |
44 | ||
45 | /* set mode register: reset DLL */ | |
46 | out_be32 (&sdram->mode, | |
47 | (SDRAM_MODE | 0x04000000)); | |
48 | #endif | |
49 | ||
50 | /* precharge all banks */ | |
51 | out_be32 (&sdram->ctrl, | |
52 | (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); | |
53 | ||
54 | /* auto refresh */ | |
55 | out_be32 (&sdram->ctrl, | |
56 | (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); | |
57 | ||
58 | /* set mode register */ | |
59 | out_be32 (&sdram->mode, (SDRAM_MODE)); | |
60 | ||
61 | /* normal operation */ | |
62 | out_be32 (&sdram->ctrl, | |
63 | (SDRAM_CONTROL | hi_addr_bit)); | |
64 | ||
65 | /* set CDM clock enable register, set MPC5200B SDRAM bus */ | |
66 | /* to reduced driver strength */ | |
67 | out_be32 (&cdm->clock_enable, (0x00CFFFFF)); | |
68 | } | |
69 | #endif | |
70 | ||
71 | /* | |
72 | * ATTENTION: Although partially referenced initdram does NOT make | |
73 | * real use of CONFIG_SYS_SDRAM_BASE. The code does not | |
74 | * work if CONFIG_SYS_SDRAM_BASE | |
75 | * is something else than 0x00000000. | |
76 | */ | |
77 | ||
088454cd | 78 | int initdram(void) |
c9969947 JS |
79 | { |
80 | volatile struct mpc5xxx_mmap_ctl *mm = | |
81 | (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; | |
82 | volatile struct mpc5xxx_cdm *cdm = | |
83 | (struct mpc5xxx_cdm *)MPC5XXX_CDM; | |
84 | volatile struct mpc5xxx_sdram *sdram = | |
85 | (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; | |
86 | ulong dramsize = 0; | |
87 | ulong dramsize2 = 0; | |
88 | #ifndef CONFIG_SYS_RAMBOOT | |
89 | ulong test1, test2; | |
90 | ||
91 | /* setup SDRAM chip selects */ | |
92 | /* 256MB at 0x0 */ | |
93 | out_be32 (&mm->sdram0, 0x0000001b); | |
94 | /* disabled */ | |
95 | out_be32 (&mm->sdram1, 0x10000000); | |
96 | ||
97 | /* setup config registers */ | |
98 | out_be32 (&sdram->config1, SDRAM_CONFIG1); | |
99 | out_be32 (&sdram->config2, SDRAM_CONFIG2); | |
100 | ||
101 | #if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY) | |
102 | /* set tap delay */ | |
103 | out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); | |
104 | #endif | |
105 | ||
106 | /* find RAM size using SDRAM CS0 only */ | |
107 | sdram_start(0); | |
108 | test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); | |
109 | sdram_start(1); | |
110 | test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); | |
111 | if (test1 > test2) { | |
112 | sdram_start(0); | |
113 | dramsize = test1; | |
114 | } else | |
115 | dramsize = test2; | |
116 | ||
117 | /* memory smaller than 1MB is impossible */ | |
118 | if (dramsize < (1 << 20)) | |
119 | dramsize = 0; | |
120 | ||
121 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
122 | if (dramsize > 0) { | |
123 | out_be32 (&mm->sdram0, | |
124 | (0x13 + __builtin_ffs(dramsize >> 20) - 1)); | |
125 | } else { | |
126 | /* disabled */ | |
127 | out_be32 (&mm->sdram0, 0); | |
128 | } | |
129 | ||
130 | #else /* CONFIG_SYS_RAMBOOT */ | |
131 | ||
132 | /* retrieve size of memory connected to SDRAM CS0 */ | |
133 | dramsize = in_be32(&mm->sdram0) & 0xFF; | |
134 | if (dramsize >= 0x13) | |
135 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
136 | else | |
137 | dramsize = 0; | |
138 | ||
139 | /* retrieve size of memory connected to SDRAM CS1 */ | |
140 | dramsize2 = in_be32(&mm->sdram1) & 0xFF; | |
141 | if (dramsize2 >= 0x13) | |
142 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | |
143 | else | |
144 | dramsize2 = 0; | |
145 | ||
146 | #endif /* CONFIG_SYS_RAMBOOT */ | |
147 | ||
088454cd SG |
148 | gd->ram_size = dramsize + dramsize2; |
149 | ||
150 | return 0; | |
c9969947 JS |
151 | } |
152 | ||
153 | int checkboard(void) | |
154 | { | |
155 | puts("Board: phyCORE-MPC5200B-tiny\n"); | |
156 | return 0; | |
157 | } | |
158 | ||
159 | #ifdef CONFIG_PCI | |
160 | static struct pci_controller hose; | |
161 | ||
162 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
163 | ||
164 | void pci_init_board(void) | |
165 | { | |
166 | pci_mpc5xxx_init(&hose); | |
167 | } | |
168 | #endif | |
169 | ||
7ffe3cd6 | 170 | #ifdef CONFIG_OF_BOARD_SETUP |
e895a4b0 | 171 | int ft_board_setup(void *blob, bd_t *bd) |
c9969947 JS |
172 | { |
173 | ft_cpu_setup(blob, bd); | |
e895a4b0 SG |
174 | |
175 | return 0; | |
c9969947 | 176 | } |
7ffe3cd6 | 177 | #endif /* CONFIG_OF_BOARD_SETUP */ |
c9969947 JS |
178 | |
179 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) | |
180 | ||
181 | #define GPIO_PSC2_4 0x02000000UL | |
182 | ||
183 | void init_ide_reset(void) | |
184 | { | |
185 | volatile struct mpc5xxx_wu_gpio *wu_gpio = | |
186 | (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; | |
187 | debug("init_ide_reset\n"); | |
188 | ||
189 | /* Configure PSC2_4 as GPIO output for ATA reset */ | |
190 | setbits_be32(&wu_gpio->enable, GPIO_PSC2_4); | |
191 | setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4); | |
192 | /* Deassert reset */ | |
193 | setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); | |
194 | } | |
195 | ||
196 | void ide_set_reset(int idereset) | |
197 | { | |
198 | volatile struct mpc5xxx_wu_gpio *wu_gpio = | |
199 | (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; | |
200 | debug("ide_reset(%d)\n", idereset); | |
201 | ||
202 | if (idereset) { | |
203 | clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); | |
204 | /* Make a delay. MPC5200 spec says 25 usec min */ | |
205 | udelay(500000); | |
206 | } else | |
207 | setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); | |
208 | } | |
209 | #endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ |