[people/ms/u-boot.git] / board / phytec / pcm051 / board.c

/*
 * board.c
 *
 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
 *
 * Copyright (C) 2013 Lemonage Software GmbH
 * Author Lars Poeschel <poeschel@lemonage.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
#ifdef CONFIG_SPL_BUILD
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
#endif

/* MII mode defines */
#define MII_MODE_ENABLE		0x0
#define RGMII_MODE_ENABLE	0xA
#define RMII_RGMII2_MODE_ENABLE	0x49

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

/* UART defines */
#ifdef CONFIG_SPL_BUILD
#define UART_RESET		(0x1 << 1)
#define UART_CLK_RUNNING_MASK	0x1
#define UART_SMART_IDLE_EN	(0x1 << 0x3)

/* DDR RAM defines */
#define DDR_CLK_MHZ		303 /* DDR_DPLL_MULT value */

static void rtc32k_enable(void)
{
	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;

	/*
	 * Unlock the RTC's registers.  For more details please see the
	 * RTC_SS section of the TRM.  In order to unlock we need to
	 * write these specific values (keys) in this order.
	 */
	writel(0x83e70b13, &rtc->kick0r);
	writel(0x95a4f1e0, &rtc->kick1r);

	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
	writel((1 << 3) | (1 << 6), &rtc->osc);
}

static const struct ddr_data ddr3_data = {
	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
	.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
	.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct cmd_control ddr3_cmd_ctrl_data = {
	.cmd0csratio = MT41J256M8HX15E_RATIO,
	.cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,

	.cmd1csratio = MT41J256M8HX15E_RATIO,
	.cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,

	.cmd2csratio = MT41J256M8HX15E_RATIO,
	.cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
};

static struct emif_regs ddr3_emif_reg_data = {
	.sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
	.ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
	.sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
	.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
	.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
	.zq_config = MT41J256M8HX15E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
};
#endif

/*
 * early system init of muxing and clocks.
 */
void s_init(void)
{
	/*
	 * WDT1 is already running when the bootloader gets control
	 * Disable it to avoid "random" resets
	 */
	writel(0xAAAA, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;
	writel(0x5555, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;

#ifdef CONFIG_SPL_BUILD
	/* Setup the PLLs and the clocks for the peripherals */
	pll_init();

	/* Enable RTC32K clock */
	rtc32k_enable();

	/* UART softreset */
	u32 regval;

	enable_uart0_pin_mux();

	regval = readl(&uart_base->uartsyscfg);
	regval |= UART_RESET;
	writel(regval, &uart_base->uartsyscfg);
	while ((readl(&uart_base->uartsyssts) &	UART_CLK_RUNNING_MASK)
		!= UART_CLK_RUNNING_MASK)
		;

	/* Disable smart idle */
	regval = readl(&uart_base->uartsyscfg);
	regval |= UART_SMART_IDLE_EN;
	writel(regval, &uart_base->uartsyscfg);

	gd = &gdata;

	preloader_console_init();

	/* Initalize the board header */
	enable_i2c0_pin_mux();
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	enable_board_pin_mux();

	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
#endif
}

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;

	return 0;
}

#ifdef CONFIG_DRIVER_TI_CPSW
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_id		= 0,
		.phy_if		= PHY_INTERFACE_MODE_RGMII,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_id		= 1,
		.phy_if		= PHY_INTERFACE_MODE_RGMII,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};
#endif

#if defined(CONFIG_DRIVER_TI_CPSW) || \
	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
	int rv, n = 0;
#ifdef CONFIG_DRIVER_TI_CPSW
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;

	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
		printf("<ethaddr> not set. Reading from E-fuse\n");
		/* try reading mac address from efuse */
		mac_lo = readl(&cdev->macid0l);
		mac_hi = readl(&cdev->macid0h);
		mac_addr[0] = mac_hi & 0xFF;
		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
		mac_addr[4] = mac_lo & 0xFF;
		mac_addr[5] = (mac_lo & 0xFF00) >> 8;

		if (is_valid_ether_addr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
		else
			goto try_usbether;
	}

	writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;
try_usbether:
#endif

#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
	rv = usb_eth_initialize(bis);
	if (rv < 0)
		printf("Error %d registering USB_ETHER\n", rv);
	else
		n += rv;
#endif
	return n;
}
#endif
Commit	Line	Data
1c1b7c37 LP	1	/*
	2	* board.c
	3	*
	4	* Board functions for Phytec phyCORE-AM335x (pcm051) based boards
	5	*
	6	* Copyright (C) 2013 Lemonage Software GmbH
	7	* Author Lars Poeschel <poeschel@lemonage.de>
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*/
	19
	20	#include <common.h>
	21	#include <errno.h>
	22	#include <spl.h>
	23	#include <asm/arch/cpu.h>
	24	#include <asm/arch/hardware.h>
	25	#include <asm/arch/omap.h>
	26	#include <asm/arch/ddr_defs.h>
	27	#include <asm/arch/clock.h>
	28	#include <asm/arch/gpio.h>
	29	#include <asm/arch/mmc_host_def.h>
	30	#include <asm/arch/sys_proto.h>
	31	#include <asm/io.h>
	32	#include <asm/emif.h>
	33	#include <asm/gpio.h>
	34	#include <i2c.h>
	35	#include <miiphy.h>
	36	#include <cpsw.h>
	37	#include "board.h"
	38
	39	DECLARE_GLOBAL_DATA_PTR;
	40
	41	static struct wd_timer wdtimer = (struct wd_timer )WDT_BASE;
	42	#ifdef CONFIG_SPL_BUILD
	43	static struct uart_sys uart_base = (struct uart_sys )DEFAULT_UART_BASE;
	44	#endif
	45
	46	/* MII mode defines */
	47	#define MII_MODE_ENABLE 0x0
	48	#define RGMII_MODE_ENABLE 0xA
	49	#define RMII_RGMII2_MODE_ENABLE 0x49
	50
	51	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	52
	53	/* UART defines */
	54	#ifdef CONFIG_SPL_BUILD
	55	#define UART_RESET (0x1 << 1)
	56	#define UART_CLK_RUNNING_MASK 0x1
	57	#define UART_SMART_IDLE_EN (0x1 << 0x3)
	58
	59	/* DDR RAM defines */
	60	#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
	61
	62	static void rtc32k_enable(void)
	63	{
81df2bab	64	struct rtc_regs rtc = (struct rtc_regs )RTC_BASE;
1c1b7c37 LP	65
	66	/*
	67	* Unlock the RTC's registers. For more details please see the
	68	* RTC_SS section of the TRM. In order to unlock we need to
	69	* write these specific values (keys) in this order.
	70	*/
	71	writel(0x83e70b13, &rtc->kick0r);
	72	writel(0x95a4f1e0, &rtc->kick1r);
	73
	74	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
	75	writel((1 << 3) \| (1 << 6), &rtc->osc);
	76	}
	77
	78	static const struct ddr_data ddr3_data = {
	79	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
	80	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
	81	.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
	82	.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
	83	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	84	};
	85
	86	static const struct cmd_control ddr3_cmd_ctrl_data = {
	87	.cmd0csratio = MT41J256M8HX15E_RATIO,
	88	.cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
	89	.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
	90
	91	.cmd1csratio = MT41J256M8HX15E_RATIO,
	92	.cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
	93	.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
	94
	95	.cmd2csratio = MT41J256M8HX15E_RATIO,
	96	.cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
	97	.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
	98	};
	99
	100	static struct emif_regs ddr3_emif_reg_data = {
	101	.sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
	102	.ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
	103	.sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
	104	.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
	105	.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
	106	.zq_config = MT41J256M8HX15E_ZQ_CFG,
	107	.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
	108	};
	109	#endif
	110
	111	/*
	112	* early system init of muxing and clocks.
	113	*/
	114	void s_init(void)
	115	{
	116	/*
	117	* WDT1 is already running when the bootloader gets control
	118	* Disable it to avoid "random" resets
	119	*/
	120	writel(0xAAAA, &wdtimer->wdtwspr);
	121	while (readl(&wdtimer->wdtwwps) != 0x0)
	122	;
	123	writel(0x5555, &wdtimer->wdtwspr);
	124	while (readl(&wdtimer->wdtwwps) != 0x0)
	125	;
	126
	127	#ifdef CONFIG_SPL_BUILD
	128	/* Setup the PLLs and the clocks for the peripherals */
129	pll_init();
130
131	/* Enable RTC32K clock */
132	rtc32k_enable();
133
134	/* UART softreset */
135	u32 regval;
136
137	enable_uart0_pin_mux();
138
139	regval = readl(&uart_base->uartsyscfg);
140	regval \|= UART_RESET;
141	writel(regval, &uart_base->uartsyscfg);
142	while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
143	!= UART_CLK_RUNNING_MASK)
144	;
145
146	/* Disable smart idle */
147	regval = readl(&uart_base->uartsyscfg);
148	regval \|= UART_SMART_IDLE_EN;
149	writel(regval, &uart_base->uartsyscfg);
150
151	gd = &gdata;
152
153	preloader_console_init();
154
155	/* Initalize the board header */
156	enable_i2c0_pin_mux();
157	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
158
159	enable_board_pin_mux();
160
161	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
3ba65f97	162	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
1c1b7c37 LP	163	#endif
	164	}
	165
	166	/*
	167	* Basic board specific setup. Pinmux has been handled already.
	168	*/
	169	int board_init(void)
	170	{
	171	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	172
	173	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
	174
	175	return 0;
	176	}
	177
	178	#ifdef CONFIG_DRIVER_TI_CPSW
	179	static void cpsw_control(int enabled)
	180	{
	181	/* VTP can be added here */
	182
	183	return;
	184	}
	185
	186	static struct cpsw_slave_data cpsw_slaves[] = {
	187	{
	188	.slave_reg_ofs = 0x208,
	189	.sliver_reg_ofs = 0xd80,
	190	.phy_id = 0,
	191	.phy_if = PHY_INTERFACE_MODE_RGMII,
	192	},
	193	{
	194	.slave_reg_ofs = 0x308,
	195	.sliver_reg_ofs = 0xdc0,
	196	.phy_id = 1,
	197	.phy_if = PHY_INTERFACE_MODE_RGMII,
	198	},
	199	};
	200
	201	static struct cpsw_platform_data cpsw_data = {
81df2bab MP	202	.mdio_base = CPSW_MDIO_BASE,
81df2bab MP	203	.cpsw_base = CPSW_BASE,
1c1b7c37 LP	204	.mdio_div = 0xff,
	205	.channels = 8,
	206	.cpdma_reg_ofs = 0x800,
	207	.slaves = 1,
	208	.slave_data = cpsw_slaves,
	209	.ale_reg_ofs = 0xd00,
	210	.ale_entries = 1024,
	211	.host_port_reg_ofs = 0x108,
	212	.hw_stats_reg_ofs = 0x900,
	213	.mac_control = (1 << 5),
	214	.control = cpsw_control,
	215	.host_port_num = 0,
	216	.version = CPSW_CTRL_VERSION_2,
	217	};
	218	#endif
	219
	220	#if defined(CONFIG_DRIVER_TI_CPSW) \|\| \
	221	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
	222	int board_eth_init(bd_t *bis)
	223	{
	224	int rv, n = 0;
	225	#ifdef CONFIG_DRIVER_TI_CPSW
	226	uint8_t mac_addr[6];
	227	uint32_t mac_hi, mac_lo;
	228
	229	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
	230	printf("<ethaddr> not set. Reading from E-fuse\n");
	231	/* try reading mac address from efuse */
	232	mac_lo = readl(&cdev->macid0l);
	233	mac_hi = readl(&cdev->macid0h);
	234	mac_addr[0] = mac_hi & 0xFF;
	235	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	236	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	237	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	238	mac_addr[4] = mac_lo & 0xFF;
	239	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
	240
	241	if (is_valid_ether_addr(mac_addr))
	242	eth_setenv_enetaddr("ethaddr", mac_addr);
	243	else
	244	goto try_usbether;
	245	}
	246
	247	writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
	248
	249	rv = cpsw_register(&cpsw_data);
	250	if (rv < 0)
	251	printf("Error %d registering CPSW switch\n", rv);
	252	else
	253	n += rv;
	254	try_usbether:
	255	#endif
	256
	257	#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
	258	rv = usb_eth_initialize(bis);
	259	if (rv < 0)
	260	printf("Error %d registering USB_ETHER\n", rv);
	261	else
	262	n += rv;
	263	#endif
	264	return n;
	265	}
	266	#endif