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Commit | Line | Data |
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c2042f59 | 1 | /* |
b81786cf | 2 | * Copyright (C) 2007-2008 |
c2042f59 | 3 | * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
4 | * | |
5 | * Copyright (C) 2007 | |
6 | * Kenati Technologies, Inc. | |
7 | * | |
8 | * board/MigoR/lowlevel_init.S | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
c2042f59 | 11 | */ |
12 | ||
13 | #include <config.h> | |
14 | #include <version.h> | |
15 | ||
16 | #include <asm/processor.h> | |
f7e78f3b | 17 | #include <asm/macro.h> |
c2042f59 | 18 | |
19 | /* | |
e4430779 JCPV |
20 | * Board specific low level init code, called _very_ early in the |
21 | * startup sequence. Relocation to SDRAM has not happened yet, no | |
22 | * stack is available, bss section has not been initialised, etc. | |
c2042f59 | 23 | * |
e4430779 | 24 | * (Note: As no stack is available, no subroutines can be called...). |
c2042f59 | 25 | */ |
26 | ||
27 | .global lowlevel_init | |
28 | ||
29 | .text | |
30 | .align 2 | |
31 | ||
32 | lowlevel_init: | |
f7e78f3b JCPV |
33 | write32 CCR_A, CCR_D ! Address of Cache Control Register |
34 | ! Instruction Cache Invalidate | |
c2042f59 | 35 | |
f7e78f3b JCPV |
36 | write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register |
37 | ! TI == TLB Invalidate bit | |
c2042f59 | 38 | |
f7e78f3b | 39 | write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 |
c2042f59 | 40 | |
f7e78f3b | 41 | write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 |
c2042f59 | 42 | |
f7e78f3b | 43 | write16 PFC_PULCR_A, PFC_PULCR_D |
c2042f59 | 44 | |
f7e78f3b | 45 | write16 PFC_DRVCR_A, PFC_DRVCR_D |
c2042f59 | 46 | |
f7e78f3b | 47 | write16 SBSCR_A, SBSCR_D |
c2042f59 | 48 | |
f7e78f3b | 49 | write16 PSCR_A, PSCR_D |
c2042f59 | 50 | |
f7e78f3b JCPV |
51 | write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) |
52 | ! 0xA507 -> timer_STOP / WDT_CLK = max | |
c2042f59 | 53 | |
f7e78f3b JCPV |
54 | write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) |
55 | ! 0x5A00 -> Clear | |
c2042f59 | 56 | |
f7e78f3b JCPV |
57 | write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) |
58 | ! 0xA504 -> timer_STOP / CLK = 500ms | |
c2042f59 | 59 | |
f7e78f3b JCPV |
60 | write32 DLLFRQ_A, DLLFRQ_D ! 20080115 |
61 | ! 20080115 | |
c2042f59 | 62 | |
f7e78f3b JCPV |
63 | write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register |
64 | ! 20080115 | |
c2042f59 | 65 | |
f7e78f3b JCPV |
66 | write32 CCR_A, CCR_D_2 ! Address of Cache Control Register |
67 | ! ?? | |
c2042f59 | 68 | |
69 | bsc_init: | |
f7e78f3b | 70 | write32 CMNCR_A, CMNCR_D |
c2042f59 | 71 | |
f7e78f3b | 72 | write32 CS0BCR_A, CS0BCR_D |
c2042f59 | 73 | |
f7e78f3b | 74 | write32 CS4BCR_A, CS4BCR_D |
c2042f59 | 75 | |
f7e78f3b | 76 | write32 CS5ABCR_A, CS5ABCR_D |
c2042f59 | 77 | |
f7e78f3b | 78 | write32 CS5BBCR_A, CS5BBCR_D |
c2042f59 | 79 | |
f7e78f3b | 80 | write32 CS6ABCR_A, CS6ABCR_D |
c2042f59 | 81 | |
f7e78f3b | 82 | write32 CS0WCR_A, CS0WCR_D |
c2042f59 | 83 | |
f7e78f3b | 84 | write32 CS4WCR_A, CS4WCR_D |
c2042f59 | 85 | |
f7e78f3b | 86 | write32 CS5AWCR_A, CS5AWCR_D |
c2042f59 | 87 | |
f7e78f3b | 88 | write32 CS5BWCR_A, CS5BWCR_D |
c2042f59 | 89 | |
f7e78f3b | 90 | write32 CS6AWCR_A, CS6AWCR_D |
c2042f59 | 91 | |
92 | ! SDRAM initialization | |
f7e78f3b | 93 | write32 SDCR_A, SDCR_D |
c2042f59 | 94 | |
f7e78f3b | 95 | write32 SDWCR_A, SDWCR_D |
c2042f59 | 96 | |
f7e78f3b | 97 | write32 SDPCR_A, SDPCR_D |
c2042f59 | 98 | |
f7e78f3b | 99 | write32 RTCOR_A, RTCOR_D |
c2042f59 | 100 | |
f7e78f3b | 101 | write32 RTCNT_A, RTCNT_D |
c2042f59 | 102 | |
f7e78f3b | 103 | write32 RTCSR_A, RTCSR_D |
c2042f59 | 104 | |
f7e78f3b | 105 | write32 RFCR_A, RFCR_D |
c2042f59 | 106 | |
c9935c99 | 107 | write8 SDMR3_A, SDMR3_D |
c2042f59 | 108 | |
e4430779 | 109 | ! BL bit off (init = ON) (?!?) |
c2042f59 | 110 | |
111 | stc sr, r0 ! BL bit off(init=ON) | |
112 | mov.l SR_MASK_D, r1 | |
113 | and r1, r0 | |
114 | ldc r0, sr | |
115 | ||
116 | rts | |
117 | mov #0, r0 | |
118 | ||
c2042f59 | 119 | .align 4 |
120 | ||
121 | CCR_A: .long CCR | |
122 | MMUCR_A: .long MMUCR | |
123 | MSTPCR0_A: .long MSTPCR0 | |
124 | MSTPCR2_A: .long MSTPCR2 | |
125 | PFC_PULCR_A: .long PULCR | |
126 | PFC_DRVCR_A: .long DRVCR | |
127 | SBSCR_A: .long SBSCR | |
128 | PSCR_A: .long PSCR | |
129 | RWTCSR_A: .long RWTCSR | |
130 | RWTCNT_A: .long RWTCNT | |
131 | FRQCR_A: .long FRQCR | |
132 | PLLCR_A: .long PLLCR | |
133 | DLLFRQ_A: .long DLLFRQ | |
134 | ||
135 | CCR_D: .long 0x00000800 | |
136 | CCR_D_2: .long 0x00000103 | |
137 | MMUCR_D: .long 0x00000004 | |
138 | MSTPCR0_D: .long 0x00001001 | |
139 | MSTPCR2_D: .long 0xffffffff | |
140 | PFC_PULCR_D: .long 0x6000 | |
141 | PFC_DRVCR_D: .long 0x0464 | |
142 | FRQCR_D: .long 0x07033639 | |
143 | PLLCR_D: .long 0x00005000 | |
b81786cf | 144 | DLLFRQ_D: .long 0x000004F6 |
c2042f59 | 145 | |
146 | CMNCR_A: .long CMNCR | |
b81786cf NI |
147 | CMNCR_D: .long 0x0000001B |
148 | CS0BCR_A: .long CS0BCR | |
c2042f59 | 149 | CS0BCR_D: .long 0x24920400 |
b81786cf NI |
150 | CS4BCR_A: .long CS4BCR |
151 | CS4BCR_D: .long 0x00003400 | |
152 | CS5ABCR_A: .long CS5ABCR | |
c2042f59 | 153 | CS5ABCR_D: .long 0x24920400 |
b81786cf | 154 | CS5BBCR_A: .long CS5BBCR |
c2042f59 | 155 | CS5BBCR_D: .long 0x24920400 |
b81786cf | 156 | CS6ABCR_A: .long CS6ABCR |
c2042f59 | 157 | CS6ABCR_D: .long 0x24920400 |
158 | ||
159 | CS0WCR_A: .long CS0WCR | |
160 | CS0WCR_D: .long 0x00000380 | |
161 | CS4WCR_A: .long CS4WCR | |
b81786cf | 162 | CS4WCR_D: .long 0x00110080 |
c2042f59 | 163 | CS5AWCR_A: .long CS5AWCR |
164 | CS5AWCR_D: .long 0x00000300 | |
165 | CS5BWCR_A: .long CS5BWCR | |
166 | CS5BWCR_D: .long 0x00000300 | |
167 | CS6AWCR_A: .long CS6AWCR | |
168 | CS6AWCR_D: .long 0x00000300 | |
169 | ||
170 | SDCR_A: .long SBSC_SDCR | |
b81786cf | 171 | SDCR_D: .long 0x80160809 |
c2042f59 | 172 | SDWCR_A: .long SBSC_SDWCR |
b81786cf | 173 | SDWCR_D: .long 0x0014450C |
c2042f59 | 174 | SDPCR_A: .long SBSC_SDPCR |
175 | SDPCR_D: .long 0x00000087 | |
176 | RTCOR_A: .long SBSC_RTCOR | |
177 | RTCNT_A: .long SBSC_RTCNT | |
178 | RTCNT_D: .long 0xA55A0012 | |
b81786cf | 179 | RTCOR_D: .long 0xA55A001C |
c2042f59 | 180 | RTCSR_A: .long SBSC_RTCSR |
181 | RFCR_A: .long SBSC_RFCR | |
182 | RFCR_D: .long 0xA55A0221 | |
b81786cf NI |
183 | RTCSR_D: .long 0xA55A009a |
184 | SDMR3_A: .long 0xFE581180 | |
c9935c99 | 185 | SDMR3_D: .long 0x0 |
c2042f59 | 186 | |
187 | SR_MASK_D: .long 0xEFFFFF0F | |
188 | ||
189 | .align 2 | |
190 | ||
191 | SBSCR_D: .word 0x0044 | |
192 | PSCR_D: .word 0x0000 | |
193 | RWTCSR_D_1: .word 0xA507 | |
b81786cf | 194 | RWTCSR_D_2: .word 0xA504 |
c2042f59 | 195 | RWTCNT_D: .word 0x5A00 |