[people/ms/u-boot.git] / board / renesas / blanche / blanche.c

/*
 * board/renesas/blanche/blanche.c
 *     This file is blanche board support.
 *
 * Copyright (C) 2016 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <miiphy.h>
#include <i2c.h>
#include <mmc.h>
#include "qos.h"

DECLARE_GLOBAL_DATA_PTR;

struct pin_db {
	u32	addr;	/* register address */
	u32	mask;	/* mask value */
	u32	val;	/* setting value */
};

#define	PMMR		0xE6060000
#define	GPSR0		0xE6060004
#define	GPSR1		0xE6060008
#define	GPSR4		0xE6060014
#define	GPSR5		0xE6060018
#define	GPSR6		0xE606001C
#define	GPSR7		0xE6060020
#define	GPSR8		0xE6060024
#define	GPSR9		0xE6060028
#define	GPSR10		0xE606002C
#define	GPSR11		0xE6060030
#define	IPSR6		0xE6060058
#define	PUPR2		0xE6060108
#define	PUPR3		0xE606010C
#define	PUPR4		0xE6060110
#define	PUPR5		0xE6060114
#define	PUPR7		0xE606011C
#define	PUPR9		0xE6060124
#define	PUPR10		0xE6060128
#define	PUPR11		0xE606012C

#define	CPG_PLL1CR	0xE6150028
#define	CPG_PLL3CR	0xE61500DC

#define	SetREG(x) \
	writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)

#define	SetGuardREG(x)				\
{ \
	u32	val; \
	val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
	writel(~val, PMMR); \
	writel(val, (x)->addr); \
}

struct pin_db	pin_guard[] = {
	{ GPSR0,	0xFFFFFFFF,	0x0BFFFFFF },
	{ GPSR1,	0xFFFFFFFF,	0x002FFFFF },
	{ GPSR4,	0xFFFFFFFF,	0x00000FFF },
	{ GPSR5,	0xFFFFFFFF,	0x00010FFF },
	{ GPSR6,	0xFFFFFFFF,	0x00010FFF },
	{ GPSR7,	0xFFFFFFFF,	0x00010FFF },
	{ GPSR8,	0xFFFFFFFF,	0x00010FFF },
	{ GPSR9,	0xFFFFFFFF,	0x00010FFF },
	{ GPSR10,	0xFFFFFFFF,	0x04006000 },
	{ GPSR11,	0xFFFFFFFF,	0x303FEFE0 },
	{ IPSR6,	0xFFFFFFFF,	0x0002000E },
};

struct pin_db	pin_tbl[] = {
	{ PUPR2,	0xFFFFFFFF,	0x00000000 },
	{ PUPR3,	0xFFFFFFFF,	0x0803FF40 },
	{ PUPR4,	0xFFFFFFFF,	0x0000FFFF },
	{ PUPR5,	0xFFFFFFFF,	0x00010FFF },
	{ PUPR7,	0xFFFFFFFF,	0x0001AFFF },
	{ PUPR9,	0xFFFFFFFF,	0x0001CFFF },
	{ PUPR10,	0xFFFFFFFF,	0xC0438001 },
	{ PUPR11,	0xFFFFFFFF,	0x0FC00007 },
};

void pin_init(void)
{
	struct pin_db	*db;

	for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
		SetGuardREG(db);
	}
	for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
		SetREG(db);
	}
}

#define s_init_wait(cnt) \
		({	\
			volatile u32 i = 0x10000 * cnt;	\
			while (i > 0)	\
				i--;	\
		})

void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
	u32 cpu_type;

	cpu_type = rmobile_get_cpu_type();
	if (cpu_type == 0x4A) {
		writel(0x4D000000, CPG_PLL1CR);
		writel(0x4F000000, CPG_PLL3CR);
	}

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	/* QoS(Quality-of-Service) Init */
	qos_init();

	/* SCIF Init */
	pin_init();

#if defined(CONFIG_MTD_NOR_FLASH)
	struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
	struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;

	/* LBSC */
	writel(0x00000020, &lbsc->cs0ctrl);
	writel(0x00000020, &lbsc->cs1ctrl);
	writel(0x00002020, &lbsc->ecs0ctrl);
	writel(0x00002020, &lbsc->ecs1ctrl);

	writel(0x2A103320, &lbsc->cswcr0);
	writel(0x2A103320, &lbsc->cswcr1);
	writel(0x19102110, &lbsc->ecswcr0);
	writel(0x19102110, &lbsc->ecswcr1);

	/* DBSC3 */
	s_init_wait(10);

	writel(0x0000A55A, &dbsc3_0->dbpdlck);

	writel(0x21000000, &dbsc3_0->dbcmd);		/* opc=RstH (RESET => H) */
	writel(0x11000000, &dbsc3_0->dbcmd);		/* opc=PDXt(CKE=H) */
	writel(0x10000000, &dbsc3_0->dbcmd);		/* opc=PDEn(CKE=L) */

	/* Stop Auto-Calibration */
	writel(0x00000001, &dbsc3_0->dbpdrga);
	writel(0x80000000, &dbsc3_0->dbpdrgd);

	writel(0x00000004, &dbsc3_0->dbpdrga);
	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);

	/* PLLCR: PLL Control Register */
	writel(0x00000006, &dbsc3_0->dbpdrga);
	writel(0x0001C000, &dbsc3_0->dbpdrgd);	// > DDR1440

	/* DXCCR: DATX8 Common Configuration Register */
	writel(0x0000000F, &dbsc3_0->dbpdrga);
	writel(0x00181EE4, &dbsc3_0->dbpdrgd);

	/* DSGCR	:DDR System General Configuration Register */
	writel(0x00000010, &dbsc3_0->dbpdrga);
	writel(0xF00464DB, &dbsc3_0->dbpdrgd);

	writel(0x00000061, &dbsc3_0->dbpdrga);
	writel(0x0000008D, &dbsc3_0->dbpdrgd);

	/* Re-Execute ZQ calibration */
	writel(0x00000001, &dbsc3_0->dbpdrga);
	writel(0x00000073, &dbsc3_0->dbpdrgd);

	writel(0x00000007, &dbsc3_0->dbkind);
	writel(0x0F030A02, &dbsc3_0->dbconf0);
	writel(0x00000001, &dbsc3_0->dbphytype);
	writel(0x00000000, &dbsc3_0->dbbl);

	writel(0x0000000B, &dbsc3_0->dbtr0);	// tCL=11
	writel(0x00000008, &dbsc3_0->dbtr1);	// tCWL=8
	writel(0x00000000, &dbsc3_0->dbtr2);	// tAL=0
	writel(0x0000000B, &dbsc3_0->dbtr3);	// tRCD=11
	writel(0x000C000B, &dbsc3_0->dbtr4);	// tRPA=12,tRP=11
	writel(0x00000027, &dbsc3_0->dbtr5);	// tRC = 39
	writel(0x0000001C, &dbsc3_0->dbtr6);	// tRAS = 28
	writel(0x00000006, &dbsc3_0->dbtr7);	// tRRD = 6
	writel(0x00000020, &dbsc3_0->dbtr8);	// tRFAW = 32
	writel(0x00000008, &dbsc3_0->dbtr9);	// tRDPR = 8
	writel(0x0000000C, &dbsc3_0->dbtr10);	// tWR = 12
	writel(0x00000009, &dbsc3_0->dbtr11);	// tRDWR = 9
	writel(0x00000012, &dbsc3_0->dbtr12);	// tWRRD = 18
	writel(0x000000D0, &dbsc3_0->dbtr13);	// tRFC = 208
	writel(0x00140005, &dbsc3_0->dbtr14);
	writel(0x00050004, &dbsc3_0->dbtr15);
	writel(0x70233005, &dbsc3_0->dbtr16);		/* DQL = 35, WDQL = 5 */
	writel(0x000C0000, &dbsc3_0->dbtr17);
	writel(0x00000300, &dbsc3_0->dbtr18);
	writel(0x00000040, &dbsc3_0->dbtr19);
	writel(0x00000001, &dbsc3_0->dbrnk0);
	writel(0x00020001, &dbsc3_0->dbadj0);
	writel(0x20082004, &dbsc3_0->dbadj2);		/* blanche QoS rev0.1 */
	writel(0x00020002, &dbsc3_0->dbwt0cnf0);	/* 1600 */
	writel(0x0000001F, &dbsc3_0->dbwt0cnf4);

	while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
	writel(0x00000011, &dbsc3_0->dbdficnt);

	/* PGCR1	:PHY General Configuration Register 1 */
	writel(0x00000003, &dbsc3_0->dbpdrga);
	writel(0x0300C4E1, &dbsc3_0->dbpdrgd);		/* DDR3 */

	/* PGCR2: PHY General Configuration Registers 2 */
	writel(0x00000023, &dbsc3_0->dbpdrga);
	writel(0x00FCDB60, &dbsc3_0->dbpdrgd);

	writel(0x00000011, &dbsc3_0->dbpdrga);
	writel(0x1000040B, &dbsc3_0->dbpdrgd);

	/* DTPR0	:DRAM Timing Parameters Register 0 */
	writel(0x00000012, &dbsc3_0->dbpdrga);
	writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);

	/* DTPR1	:DRAM Timing Parameters Register 1 */
	writel(0x00000013, &dbsc3_0->dbpdrga);
	writel(0x1A868400, &dbsc3_0->dbpdrgd);

	/* DTPR2	::DRAM Timing Parameters Register 2 */
	writel(0x00000014, &dbsc3_0->dbpdrga);
	writel(0x300214D8, &dbsc3_0->dbpdrgd);

	/* MR0	:Mode Register 0 */
	writel(0x00000015, &dbsc3_0->dbpdrga);
	writel(0x00000D70, &dbsc3_0->dbpdrgd);

	/* MR1	:Mode Register 1 */
	writel(0x00000016, &dbsc3_0->dbpdrga);
	writel(0x00000004, &dbsc3_0->dbpdrgd);	/* DRAM Drv 40ohm */

	/* MR2	:Mode Register 2 */
	writel(0x00000017, &dbsc3_0->dbpdrga);
	writel(0x00000018, &dbsc3_0->dbpdrgd);	/* CWL=8 */

	/* VREF(ZQCAL) */
	writel(0x0000001A, &dbsc3_0->dbpdrga);
	writel(0x910035C7, &dbsc3_0->dbpdrgd);

	/* PGSR0	:PHY General Status Registers 0 */
	writel(0x00000004, &dbsc3_0->dbpdrga);
	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);

	/* DRAM Init (set MRx etc) */
	writel(0x00000001, &dbsc3_0->dbpdrga);
	writel(0x00000181, &dbsc3_0->dbpdrgd);

	/* CKE  = H */
	writel(0x11000000, &dbsc3_0->dbcmd);		/* opc=PDXt(CKE=H) */

	/* PGSR0	:PHY General Status Registers 0 */
	writel(0x00000004, &dbsc3_0->dbpdrga);
	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);

	/* RAM ACC Training */
	writel(0x00000001, &dbsc3_0->dbpdrga);
	writel(0x0000FE01, &dbsc3_0->dbpdrgd);

	/* Bus control 0 */
	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
	/* DDR3 Calibration set */
	writel(0x01004C20, &dbsc3_0->dbcalcnf);
	/* DDR3 Calibration timing */
	writel(0x014000AA, &dbsc3_0->dbcaltr);
	/* Refresh */
	writel(0x00000140, &dbsc3_0->dbrfcnf0);
	writel(0x00081860, &dbsc3_0->dbrfcnf1);
	writel(0x00010000, &dbsc3_0->dbrfcnf2);

	/* PGSR0	:PHY General Status Registers 0 */
	writel(0x00000004, &dbsc3_0->dbpdrga);
	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);

	/* Enable Auto-Refresh */
	writel(0x00000001, &dbsc3_0->dbrfen);
	/* Permit DDR-Access */
	writel(0x00000001, &dbsc3_0->dbacen);

	/* This locks the access to the PHY unit registers */
	writel(0x00000000, &dbsc3_0->dbpdlck);
#endif /* CONFIG_MTD_NOR_FLASH */

}

#define TMU0_MSTP125	(1 << 25)
#define SCIF0_MSTP721	(1 << 21)
#define SDHI0_MSTP314	(1 << 14)
#define QSPI_MSTP917	(1 << 17)

int board_early_init_f(void)
{
	/* TMU0 */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	/* SCIF0 */
	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
	/* SDHI0 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
	/* QSPI */
	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);

	return 0;
}

DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	/* Init PFC controller */
	r8a7792_pinmux_init();

	gpio_request(GPIO_FN_D0, NULL);
	gpio_request(GPIO_FN_D1, NULL);
	gpio_request(GPIO_FN_D2, NULL);
	gpio_request(GPIO_FN_D3, NULL);
	gpio_request(GPIO_FN_D4, NULL);
	gpio_request(GPIO_FN_D5, NULL);
	gpio_request(GPIO_FN_D6, NULL);
	gpio_request(GPIO_FN_D7, NULL);
	gpio_request(GPIO_FN_D8, NULL);
	gpio_request(GPIO_FN_D9, NULL);
	gpio_request(GPIO_FN_D10, NULL);
	gpio_request(GPIO_FN_D11, NULL);
	gpio_request(GPIO_FN_D12, NULL);
	gpio_request(GPIO_FN_D13, NULL);
	gpio_request(GPIO_FN_D14, NULL);
	gpio_request(GPIO_FN_D15, NULL);
	gpio_request(GPIO_FN_A0, NULL);
	gpio_request(GPIO_FN_A1, NULL);
	gpio_request(GPIO_FN_A2, NULL);
	gpio_request(GPIO_FN_A3, NULL);
	gpio_request(GPIO_FN_A4, NULL);
	gpio_request(GPIO_FN_A5, NULL);
	gpio_request(GPIO_FN_A6, NULL);
	gpio_request(GPIO_FN_A7, NULL);
	gpio_request(GPIO_FN_A8, NULL);
	gpio_request(GPIO_FN_A9, NULL);
	gpio_request(GPIO_FN_A10, NULL);
	gpio_request(GPIO_FN_A11, NULL);
	gpio_request(GPIO_FN_A12, NULL);
	gpio_request(GPIO_FN_A13, NULL);
	gpio_request(GPIO_FN_A14, NULL);
	gpio_request(GPIO_FN_A15, NULL);
	gpio_request(GPIO_FN_A16, NULL);
	gpio_request(GPIO_FN_A17, NULL);
	gpio_request(GPIO_FN_A18, NULL);
	gpio_request(GPIO_FN_A19, NULL);
#if !defined(CONFIG_MTD_NOR_FLASH)
	gpio_request(GPIO_FN_MOSI_IO0, NULL);
	gpio_request(GPIO_FN_MISO_IO1, NULL);
	gpio_request(GPIO_FN_IO2, NULL);
	gpio_request(GPIO_FN_IO3, NULL);
	gpio_request(GPIO_FN_SPCLK, NULL);
	gpio_request(GPIO_FN_SSL, NULL);
#else	/* CONFIG_MTD_NOR_FLASH */
	gpio_request(GPIO_FN_A20, NULL);
	gpio_request(GPIO_FN_A21, NULL);
	gpio_request(GPIO_FN_A22, NULL);
	gpio_request(GPIO_FN_A23, NULL);
	gpio_request(GPIO_FN_A24, NULL);
	gpio_request(GPIO_FN_A25, NULL);
#endif	/* CONFIG_MTD_NOR_FLASH */

	gpio_request(GPIO_FN_CS1_A26, NULL);
	gpio_request(GPIO_FN_EX_CS0, NULL);
	gpio_request(GPIO_FN_EX_CS1, NULL);
	gpio_request(GPIO_FN_BS, NULL);
	gpio_request(GPIO_FN_RD, NULL);
	gpio_request(GPIO_FN_WE0, NULL);
	gpio_request(GPIO_FN_WE1, NULL);
	gpio_request(GPIO_FN_EX_WAIT0, NULL);
	gpio_request(GPIO_FN_IRQ0, NULL);
	gpio_request(GPIO_FN_IRQ2, NULL);
	gpio_request(GPIO_FN_IRQ3, NULL);
	gpio_request(GPIO_FN_CS0, NULL);

	/* Init timer */
	timer_init();

	return 0;
}

/*
 Added for BLANCHE(R-CarV2H board)
*/
int board_eth_init(bd_t *bis)
{
	int rc = 0;

#ifdef CONFIG_SMC911X
#define STR_ENV_ETHADDR	"ethaddr"

	struct eth_device *dev;
	uchar eth_addr[6];

	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);

	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
		dev = eth_get_dev_by_index(0);
		if (dev) {
			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
		} else {
			printf("blanche: Couldn't get eth device\n");
			rc = -1;
		}
	}

#endif

	return rc;
}

int board_mmc_init(bd_t *bis)
{
	int ret = -ENODEV;

#ifdef CONFIG_SH_SDHI
	gpio_request(GPIO_FN_SD0_DAT0, NULL);
	gpio_request(GPIO_FN_SD0_DAT1, NULL);
	gpio_request(GPIO_FN_SD0_DAT2, NULL);
	gpio_request(GPIO_FN_SD0_DAT3, NULL);
	gpio_request(GPIO_FN_SD0_CLK, NULL);
	gpio_request(GPIO_FN_SD0_CMD, NULL);
	gpio_request(GPIO_FN_SD0_CD, NULL);

	gpio_request(GPIO_GP_11_12, NULL);
	gpio_direction_output(GPIO_GP_11_12, 1);	/* power on */


	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
			   SH_SDHI_QUIRK_16BIT_BUF);

	if (ret)
		return ret;
#endif
	return ret;
}

int dram_init(void)
{
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}

const struct rmobile_sysinfo sysinfo = {
	CONFIG_RMOBILE_BOARD_STRING
};

void reset_cpu(ulong addr)
{
}

static const struct sh_serial_platdata serial_platdata = {
	.base = SCIF0_BASE,
	.type = PORT_SCIF,
	.clk = 14745600,
	.clk_mode = EXT_CLK,
};

U_BOOT_DEVICE(blanche_serials) = {
	.name = "serial_sh",
	.platdata = &serial_platdata,
};
Commit	Line	Data
6f107e4c	1	/*
	2	* board/renesas/blanche/blanche.c
	3	* This file is blanche board support.
	4	*
	5	* Copyright (C) 2016 Renesas Electronics Corporation
	6	*
	7	* SPDX-License-Identifier: GPL-2.0
	8	*/
	9
	10	#include <common.h>
	11	#include <malloc.h>
	12	#include <netdev.h>
	13	#include <dm.h>
	14	#include <dm/platform_data/serial_sh.h>
	15	#include <asm/processor.h>
	16	#include <asm/mach-types.h>
	17	#include <asm/io.h>
1221ce45	18	#include <linux/errno.h>
6f107e4c	19	#include <asm/arch/sys_proto.h>
	20	#include <asm/gpio.h>
	21	#include <asm/arch/rmobile.h>
	22	#include <asm/arch/rcar-mstp.h>
	23	#include <asm/arch/mmc.h>
	24	#include <asm/arch/sh_sdhi.h>
	25	#include <miiphy.h>
	26	#include <i2c.h>
	27	#include <mmc.h>
	28	#include "qos.h"
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	struct pin_db {
	33	u32 addr; /* register address */
	34	u32 mask; /* mask value */
	35	u32 val; /* setting value */
	36	};
	37
	38	#define PMMR 0xE6060000
d8fc402a	39	#define GPSR0 0xE6060004
	40	#define GPSR1 0xE6060008
	41	#define GPSR4 0xE6060014
	42	#define GPSR5 0xE6060018
	43	#define GPSR6 0xE606001C
	44	#define GPSR7 0xE6060020
	45	#define GPSR8 0xE6060024
	46	#define GPSR9 0xE6060028
6f107e4c	47	#define GPSR10 0xE606002C
d8fc402a	48	#define GPSR11 0xE6060030
	49	#define IPSR6 0xE6060058
	50	#define PUPR2 0xE6060108
6f107e4c	51	#define PUPR3 0xE606010C
d8fc402a	52	#define PUPR4 0xE6060110
	53	#define PUPR5 0xE6060114
	54	#define PUPR7 0xE606011C
	55	#define PUPR9 0xE6060124
6f107e4c	56	#define PUPR10 0xE6060128
	57	#define PUPR11 0xE606012C
	58
	59	#define CPG_PLL1CR 0xE6150028
	60	#define CPG_PLL3CR 0xE61500DC
	61
	62	#define SetREG(x) \
	63	writel((readl((x)->addr) & ~((x)->mask)) \| ((x)->val), (x)->addr)
	64
	65	#define SetGuardREG(x) \
	66	{ \
	67	u32 val; \
	68	val = (readl((x)->addr) & ~((x)->mask)) \| ((x)->val); \
	69	writel(~val, PMMR); \
	70	writel(val, (x)->addr); \
	71	}
	72
	73	struct pin_db pin_guard[] = {
d8fc402a	74	{ GPSR0, 0xFFFFFFFF, 0x0BFFFFFF },
	75	{ GPSR1, 0xFFFFFFFF, 0x002FFFFF },
	76	{ GPSR4, 0xFFFFFFFF, 0x00000FFF },
	77	{ GPSR5, 0xFFFFFFFF, 0x00010FFF },
	78	{ GPSR6, 0xFFFFFFFF, 0x00010FFF },
	79	{ GPSR7, 0xFFFFFFFF, 0x00010FFF },
	80	{ GPSR8, 0xFFFFFFFF, 0x00010FFF },
	81	{ GPSR9, 0xFFFFFFFF, 0x00010FFF },
6f107e4c	82	{ GPSR10, 0xFFFFFFFF, 0x04006000 },
d8fc402a	83	{ GPSR11, 0xFFFFFFFF, 0x303FEFE0 },
d8fc402a	84	{ IPSR6, 0xFFFFFFFF, 0x0002000E },
6f107e4c	85	};
	86
	87	struct pin_db pin_tbl[] = {
d8fc402a	88	{ PUPR2, 0xFFFFFFFF, 0x00000000 },
6f107e4c	89	{ PUPR3, 0xFFFFFFFF, 0x0803FF40 },
d8fc402a	90	{ PUPR4, 0xFFFFFFFF, 0x0000FFFF },
	91	{ PUPR5, 0xFFFFFFFF, 0x00010FFF },
	92	{ PUPR7, 0xFFFFFFFF, 0x0001AFFF },
	93	{ PUPR9, 0xFFFFFFFF, 0x0001CFFF },
6f107e4c	94	{ PUPR10, 0xFFFFFFFF, 0xC0438001 },
	95	{ PUPR11, 0xFFFFFFFF, 0x0FC00007 },
	96	};
	97
	98	void pin_init(void)
	99	{
	100	struct pin_db *db;
	101
	102	for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
	103	SetGuardREG(db);
	104	}
	105	for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
	106	SetREG(db);
	107	}
	108	}
	109
	110	#define s_init_wait(cnt) \
	111	({ \
	112	volatile u32 i = 0x10000 * cnt; \
	113	while (i > 0) \
	114	i--; \
	115	})
	116
	117	void s_init(void)
	118	{
	119	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	120	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	121	u32 cpu_type;
	122
	123	cpu_type = rmobile_get_cpu_type();
	124	if (cpu_type == 0x4A) {
	125	writel(0x4D000000, CPG_PLL1CR);
	126	writel(0x4F000000, CPG_PLL3CR);
	127	}
	128
	129	/* Watchdog init */
	130	writel(0xA5A5A500, &rwdt->rwtcsra);
	131	writel(0xA5A5A500, &swdt->swtcsra);
	132
	133	/* QoS(Quality-of-Service) Init */
	134	qos_init();
	135
	136	/* SCIF Init */
	137	pin_init();
	138
e856bdcf	139	#if defined(CONFIG_MTD_NOR_FLASH)
6f107e4c	140	struct rcar_lbsc lbsc = (struct rcar_lbsc )LBSC_BASE;
	141	struct rcar_dbsc3 dbsc3_0 = (struct rcar_dbsc3 )DBSC3_0_BASE;
	142
	143	/* LBSC */
	144	writel(0x00000020, &lbsc->cs0ctrl);
	145	writel(0x00000020, &lbsc->cs1ctrl);
	146	writel(0x00002020, &lbsc->ecs0ctrl);
	147	writel(0x00002020, &lbsc->ecs1ctrl);
	148
	149	writel(0x2A103320, &lbsc->cswcr0);
	150	writel(0x2A103320, &lbsc->cswcr1);
	151	writel(0x19102110, &lbsc->ecswcr0);
	152	writel(0x19102110, &lbsc->ecswcr1);
	153
	154	/* DBSC3 */
	155	s_init_wait(10);
	156
	157	writel(0x0000A55A, &dbsc3_0->dbpdlck);
	158
	159	writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */
	160	writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
	161	writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */
	162
	163	/* Stop Auto-Calibration */
	164	writel(0x00000001, &dbsc3_0->dbpdrga);
	165	writel(0x80000000, &dbsc3_0->dbpdrgd);
	166
	167	writel(0x00000004, &dbsc3_0->dbpdrga);
	168	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
	169
	170	/* PLLCR: PLL Control Register */
	171	writel(0x00000006, &dbsc3_0->dbpdrga);
	172	writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440
	173
	174	/* DXCCR: DATX8 Common Configuration Register */
	175	writel(0x0000000F, &dbsc3_0->dbpdrga);
	176	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
	177
	178	/* DSGCR :DDR System General Configuration Register */
	179	writel(0x00000010, &dbsc3_0->dbpdrga);
	180	writel(0xF00464DB, &dbsc3_0->dbpdrgd);
	181
	182	writel(0x00000061, &dbsc3_0->dbpdrga);
	183	writel(0x0000008D, &dbsc3_0->dbpdrgd);
	184
	185	/* Re-Execute ZQ calibration */
	186	writel(0x00000001, &dbsc3_0->dbpdrga);
	187	writel(0x00000073, &dbsc3_0->dbpdrgd);
	188
	189	writel(0x00000007, &dbsc3_0->dbkind);
	190	writel(0x0F030A02, &dbsc3_0->dbconf0);
	191	writel(0x00000001, &dbsc3_0->dbphytype);
	192	writel(0x00000000, &dbsc3_0->dbbl);
	193
	194	writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11
	195	writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8
	196	writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0
	197	writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11
	198	writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11
	199	writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39
	200	writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28
	201	writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6
	202	writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32
	203	writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8
204	writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12
205	writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9
206	writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18
207	writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208
208	writel(0x00140005, &dbsc3_0->dbtr14);
209	writel(0x00050004, &dbsc3_0->dbtr15);
210	writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */
211	writel(0x000C0000, &dbsc3_0->dbtr17);
212	writel(0x00000300, &dbsc3_0->dbtr18);
213	writel(0x00000040, &dbsc3_0->dbtr19);
214	writel(0x00000001, &dbsc3_0->dbrnk0);
215	writel(0x00020001, &dbsc3_0->dbadj0);
216	writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */
217	writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */
218	writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
219
220	while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
221	writel(0x00000011, &dbsc3_0->dbdficnt);
222
223	/* PGCR1 :PHY General Configuration Register 1 */
224	writel(0x00000003, &dbsc3_0->dbpdrga);
225	writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */
226
227	/* PGCR2: PHY General Configuration Registers 2 */
228	writel(0x00000023, &dbsc3_0->dbpdrga);
229	writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
230
231	writel(0x00000011, &dbsc3_0->dbpdrga);
232	writel(0x1000040B, &dbsc3_0->dbpdrgd);
233
234	/* DTPR0 :DRAM Timing Parameters Register 0 */
235	writel(0x00000012, &dbsc3_0->dbpdrga);
236	writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
237
238	/* DTPR1 :DRAM Timing Parameters Register 1 */
239	writel(0x00000013, &dbsc3_0->dbpdrga);
240	writel(0x1A868400, &dbsc3_0->dbpdrgd);
241
242	/* DTPR2 ::DRAM Timing Parameters Register 2 */
243	writel(0x00000014, &dbsc3_0->dbpdrga);
244	writel(0x300214D8, &dbsc3_0->dbpdrgd);
245
246	/* MR0 :Mode Register 0 */
247	writel(0x00000015, &dbsc3_0->dbpdrga);
248	writel(0x00000D70, &dbsc3_0->dbpdrgd);
249
250	/* MR1 :Mode Register 1 */
251	writel(0x00000016, &dbsc3_0->dbpdrga);
252	writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */
253
254	/* MR2 :Mode Register 2 */
255	writel(0x00000017, &dbsc3_0->dbpdrga);
256	writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */
257
258	/* VREF(ZQCAL) */
259	writel(0x0000001A, &dbsc3_0->dbpdrga);
260	writel(0x910035C7, &dbsc3_0->dbpdrgd);
261
262	/* PGSR0 :PHY General Status Registers 0 */
263	writel(0x00000004, &dbsc3_0->dbpdrga);
264	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
265
266	/* DRAM Init (set MRx etc) */
267	writel(0x00000001, &dbsc3_0->dbpdrga);
268	writel(0x00000181, &dbsc3_0->dbpdrgd);
269
270	/* CKE = H */
271	writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */
272
273	/* PGSR0 :PHY General Status Registers 0 */
274	writel(0x00000004, &dbsc3_0->dbpdrga);
275	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
276
277	/* RAM ACC Training */
278	writel(0x00000001, &dbsc3_0->dbpdrga);
279	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
280
281	/* Bus control 0 */
282	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
283	/* DDR3 Calibration set */
284	writel(0x01004C20, &dbsc3_0->dbcalcnf);
285	/* DDR3 Calibration timing */
286	writel(0x014000AA, &dbsc3_0->dbcaltr);
287	/* Refresh */
288	writel(0x00000140, &dbsc3_0->dbrfcnf0);
289	writel(0x00081860, &dbsc3_0->dbrfcnf1);
290	writel(0x00010000, &dbsc3_0->dbrfcnf2);
291
292	/* PGSR0 :PHY General Status Registers 0 */
293	writel(0x00000004, &dbsc3_0->dbpdrga);
294	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
295
296	/* Enable Auto-Refresh */
297	writel(0x00000001, &dbsc3_0->dbrfen);
298	/* Permit DDR-Access */
299	writel(0x00000001, &dbsc3_0->dbacen);
300
301	/* This locks the access to the PHY unit registers */
302	writel(0x00000000, &dbsc3_0->dbpdlck);
e856bdcf	303	#endif /* CONFIG_MTD_NOR_FLASH */
6f107e4c	304
	305	}
	306
	307	#define TMU0_MSTP125 (1 << 25)
	308	#define SCIF0_MSTP721 (1 << 21)
	309	#define SDHI0_MSTP314 (1 << 14)
	310	#define QSPI_MSTP917 (1 << 17)
	311
	312	int board_early_init_f(void)
	313	{
	314	/* TMU0 */
	315	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	316	/* SCIF0 */
	317	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
	318	/* SDHI0 */
	319	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
	320	/* QSPI */
	321	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
	322
	323	return 0;
	324	}
	325
	326	DECLARE_GLOBAL_DATA_PTR;
	327	int board_init(void)
	328	{
	329	/* adress of boot parameters */
	330	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	331
	332	/* Init PFC controller */
	333	r8a7792_pinmux_init();
	334
	335	gpio_request(GPIO_FN_D0, NULL);
	336	gpio_request(GPIO_FN_D1, NULL);
	337	gpio_request(GPIO_FN_D2, NULL);
	338	gpio_request(GPIO_FN_D3, NULL);
	339	gpio_request(GPIO_FN_D4, NULL);
	340	gpio_request(GPIO_FN_D5, NULL);
	341	gpio_request(GPIO_FN_D6, NULL);
	342	gpio_request(GPIO_FN_D7, NULL);
	343	gpio_request(GPIO_FN_D8, NULL);
	344	gpio_request(GPIO_FN_D9, NULL);
	345	gpio_request(GPIO_FN_D10, NULL);
	346	gpio_request(GPIO_FN_D11, NULL);
	347	gpio_request(GPIO_FN_D12, NULL);
	348	gpio_request(GPIO_FN_D13, NULL);
	349	gpio_request(GPIO_FN_D14, NULL);
	350	gpio_request(GPIO_FN_D15, NULL);
	351	gpio_request(GPIO_FN_A0, NULL);
	352	gpio_request(GPIO_FN_A1, NULL);
	353	gpio_request(GPIO_FN_A2, NULL);
	354	gpio_request(GPIO_FN_A3, NULL);
	355	gpio_request(GPIO_FN_A4, NULL);
	356	gpio_request(GPIO_FN_A5, NULL);
	357	gpio_request(GPIO_FN_A6, NULL);
	358	gpio_request(GPIO_FN_A7, NULL);
	359	gpio_request(GPIO_FN_A8, NULL);
	360	gpio_request(GPIO_FN_A9, NULL);
	361	gpio_request(GPIO_FN_A10, NULL);
	362	gpio_request(GPIO_FN_A11, NULL);
	363	gpio_request(GPIO_FN_A12, NULL);
	364	gpio_request(GPIO_FN_A13, NULL);
	365	gpio_request(GPIO_FN_A14, NULL);
	366	gpio_request(GPIO_FN_A15, NULL);
	367	gpio_request(GPIO_FN_A16, NULL);
368	gpio_request(GPIO_FN_A17, NULL);
369	gpio_request(GPIO_FN_A18, NULL);
370	gpio_request(GPIO_FN_A19, NULL);
e856bdcf	371	#if !defined(CONFIG_MTD_NOR_FLASH)
6f107e4c	372	gpio_request(GPIO_FN_MOSI_IO0, NULL);
	373	gpio_request(GPIO_FN_MISO_IO1, NULL);
	374	gpio_request(GPIO_FN_IO2, NULL);
	375	gpio_request(GPIO_FN_IO3, NULL);
	376	gpio_request(GPIO_FN_SPCLK, NULL);
	377	gpio_request(GPIO_FN_SSL, NULL);
e856bdcf	378	#else /* CONFIG_MTD_NOR_FLASH */
6f107e4c	379	gpio_request(GPIO_FN_A20, NULL);
	380	gpio_request(GPIO_FN_A21, NULL);
	381	gpio_request(GPIO_FN_A22, NULL);
	382	gpio_request(GPIO_FN_A23, NULL);
	383	gpio_request(GPIO_FN_A24, NULL);
	384	gpio_request(GPIO_FN_A25, NULL);
e856bdcf	385	#endif /* CONFIG_MTD_NOR_FLASH */
6f107e4c	386
	387	gpio_request(GPIO_FN_CS1_A26, NULL);
	388	gpio_request(GPIO_FN_EX_CS0, NULL);
	389	gpio_request(GPIO_FN_EX_CS1, NULL);
	390	gpio_request(GPIO_FN_BS, NULL);
	391	gpio_request(GPIO_FN_RD, NULL);
	392	gpio_request(GPIO_FN_WE0, NULL);
	393	gpio_request(GPIO_FN_WE1, NULL);
	394	gpio_request(GPIO_FN_EX_WAIT0, NULL);
	395	gpio_request(GPIO_FN_IRQ0, NULL);
	396	gpio_request(GPIO_FN_IRQ2, NULL);
	397	gpio_request(GPIO_FN_IRQ3, NULL);
	398	gpio_request(GPIO_FN_CS0, NULL);
	399
	400	/* Init timer */
	401	timer_init();
	402
	403	return 0;
	404	}
	405
	406	/*
	407	Added for BLANCHE(R-CarV2H board)
	408	*/
	409	int board_eth_init(bd_t *bis)
	410	{
	411	int rc = 0;
	412
	413	#ifdef CONFIG_SMC911X
	414	#define STR_ENV_ETHADDR "ethaddr"
	415
	416	struct eth_device *dev;
	417	uchar eth_addr[6];
	418
	419	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	420
	421	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
	422	dev = eth_get_dev_by_index(0);
	423	if (dev) {
	424	eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
	425	} else {
	426	printf("blanche: Couldn't get eth device\n");
	427	rc = -1;
	428	}
	429	}
	430
	431	#endif
	432
	433	return rc;
	434	}
	435
	436	int board_mmc_init(bd_t *bis)
	437	{
	438	int ret = -ENODEV;
	439
	440	#ifdef CONFIG_SH_SDHI
	441	gpio_request(GPIO_FN_SD0_DAT0, NULL);
	442	gpio_request(GPIO_FN_SD0_DAT1, NULL);
	443	gpio_request(GPIO_FN_SD0_DAT2, NULL);
	444	gpio_request(GPIO_FN_SD0_DAT3, NULL);
	445	gpio_request(GPIO_FN_SD0_CLK, NULL);
	446	gpio_request(GPIO_FN_SD0_CMD, NULL);
	447	gpio_request(GPIO_FN_SD0_CD, NULL);
	448
	449	gpio_request(GPIO_GP_11_12, NULL);
450	gpio_direction_output(GPIO_GP_11_12, 1); /* power on */
451
452
453	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
454	SH_SDHI_QUIRK_16BIT_BUF);
455
456	if (ret)
457	return ret;
458	#endif
459	return ret;
460	}
461
462	int dram_init(void)
463	{
464	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
465	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
466
467	return 0;
468	}
469
470	const struct rmobile_sysinfo sysinfo = {
471	CONFIG_RMOBILE_BOARD_STRING
472	};
473
474	void reset_cpu(ulong addr)
475	{
476	}
477
478	static const struct sh_serial_platdata serial_platdata = {
479	.base = SCIF0_BASE,
480	.type = PORT_SCIF,
481	.clk = 14745600,
482	.clk_mode = EXT_CLK,
483	};
484
485	U_BOOT_DEVICE(blanche_serials) = {
486	.name = "serial_sh",
487	.platdata = &serial_platdata,
488	};