projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6d1d5cf9 NI |
1 | /* |
| 2 | * Copyright (C) 2011 Renesas Solutions Corp. | |
| 3 | * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com> | |
| 4 | * | |
| 5 | * board/renesas/ecovec/lowlevel_init.S | |
| 6 | * | |
| 1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 6d1d5cf9 NI |
8 | */ |
| 9 | ||
| 10 | #include <config.h> | |
| 11 | #include <version.h> | |
| 12 | #include <asm/processor.h> | |
| 13 | #include <asm/macro.h> | |
| 14 | #include <configs/ecovec.h> | |
| 15 | ||
| 16 | .global lowlevel_init | |
| 17 | ||
| 18 | .text | |
| 19 | .align 2 | |
| 20 | ||
| 21 | lowlevel_init: | |
| 22 | ||
| 23 | /* jump to 0xA0020000 if bit 1 of PVDR_A */ | |
| 24 | mov.l PVDR_A, r1 | |
| 25 | mov.l PVDR_D, r2 | |
| 26 | mov.b @r1, r0 | |
| 27 | tst r0, r2 | |
| 28 | bt 1f | |
| 29 | mov.l JUMP_A, r1 | |
| 30 | jmp @r1 | |
| 31 | nop | |
| 32 | ||
| 33 | 1: | |
| 34 | /* Disable watchdog */ | |
| 35 | write16 RWTCSR_A, RWTCSR_D | |
| 36 | ||
| 37 | /* MMU Disable */ | |
| 38 | write32 MMUCR_A, MMUCR_D | |
| 39 | ||
| 40 | /* Setup clocks */ | |
| 41 | write32 PLLCR_A, PLLCR_D | |
| 42 | write32 FRQCRA_A, FRQCRA_D | |
| 43 | write32 FRQCRB_A, FRQCRB_D | |
| 44 | ||
| 45 | wait_timer TIMER_D | |
| 46 | ||
| 47 | write32 MMSELR_A, MMSELR_D | |
| 48 | ||
| 49 | /* Srtup BSC */ | |
| 50 | write32 CMNCR_A, CMNCR_D | |
| 51 | write32 CS0BCR_A, CS0BCR_D | |
| 52 | write32 CS0WCR_A, CS0WCR_D | |
| 53 | ||
| 54 | wait_timer TIMER_D | |
| 55 | ||
| 56 | /* Setup SDRAM */ | |
| 57 | write32 DBPDCNT0_A, DBPDCNT0_D0 | |
| 58 | write32 DBCONF_A, DBCONF_D | |
| 59 | write32 DBTR0_A, DBTR0_D | |
| 60 | write32 DBTR1_A, DBTR1_D | |
| 61 | write32 DBTR2_A, DBTR2_D | |
| 62 | write32 DBTR3_A, DBTR3_D | |
| 63 | write32 DBKIND_A, DBKIND_D | |
| 64 | write32 DBCKECNT_A, DBCKECNT_D | |
| 65 | ||
| 66 | wait_timer TIMER_D | |
| 67 | ||
| 68 | write32 DBCMDCNT_A, DBCMDCNT_D0 | |
| 69 | write32 DBMRCNT_A, DBMRCNT_D0 | |
| 70 | write32 DBMRCNT_A, DBMRCNT_D1 | |
| 71 | write32 DBMRCNT_A, DBMRCNT_D2 | |
| 72 | write32 DBMRCNT_A, DBMRCNT_D3 | |
| 73 | write32 DBCMDCNT_A, DBCMDCNT_D0 | |
| 74 | write32 DBCMDCNT_A, DBCMDCNT_D1 | |
| 75 | write32 DBCMDCNT_A, DBCMDCNT_D1 | |
| 76 | write32 DBMRCNT_A, DBMRCNT_D4 | |
| 77 | write32 DBMRCNT_A, DBMRCNT_D5 | |
| 78 | write32 DBMRCNT_A, DBMRCNT_D6 | |
| 79 | ||
| 80 | wait_timer TIMER_D | |
| 81 | ||
| 82 | write32 DBEN_A, DBEN_D | |
| 83 | write32 DBRFPDN1_A, DBRFPDN1_D | |
| 84 | write32 DBRFPDN2_A, DBRFPDN2_D | |
| 85 | write32 DBCMDCNT_A, DBCMDCNT_D0 | |
| 86 | ||
| 87 | ||
| 88 | /* Dummy read */ | |
| 89 | mov.l DUMMY_A ,r1 | |
| 90 | synco | |
| 91 | mov.l @r1, r0 | |
| 92 | synco | |
| 93 | ||
| 94 | mov.l SDRAM_A ,r1 | |
| 95 | synco | |
| 96 | mov.l @r1, r0 | |
| 97 | synco | |
| 98 | wait_timer TIMER_D | |
| 99 | ||
| 100 | add #4, r1 | |
| 101 | synco | |
| 102 | mov.l @r1, r0 | |
| 103 | synco | |
| 104 | wait_timer TIMER_D | |
| 105 | ||
| 106 | add #4, r1 | |
| 107 | synco | |
| 108 | mov.l @r1, r0 | |
| 109 | synco | |
| 110 | wait_timer TIMER_D | |
| 111 | ||
| 112 | add #4, r1 | |
| 113 | synco | |
| 114 | mov.l @r1, r0 | |
| 115 | synco | |
| 116 | wait_timer TIMER_D | |
| 117 | ||
| 118 | write32 DBCMDCNT_A, DBCMDCNT_D0 | |
| 119 | write32 DBCMDCNT_A, DBCMDCNT_D1 | |
| 120 | write32 DBPDCNT0_A, DBPDCNT0_D1 | |
| 121 | write32 DBRFPDN0_A, DBRFPDN0_D | |
| 122 | ||
| 123 | wait_timer TIMER_D | |
| 124 | ||
| 125 | write32 CCR_A, CCR_D | |
| 126 | ||
| 127 | stc sr, r0 | |
| 128 | mov.l SR_MASK_D, r1 | |
| 129 | and r1, r0 | |
| 130 | ldc r0, sr | |
| 131 | ||
| 132 | rts | |
| 133 | ||
| 134 | .align 2 | |
| 135 | ||
| 136 | PVDR_A: .long PVDR | |
| 137 | PVDR_D: .long 0x00000001 | |
| 138 | JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR | |
| 139 | TIMER_D: .long 64 | |
| 140 | RWTCSR_A: .long RWTCSR | |
| 141 | RWTCSR_D: .long 0x0000A507 | |
| 142 | MMUCR_A: .long MMUCR | |
| 143 | MMUCR_D: .long 0x00000004 | |
| 144 | PLLCR_A: .long PLLCR | |
| 145 | PLLCR_D: .long 0x00004000 | |
| 146 | FRQCRA_A: .long FRQCRA | |
| 147 | FRQCRA_D: .long 0x8E003508 | |
| 148 | FRQCRB_A: .long FRQCRB | |
| 149 | FRQCRB_D: .long 0x0 | |
| 150 | MMSELR_A: .long MMSELR | |
| 151 | MMSELR_D: .long 0xA5A50000 | |
| 152 | CMNCR_A: .long CMNCR | |
| 153 | CMNCR_D: .long 0x00000013 | |
| 154 | CS0BCR_A: .long CS0BCR | |
| 155 | CS0BCR_D: .long 0x11110400 | |
| 156 | CS0WCR_A: .long CS0WCR | |
| 157 | CS0WCR_D: .long 0x00000440 | |
| 158 | DBPDCNT0_A: .long DBPDCNT0 | |
| 159 | DBPDCNT0_D0: .long 0x00000181 | |
| 160 | DBPDCNT0_D1: .long 0x00000080 | |
| 161 | DBCONF_A: .long DBCONF | |
| 162 | DBCONF_D: .long 0x015B0002 | |
| 163 | DBTR0_A: .long DBTR0 | |
| 164 | DBTR0_D: .long 0x03061502 | |
| 165 | DBTR1_A: .long DBTR1 | |
| 166 | DBTR1_D: .long 0x02020102 | |
| 167 | DBTR2_A: .long DBTR2 | |
| 168 | DBTR2_D: .long 0x01090305 | |
| 169 | DBTR3_A: .long DBTR3 | |
| 170 | DBTR3_D: .long 0x00000002 | |
| 171 | DBKIND_A: .long DBKIND | |
| 172 | DBKIND_D: .long 0x00000005 | |
| 173 | DBCKECNT_A: .long DBCKECNT | |
| 174 | DBCKECNT_D: .long 0x00000001 | |
| 175 | DBCMDCNT_A: .long DBCMDCNT | |
| 176 | DBCMDCNT_D0:.long 0x2 | |
| 177 | DBCMDCNT_D1:.long 0x4 | |
| 178 | DBMRCNT_A: .long DBMRCNT | |
| 179 | DBMRCNT_D0: .long 0x00020000 | |
| 180 | DBMRCNT_D1: .long 0x00030000 | |
| 181 | DBMRCNT_D2: .long 0x00010040 | |
| 182 | DBMRCNT_D3: .long 0x00000532 | |
| 183 | DBMRCNT_D4: .long 0x00000432 | |
| 184 | DBMRCNT_D5: .long 0x000103C0 | |
| 185 | DBMRCNT_D6: .long 0x00010040 | |
| 186 | DBEN_A: .long DBEN | |
| 187 | DBEN_D: .long 0x01 | |
| 188 | DBRFPDN0_A: .long DBRFPDN0 | |
| 189 | DBRFPDN1_A: .long DBRFPDN1 | |
| 190 | DBRFPDN2_A: .long DBRFPDN2 | |
| 191 | DBRFPDN0_D: .long 0x00010000 | |
| 192 | DBRFPDN1_D: .long 0x00000613 | |
| 193 | DBRFPDN2_D: .long 0x238C003A | |
| 194 | SDRAM_A: .long 0xa8000000 | |
| 195 | DUMMY_A: .long 0x0c400000 | |
| 196 | CCR_A: .long CCR | |
| 197 | CCR_D: .long 0x0000090B | |
| 198 | SR_MASK_D: .long 0xEFFFFF0F |