[people/ms/u-boot.git] / board / renesas / r7780mp / lowlevel_init.S

/*
 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
 *
 * u-boot/board/r7780mp/lowlevel_init.S
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>

/*
 * Board specific low level init code, called _very_ early in the
 * startup sequence. Relocation to SDRAM has not happened yet, no
 * stack is available, bss section has not been initialised, etc.
 *
 * (Note: As no stack is available, no subroutines can be called...).
 */

	.global	lowlevel_init

	.text
	.align	2

lowlevel_init:

	write32	CCR_A, CCR_D		/* Address of Cache Control Register */
					/* Instruction Cache Invalidate */

	write32	FRQCR_A, FRQCR_D	/* Frequency control register */

	/* pin_multi_setting */
	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR1

	write32	BBG_PMSR1_A, BBG_PMSR1_D

	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR2

	write32	BBG_PMSR2_A, BBG_PMSR2_D

	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR3

	write32	BBG_PMSR3_A, BBG_PMSR3_D

	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR4

	write32	BBG_PMSR4_A, BBG_PMSR4_D

	write32	BBG_PMMR_A, BBG_PMMR_D_PMSRG

	write32	BBG_PMSRG_A, BBG_PMSRG_D

	/* cpg_setting */
	write32	FRQCR_A, FRQCR_D

	write32	DLLCSR_A, DLLCSR_D

	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

	/* wait 200us */
	mov.l	REPEAT0_R3, r3
	mov	#0, r2
repeat0:
	add	#1, r2
	cmp/hs	r3, r2
	bf	repeat0
	nop

	/* bsc_setting */
	write32	MMSELR_A, MMSELR_D

	write32	BCR_A, BCR_D

	write32	CS0BCR_A, CS0BCR_D

	write32	CS1BCR_A, CS1BCR_D

	write32	CS2BCR_A, CS2BCR_D

	write32	CS4BCR_A, CS4BCR_D

	write32	CS5BCR_A, CS5BCR_D

	write32	CS6BCR_A, CS6BCR_D

	write32	CS0WCR_A, CS0WCR_D

	write32	CS1WCR_A, CS1WCR_D

	write32	CS2WCR_A, CS2WCR_D

	write32	CS4WCR_A, CS4WCR_D

	write32	CS5WCR_A, CS5WCR_D

	write32	CS6WCR_A, CS6WCR_D

	write32	CS5PCR_A, CS5PCR_D

	write32	CS6PCR_A, CS6PCR_D

	/* ddr_setting */
	/* wait 200us */
	mov.l	REPEAT0_R3, r3
	mov	#0, r2
repeat1:
	add	#1, r2
	cmp/hs	r3, r2
	bf	repeat1
	nop

	mov.l	MIM_U_A, r0
	mov.l	MIM_U_D, r1
	synco
	mov.l	r1, @r0
	synco

	mov.l	MIM_L_A, r0
	mov.l	MIM_L_D0, r1
	synco
	mov.l	r1, @r0
	synco

	mov.l	STR_L_A, r0
	mov.l	STR_L_D, r1
	synco
	mov.l	r1, @r0
	synco

	mov.l	SDR_L_A, r0
	mov.l	SDR_L_D, r1
	synco
	mov.l	r1, @r0
	synco

	nop
	nop
	nop
	nop

	mov.l	SCR_L_A, r0
	mov.l	SCR_L_D0, r1
	synco
	mov.l	r1, @r0
	synco

	mov.l	SCR_L_A, r0
	mov.l	SCR_L_D1, r1
	synco
	mov.l	r1, @r0
	synco

	nop
	nop
	nop

	mov.l	EMRS_A, r0
	mov.l	EMRS_D, r1
	synco
	mov.l	r1, @r0
	synco

	nop
	nop
	nop

	mov.l	MRS1_A, r0
	mov.l	MRS1_D, r1
	synco
	mov.l	r1, @r0
	synco

	nop
	nop
	nop

	mov.l	SCR_L_A, r0
	mov.l	SCR_L_D2, r1
	synco
	mov.l	r1, @r0
	synco

	nop
	nop
	nop

	mov.l	SCR_L_A, r0
	mov.l	SCR_L_D3, r1
	synco
	mov.l	r1, @r0
	synco

	nop
	nop
	nop

	mov.l	SCR_L_A, r0
	mov.l	SCR_L_D4, r1
	synco
	mov.l	r1, @r0
	synco

	nop
	nop
	nop

	mov.l	MRS2_A, r0
	mov.l	MRS2_D, r1
	synco
	mov.l	r1, @r0
	synco

	nop
	nop
	nop

	mov.l	SCR_L_A, r0
	mov.l	SCR_L_D5, r1
	synco
	mov.l	r1, @r0
	synco

	/* wait 200us */
	mov.l	REPEAT0_R1, r3
	mov	#0, r2
repeat2:
	add	#1, r2
	cmp/hs	r3, r2
	bf	repeat2

	synco

	mov.l	MIM_L_A, r0
	mov.l	MIM_L_D1, r1
	synco
	mov.l	r1, @r0
	synco

	rts
	nop
	.align	4

RWTCSR_D_1:		.word	0xA507
RWTCSR_D_2:		.word	0xA507
RWTCNT_D:		.word	0x5A00
	.align	2

BBG_PMMR_A:		.long	0xFF800010
BBG_PMSR1_A:		.long	0xFF800014
BBG_PMSR2_A:		.long	0xFF800018
BBG_PMSR3_A:		.long	0xFF80001C
BBG_PMSR4_A:		.long	0xFF800020
BBG_PMSRG_A:		.long	0xFF800024

BBG_PMMR_D_PMSR1:	.long	0xffffbffd
BBG_PMSR1_D:		.long	0x00004002
BBG_PMMR_D_PMSR2:	.long	0xfc21a7ff
BBG_PMSR2_D:		.long	0x03de5800
BBG_PMMR_D_PMSR3:	.long	0xfffffff8
BBG_PMSR3_D:		.long	0x00000007
BBG_PMMR_D_PMSR4:	.long	0xdffdfff9
BBG_PMSR4_D:		.long	0x20020006
BBG_PMMR_D_PMSRG:	.long	0xffffffff
BBG_PMSRG_D:		.long	0x00000000

FRQCR_A:		.long	FRQCR
DLLCSR_A:		.long	0xffc40010
FRQCR_D:		.long	0x40233035
DLLCSR_D:		.long	0x00000000

/* for DDR-SDRAM */
MIM_U_A:		.long	MIM_1
MIM_L_A:		.long	MIM_2
SCR_U_A:		.long	SCR_1
SCR_L_A:		.long	SCR_2
STR_U_A:		.long	STR_1
STR_L_A:		.long	STR_2
SDR_U_A:		.long	SDR_1
SDR_L_A:		.long	SDR_2

EMRS_A:			.long	0xFEC02000
MRS1_A:			.long	0xFEC00B08
MRS2_A:			.long	0xFEC00308

MIM_U_D:		.long	0x00004000
MIM_L_D0:		.long	0x03e80009
MIM_L_D1:		.long	0x03e80209
SCR_L_D0:		.long	0x3
SCR_L_D1:		.long	0x2
SCR_L_D2:		.long	0x2
SCR_L_D3:		.long	0x4
SCR_L_D4:		.long	0x4
SCR_L_D5:		.long	0x0
STR_L_D:		.long	0x000f0000
SDR_L_D:		.long	0x00000400
EMRS_D:			.long	0x0
MRS1_D:			.long	0x0
MRS2_D:			.long	0x0

/* Cache Controller */
CCR_A:			.long	CCR
MMUCR_A:		.long	MMUCR
RWTCNT_A:		.long	WTCNT

CCR_D:			.long	0x0000090b
CCR_D_2:		.long	0x00000103
MMUCR_D:		.long	0x00000004
MSTPCR0_D:		.long	0x00001001
MSTPCR2_D:		.long	0xffffffff

/* local Bus State Controller */
MMSELR_A:		.long	MMSELR
BCR_A:			.long	BCR
CS0BCR_A:		.long	CS0BCR
CS1BCR_A:		.long	CS1BCR
CS2BCR_A:		.long	CS2BCR
CS4BCR_A:		.long	CS4BCR
CS5BCR_A:		.long	CS5BCR
CS6BCR_A:		.long	CS6BCR
CS0WCR_A:		.long	CS0WCR
CS1WCR_A:		.long	CS1WCR
CS2WCR_A:		.long	CS2WCR
CS4WCR_A:		.long	CS4WCR
CS5WCR_A:		.long	CS5WCR
CS6WCR_A:		.long	CS6WCR
CS5PCR_A:		.long	CS5PCR
CS6PCR_A:		.long	CS6PCR

MMSELR_D:		.long	0xA5A50003
BCR_D:			.long	0x00000000
CS0BCR_D:		.long	0x77777770
CS1BCR_D:		.long	0x77777670
CS2BCR_D:		.long	0x77777770
CS4BCR_D:		.long	0x77777770
CS5BCR_D:		.long	0x77777670
CS6BCR_D:		.long	0x77777770
CS0WCR_D:		.long	0x00020006
CS1WCR_D:		.long	0x00232304
CS2WCR_D:		.long	0x7777770F
CS4WCR_D:		.long	0x7777770F
CS5WCR_D:		.long	0x00101006
CS6WCR_D:		.long	0x77777703
CS5PCR_D:		.long	0x77000000
CS6PCR_D:		.long	0x77000000

REPEAT0_R3:		.long	0x00002000
REPEAT0_R1:		.long	0x0000200
Commit	Line	Data
c133c1fb YG	1	/*
	2	* Copyright (C) 2007,2008 Nobuhiro Iwamatsu
	3	*
	4	* u-boot/board/r7780mp/lowlevel_init.S
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
c133c1fb YG	7	*/
	8
	9	#include <config.h>
	10	#include <version.h>
	11	#include <asm/processor.h>
f7e78f3b	12	#include <asm/macro.h>
c133c1fb YG	13
c133c1fb YG	14	/*
e4430779 JCPV	15	* Board specific low level init code, called _very_ early in the
	16	* startup sequence. Relocation to SDRAM has not happened yet, no
	17	* stack is available, bss section has not been initialised, etc.
c133c1fb	18	*
e4430779	19	* (Note: As no stack is available, no subroutines can be called...).
c133c1fb YG	20	*/
	21
	22	.global lowlevel_init
	23
	24	.text
	25	.align 2
	26
	27	lowlevel_init:
	28
f7e78f3b JCPV	29	write32 CCR_A, CCR_D /* Address of Cache Control Register */
f7e78f3b JCPV	30	/* Instruction Cache Invalidate */
c133c1fb	31
f7e78f3b	32	write32 FRQCR_A, FRQCR_D /* Frequency control register */
c133c1fb YG	33
c133c1fb YG	34	/* pin_multi_setting */
f7e78f3b	35	write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
c133c1fb	36
f7e78f3b	37	write32 BBG_PMSR1_A, BBG_PMSR1_D
c133c1fb	38
f7e78f3b	39	write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
c133c1fb	40
f7e78f3b	41	write32 BBG_PMSR2_A, BBG_PMSR2_D
c133c1fb	42
f7e78f3b	43	write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
c133c1fb	44
f7e78f3b	45	write32 BBG_PMSR3_A, BBG_PMSR3_D
c133c1fb	46
f7e78f3b	47	write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
c133c1fb	48
f7e78f3b	49	write32 BBG_PMSR4_A, BBG_PMSR4_D
c133c1fb	50
f7e78f3b	51	write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
c133c1fb	52
f7e78f3b	53	write32 BBG_PMSRG_A, BBG_PMSRG_D
c133c1fb YG	54
c133c1fb YG	55	/* cpg_setting */
f7e78f3b	56	write32 FRQCR_A, FRQCR_D
c133c1fb	57
f7e78f3b	58	write32 DLLCSR_A, DLLCSR_D
c133c1fb YG	59
	60	nop
	61	nop
	62	nop
	63	nop
	64	nop
	65	nop
	66	nop
	67	nop
	68	nop
	69	nop
	70
	71	/* wait 200us */
e4430779 JCPV	72	mov.l REPEAT0_R3, r3
e4430779 JCPV	73	mov #0, r2
c133c1fb	74	repeat0:
e4430779 JCPV	75	add #1, r2
	76	cmp/hs r3, r2
	77	bf repeat0
c133c1fb YG	78	nop
	79
	80	/* bsc_setting */
f7e78f3b	81	write32 MMSELR_A, MMSELR_D
c133c1fb	82
f7e78f3b	83	write32 BCR_A, BCR_D
c133c1fb	84
f7e78f3b	85	write32 CS0BCR_A, CS0BCR_D
c133c1fb	86
f7e78f3b	87	write32 CS1BCR_A, CS1BCR_D
c133c1fb	88
f7e78f3b	89	write32 CS2BCR_A, CS2BCR_D
c133c1fb	90
f7e78f3b	91	write32 CS4BCR_A, CS4BCR_D
c133c1fb	92
f7e78f3b	93	write32 CS5BCR_A, CS5BCR_D
c133c1fb	94
f7e78f3b	95	write32 CS6BCR_A, CS6BCR_D
c133c1fb	96
f7e78f3b	97	write32 CS0WCR_A, CS0WCR_D
c133c1fb	98
f7e78f3b	99	write32 CS1WCR_A, CS1WCR_D
c133c1fb	100
f7e78f3b	101	write32 CS2WCR_A, CS2WCR_D
c133c1fb	102
f7e78f3b	103	write32 CS4WCR_A, CS4WCR_D
c133c1fb	104
f7e78f3b	105	write32 CS5WCR_A, CS5WCR_D
c133c1fb	106
f7e78f3b	107	write32 CS6WCR_A, CS6WCR_D
c133c1fb	108
f7e78f3b	109	write32 CS5PCR_A, CS5PCR_D
c133c1fb	110
f7e78f3b	111	write32 CS6PCR_A, CS6PCR_D
c133c1fb YG	112
	113	/* ddr_setting */
	114	/* wait 200us */
e4430779 JCPV	115	mov.l REPEAT0_R3, r3
e4430779 JCPV	116	mov #0, r2
c133c1fb	117	repeat1:
e4430779 JCPV	118	add #1, r2
	119	cmp/hs r3, r2
	120	bf repeat1
c133c1fb YG	121	nop
c133c1fb YG	122
e4430779 JCPV	123	mov.l MIM_U_A, r0
e4430779 JCPV	124	mov.l MIM_U_D, r1
c133c1fb	125	synco
e4430779	126	mov.l r1, @r0
c133c1fb YG	127	synco
c133c1fb YG	128
e4430779 JCPV	129	mov.l MIM_L_A, r0
e4430779 JCPV	130	mov.l MIM_L_D0, r1
c133c1fb	131	synco
e4430779	132	mov.l r1, @r0
c133c1fb YG	133	synco
c133c1fb YG	134
e4430779 JCPV	135	mov.l STR_L_A, r0
e4430779 JCPV	136	mov.l STR_L_D, r1
c133c1fb	137	synco
e4430779	138	mov.l r1, @r0
c133c1fb YG	139	synco
c133c1fb YG	140
e4430779 JCPV	141	mov.l SDR_L_A, r0
e4430779 JCPV	142	mov.l SDR_L_D, r1
c133c1fb	143	synco
e4430779	144	mov.l r1, @r0
c133c1fb YG	145	synco
	146
	147	nop
	148	nop
	149	nop
	150	nop
	151
e4430779 JCPV	152	mov.l SCR_L_A, r0
e4430779 JCPV	153	mov.l SCR_L_D0, r1
c133c1fb	154	synco
e4430779	155	mov.l r1, @r0
c133c1fb YG	156	synco
c133c1fb YG	157
e4430779 JCPV	158	mov.l SCR_L_A, r0
e4430779 JCPV	159	mov.l SCR_L_D1, r1
c133c1fb	160	synco
e4430779	161	mov.l r1, @r0
c133c1fb YG	162	synco
	163
	164	nop
	165	nop
	166	nop
	167
e4430779 JCPV	168	mov.l EMRS_A, r0
e4430779 JCPV	169	mov.l EMRS_D, r1
c133c1fb	170	synco
e4430779	171	mov.l r1, @r0
c133c1fb YG	172	synco
	173
	174	nop
	175	nop
	176	nop
	177
e4430779 JCPV	178	mov.l MRS1_A, r0
e4430779 JCPV	179	mov.l MRS1_D, r1
c133c1fb	180	synco
e4430779	181	mov.l r1, @r0
c133c1fb YG	182	synco
	183
	184	nop
	185	nop
	186	nop
	187
e4430779 JCPV	188	mov.l SCR_L_A, r0
e4430779 JCPV	189	mov.l SCR_L_D2, r1
c133c1fb	190	synco
e4430779	191	mov.l r1, @r0
c133c1fb YG	192	synco
	193
	194	nop
	195	nop
	196	nop
	197
e4430779 JCPV	198	mov.l SCR_L_A, r0
e4430779 JCPV	199	mov.l SCR_L_D3, r1
c133c1fb	200	synco
e4430779	201	mov.l r1, @r0
c133c1fb YG	202	synco
	203
	204	nop
	205	nop
	206	nop
	207
e4430779 JCPV	208	mov.l SCR_L_A, r0
e4430779 JCPV	209	mov.l SCR_L_D4, r1
c133c1fb	210	synco
e4430779	211	mov.l r1, @r0
c133c1fb YG	212	synco
	213
	214	nop
	215	nop
	216	nop
	217
e4430779 JCPV	218	mov.l MRS2_A, r0
e4430779 JCPV	219	mov.l MRS2_D, r1
c133c1fb	220	synco
e4430779	221	mov.l r1, @r0
c133c1fb YG	222	synco
	223
	224	nop
	225	nop
	226	nop
	227
e4430779 JCPV	228	mov.l SCR_L_A, r0
e4430779 JCPV	229	mov.l SCR_L_D5, r1
c133c1fb	230	synco
e4430779	231	mov.l r1, @r0
c133c1fb YG	232	synco
	233
	234	/* wait 200us */
e4430779 JCPV	235	mov.l REPEAT0_R1, r3
e4430779 JCPV	236	mov #0, r2
c133c1fb	237	repeat2:
e4430779 JCPV	238	add #1, r2
	239	cmp/hs r3, r2
	240	bf repeat2
c133c1fb YG	241
	242	synco
	243
e4430779 JCPV	244	mov.l MIM_L_A, r0
e4430779 JCPV	245	mov.l MIM_L_D1, r1
c133c1fb	246	synco
e4430779	247	mov.l r1, @r0
c133c1fb YG	248	synco
	249
	250	rts
	251	nop
	252	.align 4
	253
e4430779 JCPV	254	RWTCSR_D_1: .word 0xA507
	255	RWTCSR_D_2: .word 0xA507
	256	RWTCNT_D: .word 0x5A00
b5d10a13	257	.align 2
c133c1fb	258
e4430779 JCPV	259	BBG_PMMR_A: .long 0xFF800010
	260	BBG_PMSR1_A: .long 0xFF800014
	261	BBG_PMSR2_A: .long 0xFF800018
	262	BBG_PMSR3_A: .long 0xFF80001C
	263	BBG_PMSR4_A: .long 0xFF800020
	264	BBG_PMSRG_A: .long 0xFF800024
	265
	266	BBG_PMMR_D_PMSR1: .long 0xffffbffd
	267	BBG_PMSR1_D: .long 0x00004002
	268	BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
	269	BBG_PMSR2_D: .long 0x03de5800
	270	BBG_PMMR_D_PMSR3: .long 0xfffffff8
	271	BBG_PMSR3_D: .long 0x00000007
	272	BBG_PMMR_D_PMSR4: .long 0xdffdfff9
	273	BBG_PMSR4_D: .long 0x20020006
	274	BBG_PMMR_D_PMSRG: .long 0xffffffff
	275	BBG_PMSRG_D: .long 0x00000000
	276
	277	FRQCR_A: .long FRQCR
	278	DLLCSR_A: .long 0xffc40010
	279	FRQCR_D: .long 0x40233035
	280	DLLCSR_D: .long 0x00000000
c133c1fb YG	281
c133c1fb YG	282	/* for DDR-SDRAM */
e4430779 JCPV	283	MIM_U_A: .long MIM_1
	284	MIM_L_A: .long MIM_2
	285	SCR_U_A: .long SCR_1
	286	SCR_L_A: .long SCR_2
	287	STR_U_A: .long STR_1
	288	STR_L_A: .long STR_2
	289	SDR_U_A: .long SDR_1
	290	SDR_L_A: .long SDR_2
	291
	292	EMRS_A: .long 0xFEC02000
	293	MRS1_A: .long 0xFEC00B08
	294	MRS2_A: .long 0xFEC00308
	295
	296	MIM_U_D: .long 0x00004000
	297	MIM_L_D0: .long 0x03e80009
	298	MIM_L_D1: .long 0x03e80209
	299	SCR_L_D0: .long 0x3
	300	SCR_L_D1: .long 0x2
	301	SCR_L_D2: .long 0x2
	302	SCR_L_D3: .long 0x4
	303	SCR_L_D4: .long 0x4
	304	SCR_L_D5: .long 0x0
	305	STR_L_D: .long 0x000f0000
	306	SDR_L_D: .long 0x00000400
	307	EMRS_D: .long 0x0
	308	MRS1_D: .long 0x0
	309	MRS2_D: .long 0x0
c133c1fb YG	310
c133c1fb YG	311	/* Cache Controller */
e4430779 JCPV	312	CCR_A: .long CCR
	313	MMUCR_A: .long MMUCR
	314	RWTCNT_A: .long WTCNT
c133c1fb	315
e4430779 JCPV	316	CCR_D: .long 0x0000090b
	317	CCR_D_2: .long 0x00000103
	318	MMUCR_D: .long 0x00000004
	319	MSTPCR0_D: .long 0x00001001
	320	MSTPCR2_D: .long 0xffffffff
c133c1fb YG	321
c133c1fb YG	322	/* local Bus State Controller */
e4430779 JCPV	323	MMSELR_A: .long MMSELR
	324	BCR_A: .long BCR
	325	CS0BCR_A: .long CS0BCR
	326	CS1BCR_A: .long CS1BCR
	327	CS2BCR_A: .long CS2BCR
	328	CS4BCR_A: .long CS4BCR
	329	CS5BCR_A: .long CS5BCR
	330	CS6BCR_A: .long CS6BCR
	331	CS0WCR_A: .long CS0WCR
	332	CS1WCR_A: .long CS1WCR
	333	CS2WCR_A: .long CS2WCR
	334	CS4WCR_A: .long CS4WCR
	335	CS5WCR_A: .long CS5WCR
	336	CS6WCR_A: .long CS6WCR
	337	CS5PCR_A: .long CS5PCR
	338	CS6PCR_A: .long CS6PCR
c133c1fb YG	339
	340	MMSELR_D: .long 0xA5A50003
	341	BCR_D: .long 0x00000000
	342	CS0BCR_D: .long 0x77777770
	343	CS1BCR_D: .long 0x77777670
	344	CS2BCR_D: .long 0x77777770
	345	CS4BCR_D: .long 0x77777770
	346	CS5BCR_D: .long 0x77777670
	347	CS6BCR_D: .long 0x77777770
	348	CS0WCR_D: .long 0x00020006
	349	CS1WCR_D: .long 0x00232304
	350	CS2WCR_D: .long 0x7777770F
	351	CS4WCR_D: .long 0x7777770F
	352	CS5WCR_D: .long 0x00101006
	353	CS6WCR_D: .long 0x77777703
	354	CS5PCR_D: .long 0x77000000
	355	CS6PCR_D: .long 0x77000000
	356
e4430779 JCPV	357	REPEAT0_R3: .long 0x00002000
e4430779 JCPV	358	REPEAT0_R1: .long 0x0000200