[people/ms/u-boot.git] / board / renesas / salvator-x / salvator-x.c

/*
 * board/renesas/salvator-x/salvator-x.c
 *     This file is Salvator-X/Salvator-XS board support.
 *
 * Copyright (C) 2015-2017 Renesas Electronics Corporation
 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>

DECLARE_GLOBAL_DATA_PTR;

#define CPGWPCR	0xE6150904
#define CPGWPR  0xE615090C

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	writel(0xA5A50000, CPGWPCR);
	writel(0xFFFFFFFF, CPGWPR);
}

#define GSX_MSTP112		BIT(12)	/* 3DG */
#define TMU0_MSTP125		BIT(25)	/* secure */
#define TMU1_MSTP124		BIT(24)	/* non-secure */
#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
#define DVFS_MSTP926		BIT(26)
#define HSUSB_MSTP704		BIT(4)	/* HSUSB */

int board_early_init_f(void)
{
	/* TMU0,1 */		/* which use ? */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);

#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	/* DVFS for reset */
	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
#endif
	return 0;
}

/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define	SYSC_PWRSR2	0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define	SYSC_PWRONCR2	0xE618010C

/* HSUSB block registers */
#define HSUSB_REG_LPSTS			0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
#define HSUSB_REG_UGCTRL2		0xE6590184
#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10

int board_init(void)
{
	u32 cpu_type = rmobile_get_cpu_type();

	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;

	if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
		/* GSX: force power and clock supply */
		writel(0x0000001F, SYSC_PWRONCR2);
		while (readl(SYSC_PWRSR2) != 0x000003E0)
			mdelay(20);

		mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
	}

	/* USB1 pull-up */
	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);

	/* Configure the HSUSB block */
	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
	/* Choice USB0SEL */
	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
	/* low power status */
	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_memory_size() != 0)
		return -EINVAL;

	return 0;
}

int dram_init_banksize(void)
{
	fdtdec_setup_memory_banksize();

	return 0;
}

#define RST_BASE	0xE6160000
#define RST_CA57RESCNT	(RST_BASE + 0x40)
#define RST_CA53RESCNT	(RST_BASE + 0x44)
#define RST_RSTOUTCR	(RST_BASE + 0x58)
#define RST_CODE	0xA5A5000F

void reset_cpu(ulong addr)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
#else
	/* only CA57 ? */
	writel(RST_CODE, RST_CA57RESCNT);
#endif
}
Commit	Line	Data
e525d34b NI	1	/*
e525d34b NI	2	* board/renesas/salvator-x/salvator-x.c
adf3057f	3	* This file is Salvator-X/Salvator-XS board support.
e525d34b	4	*
50fb0c45	5	* Copyright (C) 2015-2017 Renesas Electronics Corporation
e525d34b NI	6	* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
	12	#include <malloc.h>
	13	#include <netdev.h>
	14	#include <dm.h>
	15	#include <dm/platform_data/serial_sh.h>
	16	#include <asm/processor.h>
	17	#include <asm/mach-types.h>
	18	#include <asm/io.h>
1221ce45	19	#include <linux/errno.h>
e525d34b NI	20	#include <asm/arch/sys_proto.h>
	21	#include <asm/gpio.h>
	22	#include <asm/arch/gpio.h>
	23	#include <asm/arch/rmobile.h>
	24	#include <asm/arch/rcar-mstp.h>
50fb0c45	25	#include <asm/arch/sh_sdhi.h>
e525d34b NI	26	#include <i2c.h>
	27	#include <mmc.h>
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	#define CPGWPCR 0xE6150904
	32	#define CPGWPR 0xE615090C
	33
	34	#define CLK2MHZ(clk) (clk / 1000 / 1000)
	35	void s_init(void)
	36	{
	37	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	38	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	39
	40	/* Watchdog init */
	41	writel(0xA5A5A500, &rwdt->rwtcsra);
	42	writel(0xA5A5A500, &swdt->swtcsra);
	43
	44	writel(0xA5A50000, CPGWPCR);
	45	writel(0xFFFFFFFF, CPGWPR);
	46	}
	47
ae7a74a6 MV	48	#define GSX_MSTP112 BIT(12) /* 3DG */
	49	#define TMU0_MSTP125 BIT(25) /* secure */
	50	#define TMU1_MSTP124 BIT(24) /* non-secure */
	51	#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
fe2e8ff9	52	#define DVFS_MSTP926 BIT(26)
afb19d65	53	#define HSUSB_MSTP704 BIT(4) /* HSUSB */
50fb0c45	54
e525d34b NI	55	int board_early_init_f(void)
	56	{
	57	/* TMU0,1 / / which use ? */
	58	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 \| TMU1_MSTP124);
e525d34b	59
fe2e8ff9 MV	60	#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	61	/* DVFS for reset */
	62	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
	63	#endif
e525d34b NI	64	return 0;
	65	}
	66
	67	/* SYSC */
	68	/* R/- 32 Power status register 2(3DG) */
	69	#define SYSC_PWRSR2 0xE6180100
	70	/* -/W 32 Power resume control register 2 (3DG) */
	71	#define SYSC_PWRONCR2 0xE618010C
	72
afb19d65 MV	73	/* HSUSB block registers */
	74	#define HSUSB_REG_LPSTS 0xE6590102
	75	#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
	76	#define HSUSB_REG_UGCTRL2 0xE6590184
	77	#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
	78	#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
	79
e525d34b NI	80	int board_init(void)
e525d34b NI	81	{
bee22aa8 MV	82	u32 cpu_type = rmobile_get_cpu_type();
bee22aa8 MV	83
e525d34b NI	84	/* adress of boot parameters */
	85	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
	86
bee22aa8 MV	87	if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) {
	88	/* GSX: force power and clock supply */
	89	writel(0x0000001F, SYSC_PWRONCR2);
	90	while (readl(SYSC_PWRSR2) != 0x000003E0)
	91	mdelay(20);
e525d34b	92
bee22aa8 MV	93	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
bee22aa8 MV	94	}
e525d34b	95
d1018f5f MV	96	/* USB1 pull-up */
	97	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC \| PUEN_USB1_PWEN);
	98
afb19d65 MV	99	/* Configure the HSUSB block */
	100	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
	101	/* Choice USB0SEL */
	102	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
	103	HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
	104	/* low power status */
	105	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
	106
ddb39a07	107	return 0;
50fb0c45	108	}
50fb0c45	109
e525d34b NI	110	int dram_init(void)
e525d34b NI	111	{
aee24b59 MV	112	if (fdtdec_setup_memory_size() != 0)
aee24b59 MV	113	return -EINVAL;
8f284e66 MV	114
	115	return 0;
	116	}
e525d34b	117
8f284e66 MV	118	int dram_init_banksize(void)
8f284e66 MV	119	{
aee24b59 MV	120	fdtdec_setup_memory_banksize();
aee24b59 MV	121
e525d34b NI	122	return 0;
	123	}
	124
e525d34b NI	125	#define RST_BASE 0xE6160000
	126	#define RST_CA57RESCNT (RST_BASE + 0x40)
	127	#define RST_CA53RESCNT (RST_BASE + 0x44)
	128	#define RST_RSTOUTCR (RST_BASE + 0x58)
	129	#define RST_CODE 0xA5A5000F
	130
	131	void reset_cpu(ulong addr)
	132	{
fe2e8ff9 MV	133	#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	134	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
	135	#else
e525d34b NI	136	/* only CA57 ? */
e525d34b NI	137	writel(RST_CODE, RST_CA57RESCNT);
fe2e8ff9	138	#endif
e525d34b	139	}