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e525d34b NI |
1 | /* |
2 | * board/renesas/salvator-x/salvator-x.c | |
adf3057f | 3 | * This file is Salvator-X/Salvator-XS board support. |
e525d34b | 4 | * |
50fb0c45 | 5 | * Copyright (C) 2015-2017 Renesas Electronics Corporation |
e525d34b NI |
6 | * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <malloc.h> | |
13 | #include <netdev.h> | |
14 | #include <dm.h> | |
15 | #include <dm/platform_data/serial_sh.h> | |
16 | #include <asm/processor.h> | |
17 | #include <asm/mach-types.h> | |
18 | #include <asm/io.h> | |
1221ce45 | 19 | #include <linux/errno.h> |
e525d34b NI |
20 | #include <asm/arch/sys_proto.h> |
21 | #include <asm/gpio.h> | |
22 | #include <asm/arch/gpio.h> | |
23 | #include <asm/arch/rmobile.h> | |
24 | #include <asm/arch/rcar-mstp.h> | |
50fb0c45 | 25 | #include <asm/arch/sh_sdhi.h> |
e525d34b NI |
26 | #include <i2c.h> |
27 | #include <mmc.h> | |
28 | ||
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | #define CPGWPCR 0xE6150904 | |
32 | #define CPGWPR 0xE615090C | |
33 | ||
34 | #define CLK2MHZ(clk) (clk / 1000 / 1000) | |
35 | void s_init(void) | |
36 | { | |
37 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; | |
38 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; | |
39 | ||
40 | /* Watchdog init */ | |
41 | writel(0xA5A5A500, &rwdt->rwtcsra); | |
42 | writel(0xA5A5A500, &swdt->swtcsra); | |
43 | ||
44 | writel(0xA5A50000, CPGWPCR); | |
45 | writel(0xFFFFFFFF, CPGWPR); | |
46 | } | |
47 | ||
ae7a74a6 MV |
48 | #define GSX_MSTP112 BIT(12) /* 3DG */ |
49 | #define TMU0_MSTP125 BIT(25) /* secure */ | |
50 | #define TMU1_MSTP124 BIT(24) /* non-secure */ | |
51 | #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ | |
fe2e8ff9 | 52 | #define DVFS_MSTP926 BIT(26) |
afb19d65 | 53 | #define HSUSB_MSTP704 BIT(4) /* HSUSB */ |
50fb0c45 | 54 | |
e525d34b NI |
55 | int board_early_init_f(void) |
56 | { | |
57 | /* TMU0,1 */ /* which use ? */ | |
58 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); | |
e525d34b | 59 | |
fe2e8ff9 MV |
60 | #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
61 | /* DVFS for reset */ | |
62 | mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); | |
63 | #endif | |
e525d34b NI |
64 | return 0; |
65 | } | |
66 | ||
67 | /* SYSC */ | |
68 | /* R/- 32 Power status register 2(3DG) */ | |
69 | #define SYSC_PWRSR2 0xE6180100 | |
70 | /* -/W 32 Power resume control register 2 (3DG) */ | |
71 | #define SYSC_PWRONCR2 0xE618010C | |
72 | ||
afb19d65 MV |
73 | /* HSUSB block registers */ |
74 | #define HSUSB_REG_LPSTS 0xE6590102 | |
75 | #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) | |
76 | #define HSUSB_REG_UGCTRL2 0xE6590184 | |
77 | #define HSUSB_REG_UGCTRL2_USB0SEL 0x30 | |
78 | #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 | |
79 | ||
e525d34b NI |
80 | int board_init(void) |
81 | { | |
82 | /* adress of boot parameters */ | |
83 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; | |
84 | ||
793afcde | 85 | #ifdef CONFIG_SH_GPIO_PFC |
e525d34b | 86 | /* Init PFC controller */ |
adf3057f | 87 | #if defined(CONFIG_R8A7795) |
e525d34b | 88 | r8a7795_pinmux_init(); |
adf3057f MV |
89 | #elif defined(CONFIG_R8A7796) |
90 | r8a7796_pinmux_init(); | |
91 | #endif | |
793afcde | 92 | #endif |
e525d34b | 93 | |
adf3057f | 94 | #if defined(CONFIG_R8A7795) |
e525d34b NI |
95 | /* GSX: force power and clock supply */ |
96 | writel(0x0000001F, SYSC_PWRONCR2); | |
97 | while (readl(SYSC_PWRSR2) != 0x000003E0) | |
98 | mdelay(20); | |
99 | ||
100 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); | |
adf3057f | 101 | #endif |
e525d34b | 102 | |
d1018f5f MV |
103 | /* USB1 pull-up */ |
104 | setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); | |
105 | ||
afb19d65 MV |
106 | /* Configure the HSUSB block */ |
107 | mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); | |
108 | /* Choice USB0SEL */ | |
109 | clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, | |
110 | HSUSB_REG_UGCTRL2_USB0SEL_EHCI); | |
111 | /* low power status */ | |
112 | setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); | |
113 | ||
3158b6f6 | 114 | #ifdef CONFIG_RENESAS_RAVB |
90e53f8b MV |
115 | /* EtherAVB Enable */ |
116 | /* GPSR2 */ | |
117 | gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL); | |
118 | gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL); | |
119 | gpio_request(GPIO_GFN_AVB_LINK, NULL); | |
120 | gpio_request(GPIO_GFN_AVB_PHY_INT, NULL); | |
121 | gpio_request(GPIO_GFN_AVB_MAGIC, NULL); | |
122 | gpio_request(GPIO_GFN_AVB_MDC, NULL); | |
123 | ||
124 | /* IPSR0 */ | |
125 | gpio_request(GPIO_IFN_AVB_MDC, NULL); | |
126 | gpio_request(GPIO_IFN_AVB_MAGIC, NULL); | |
127 | gpio_request(GPIO_IFN_AVB_PHY_INT, NULL); | |
128 | gpio_request(GPIO_IFN_AVB_LINK, NULL); | |
129 | gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL); | |
130 | gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL); | |
131 | /* IPSR1 */ | |
132 | gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL); | |
133 | /* IPSR2 */ | |
134 | gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL); | |
135 | /* IPSR3 */ | |
136 | gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL); | |
137 | ||
adf3057f | 138 | #if defined(CONFIG_R8A7795) |
d1018f5f MV |
139 | /* USB2_OVC */ |
140 | gpio_request(GPIO_GP_6_15, NULL); | |
141 | gpio_direction_input(GPIO_GP_6_15); | |
142 | ||
143 | /* USB2_PWEN */ | |
144 | gpio_request(GPIO_GP_6_14, NULL); | |
145 | gpio_direction_output(GPIO_GP_6_14, 1); | |
146 | gpio_set_value(GPIO_GP_6_14, 1); | |
adf3057f | 147 | #endif |
90e53f8b MV |
148 | /* AVB_PHY_RST */ |
149 | gpio_request(GPIO_GP_2_10, NULL); | |
150 | gpio_direction_output(GPIO_GP_2_10, 0); | |
151 | mdelay(20); | |
152 | gpio_set_value(GPIO_GP_2_10, 1); | |
153 | udelay(1); | |
154 | #endif | |
155 | ||
8212f563 | 156 | #ifdef CONFIG_MMC |
50fb0c45 MV |
157 | /* SDHI0 */ |
158 | gpio_request(GPIO_GFN_SD0_DAT0, NULL); | |
159 | gpio_request(GPIO_GFN_SD0_DAT1, NULL); | |
160 | gpio_request(GPIO_GFN_SD0_DAT2, NULL); | |
161 | gpio_request(GPIO_GFN_SD0_DAT3, NULL); | |
162 | gpio_request(GPIO_GFN_SD0_CLK, NULL); | |
163 | gpio_request(GPIO_GFN_SD0_CMD, NULL); | |
164 | gpio_request(GPIO_GFN_SD0_CD, NULL); | |
165 | gpio_request(GPIO_GFN_SD0_WP, NULL); | |
166 | ||
167 | gpio_request(GPIO_GP_5_2, NULL); | |
168 | gpio_request(GPIO_GP_5_1, NULL); | |
169 | gpio_direction_output(GPIO_GP_5_2, 1); /* power on */ | |
170 | gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */ | |
171 | ||
50fb0c45 MV |
172 | /* SDHI1/SDHI2 eMMC */ |
173 | gpio_request(GPIO_GFN_SD1_DAT0, NULL); | |
174 | gpio_request(GPIO_GFN_SD1_DAT1, NULL); | |
175 | gpio_request(GPIO_GFN_SD1_DAT2, NULL); | |
176 | gpio_request(GPIO_GFN_SD1_DAT3, NULL); | |
177 | gpio_request(GPIO_GFN_SD2_DAT0, NULL); | |
178 | gpio_request(GPIO_GFN_SD2_DAT1, NULL); | |
179 | gpio_request(GPIO_GFN_SD2_DAT2, NULL); | |
180 | gpio_request(GPIO_GFN_SD2_DAT3, NULL); | |
181 | gpio_request(GPIO_GFN_SD2_CLK, NULL); | |
adf3057f | 182 | #if defined(CONFIG_R8A7795) |
50fb0c45 | 183 | gpio_request(GPIO_GFN_SD2_CMD, NULL); |
adf3057f MV |
184 | #elif defined(CONFIG_R8A7796) |
185 | gpio_request(GPIO_FN_SD2_CMD, NULL); | |
186 | #else | |
187 | #error Only R8A7795 and R87796 is supported | |
188 | #endif | |
50fb0c45 MV |
189 | gpio_request(GPIO_GP_5_3, NULL); |
190 | gpio_request(GPIO_GP_5_9, NULL); | |
191 | gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */ | |
192 | gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */ | |
193 | ||
adf3057f | 194 | #if defined(CONFIG_R8A7795) |
50fb0c45 MV |
195 | /* SDHI3 */ |
196 | gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */ | |
197 | gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */ | |
198 | gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */ | |
199 | gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */ | |
200 | gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */ | |
201 | gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */ | |
adf3057f MV |
202 | #elif defined(CONFIG_R8A7796) |
203 | gpio_request(GPIO_FN_SD3_DAT0, NULL); /* GP_4_9 */ | |
204 | gpio_request(GPIO_FN_SD3_DAT1, NULL); /* GP_4_10 */ | |
205 | gpio_request(GPIO_FN_SD3_DAT2, NULL); /* GP_4_11 */ | |
206 | gpio_request(GPIO_FN_SD3_DAT3, NULL); /* GP_4_12 */ | |
207 | gpio_request(GPIO_FN_SD3_CLK, NULL); /* GP_4_7 */ | |
208 | gpio_request(GPIO_FN_SD3_CMD, NULL); /* GP_4_8 */ | |
209 | #else | |
210 | #error Only R8A7795 and R87796 is supported | |
211 | #endif | |
50fb0c45 MV |
212 | /* IPSR10 */ |
213 | gpio_request(GPIO_FN_SD3_CD, NULL); | |
214 | gpio_request(GPIO_FN_SD3_WP, NULL); | |
215 | ||
216 | gpio_request(GPIO_GP_3_15, NULL); | |
217 | gpio_request(GPIO_GP_3_14, NULL); | |
218 | gpio_direction_output(GPIO_GP_3_15, 1); /* power on */ | |
219 | gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */ | |
8212f563 | 220 | #endif |
50fb0c45 | 221 | |
ddb39a07 | 222 | return 0; |
50fb0c45 | 223 | } |
50fb0c45 | 224 | |
e525d34b NI |
225 | int dram_init(void) |
226 | { | |
8f284e66 MV |
227 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
228 | #if (CONFIG_NR_DRAM_BANKS >= 2) | |
229 | gd->ram_size += PHYS_SDRAM_2_SIZE; | |
230 | #endif | |
231 | #if (CONFIG_NR_DRAM_BANKS >= 3) | |
232 | gd->ram_size += PHYS_SDRAM_3_SIZE; | |
233 | #endif | |
234 | #if (CONFIG_NR_DRAM_BANKS >= 4) | |
235 | gd->ram_size += PHYS_SDRAM_4_SIZE; | |
236 | #endif | |
237 | ||
238 | return 0; | |
239 | } | |
e525d34b | 240 | |
8f284e66 MV |
241 | int dram_init_banksize(void) |
242 | { | |
243 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
244 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
245 | #if (CONFIG_NR_DRAM_BANKS >= 2) | |
246 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; | |
247 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | |
248 | #endif | |
249 | #if (CONFIG_NR_DRAM_BANKS >= 3) | |
250 | gd->bd->bi_dram[2].start = PHYS_SDRAM_3; | |
251 | gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; | |
252 | #endif | |
253 | #if (CONFIG_NR_DRAM_BANKS >= 4) | |
254 | gd->bd->bi_dram[3].start = PHYS_SDRAM_4; | |
255 | gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; | |
256 | #endif | |
e525d34b NI |
257 | return 0; |
258 | } | |
259 | ||
260 | const struct rmobile_sysinfo sysinfo = { | |
261 | CONFIG_RCAR_BOARD_STRING | |
262 | }; | |
263 | ||
264 | #define RST_BASE 0xE6160000 | |
265 | #define RST_CA57RESCNT (RST_BASE + 0x40) | |
266 | #define RST_CA53RESCNT (RST_BASE + 0x44) | |
267 | #define RST_RSTOUTCR (RST_BASE + 0x58) | |
268 | #define RST_CODE 0xA5A5000F | |
269 | ||
270 | void reset_cpu(ulong addr) | |
271 | { | |
fe2e8ff9 MV |
272 | #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
273 | i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); | |
274 | #else | |
e525d34b NI |
275 | /* only CA57 ? */ |
276 | writel(RST_CODE, RST_CA57RESCNT); | |
fe2e8ff9 | 277 | #endif |
e525d34b | 278 | } |