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Commit | Line | Data |
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1a2621ba YS |
1 | /* |
2 | * Copyright (C) 2012 Renesas Solutions Corp. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
1a2621ba YS |
5 | */ |
6 | ||
7 | #include <config.h> | |
8 | #include <version.h> | |
9 | #include <asm/processor.h> | |
10 | #include <asm/macro.h> | |
11 | ||
12 | .macro or32, addr, data | |
13 | mov.l \addr, r1 | |
14 | mov.l \data, r0 | |
15 | mov.l @r1, r2 | |
16 | or r2, r0 | |
17 | mov.l r0, @r1 | |
18 | .endm | |
19 | ||
20 | .macro wait_DBCMD | |
21 | mov.l DBWAIT_A, r0 | |
22 | mov.l @r0, r1 | |
23 | .endm | |
24 | ||
25 | .global lowlevel_init | |
26 | .section .spiboot1.text | |
27 | .align 2 | |
28 | ||
29 | lowlevel_init: | |
30 | /*------- GPIO -------*/ | |
31 | write16 PDCR_A, PDCR_D ! SPI0 | |
32 | write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1) | |
33 | write16 PJCR_A, PJCR_D ! SCIF4 | |
34 | write16 PTCR_A, PTCR_D ! STATUS | |
35 | write16 PSEL1_A, PSEL1_D ! SPI0 | |
36 | write16 PSEL2_A, PSEL2_D ! SPI0 | |
37 | write16 PSEL5_A, PSEL5_D ! STATUS | |
38 | ||
39 | bra exit_gpio | |
40 | nop | |
41 | ||
42 | .align 2 | |
43 | ||
44 | /*------- GPIO -------*/ | |
45 | PDCR_A: .long 0xffec0006 | |
46 | PGCR_A: .long 0xffec000c | |
47 | PJCR_A: .long 0xffec0012 | |
48 | PTCR_A: .long 0xffec0026 | |
49 | PSEL1_A: .long 0xffec0072 | |
50 | PSEL2_A: .long 0xffec0074 | |
51 | PSEL5_A: .long 0xffec007a | |
52 | ||
53 | PDCR_D: .long 0x0000 | |
54 | PGCR_D: .long 0x0004 | |
55 | PJCR_D: .long 0x0000 | |
56 | PTCR_D: .long 0x0000 | |
57 | PSEL1_D: .long 0x0000 | |
58 | PSEL2_D: .long 0x3000 | |
59 | PSEL5_D: .long 0x0ffc | |
60 | ||
61 | .align 2 | |
62 | ||
63 | exit_gpio: | |
64 | mov #0, r14 | |
65 | mova 2f, r0 | |
66 | mov.l PC_MASK, r1 | |
67 | tst r0, r1 | |
68 | bf 2f | |
69 | ||
70 | bra exit_pmb | |
71 | nop | |
72 | ||
73 | .align 2 | |
74 | ||
75 | /* If CPU runs on SDRAM (PC=0x5???????) or not. */ | |
76 | PC_MASK: .long 0x20000000 | |
77 | ||
78 | 2: | |
79 | mov #1, r14 | |
80 | ||
81 | mov.l EXPEVT_A, r0 | |
82 | mov.l @r0, r0 | |
83 | mov.l EXPEVT_POWER_ON_RESET, r1 | |
84 | cmp/eq r0, r1 | |
85 | bt 1f | |
86 | ||
87 | /* | |
88 | * If EXPEVT value is manual reset or tlb multipul-hit, | |
89 | * initialization of DDR3IF is not necessary. | |
90 | */ | |
91 | bra exit_ddr | |
92 | nop | |
93 | ||
94 | 1: | |
95 | /*------- Reset -------*/ | |
96 | write32 MRSTCR0_A, MRSTCR0_D | |
97 | write32 MRSTCR1_A, MRSTCR1_D | |
98 | ||
99 | /* For Core Reset */ | |
100 | mov.l DBACEN_A, r0 | |
101 | mov.l @r0, r0 | |
102 | cmp/eq #0, r0 | |
103 | bt 3f | |
104 | ||
105 | /* | |
106 | * If DBACEN == 1(DBSC was already enabled), we have to avoid the | |
107 | * initialization of DDR3-SDRAM. | |
108 | */ | |
109 | bra exit_ddr | |
110 | nop | |
111 | ||
112 | 3: | |
113 | /*------- DDR3IF -------*/ | |
114 | /* oscillation stabilization time */ | |
115 | wait_timer WAIT_OSC_TIME | |
116 | ||
117 | /* step 3 */ | |
118 | write32 DBCMD_A, DBCMD_RSTL_VAL | |
119 | wait_timer WAIT_30US | |
120 | ||
121 | /* step 4 */ | |
122 | write32 DBCMD_A, DBCMD_PDEN_VAL | |
123 | ||
124 | /* step 5 */ | |
125 | write32 DBKIND_A, DBKIND_D | |
126 | ||
127 | /* step 6 */ | |
128 | write32 DBCONF_A, DBCONF_D | |
129 | write32 DBTR0_A, DBTR0_D | |
130 | write32 DBTR1_A, DBTR1_D | |
131 | write32 DBTR2_A, DBTR2_D | |
132 | write32 DBTR3_A, DBTR3_D | |
133 | write32 DBTR4_A, DBTR4_D | |
134 | write32 DBTR5_A, DBTR5_D | |
135 | write32 DBTR6_A, DBTR6_D | |
136 | write32 DBTR7_A, DBTR7_D | |
137 | write32 DBTR8_A, DBTR8_D | |
138 | write32 DBTR9_A, DBTR9_D | |
139 | write32 DBTR10_A, DBTR10_D | |
140 | write32 DBTR11_A, DBTR11_D | |
141 | write32 DBTR12_A, DBTR12_D | |
142 | write32 DBTR13_A, DBTR13_D | |
143 | write32 DBTR14_A, DBTR14_D | |
144 | write32 DBTR15_A, DBTR15_D | |
145 | write32 DBTR16_A, DBTR16_D | |
146 | write32 DBTR17_A, DBTR17_D | |
147 | write32 DBTR18_A, DBTR18_D | |
148 | write32 DBTR19_A, DBTR19_D | |
149 | write32 DBRNK0_A, DBRNK0_D | |
150 | ||
151 | /* step 7 */ | |
152 | write32 DBPDCNT3_A, DBPDCNT3_D | |
153 | ||
154 | /* step 8 */ | |
155 | write32 DBPDCNT1_A, DBPDCNT1_D | |
156 | write32 DBPDCNT2_A, DBPDCNT2_D | |
157 | write32 DBPDLCK_A, DBPDLCK_D | |
158 | write32 DBPDRGA_A, DBPDRGA_D | |
159 | write32 DBPDRGD_A, DBPDRGD_D | |
160 | ||
161 | /* step 9 */ | |
162 | wait_timer WAIT_30US | |
163 | ||
164 | /* step 10 */ | |
165 | write32 DBPDCNT0_A, DBPDCNT0_D | |
166 | ||
167 | /* step 11 */ | |
168 | wait_timer WAIT_30US | |
169 | wait_timer WAIT_30US | |
170 | ||
171 | /* step 12 */ | |
172 | write32 DBCMD_A, DBCMD_WAIT_VAL | |
173 | wait_DBCMD | |
174 | ||
175 | /* step 13 */ | |
176 | write32 DBCMD_A, DBCMD_RSTH_VAL | |
177 | wait_DBCMD | |
178 | ||
179 | /* step 14 */ | |
180 | write32 DBCMD_A, DBCMD_WAIT_VAL | |
181 | write32 DBCMD_A, DBCMD_WAIT_VAL | |
182 | write32 DBCMD_A, DBCMD_WAIT_VAL | |
183 | write32 DBCMD_A, DBCMD_WAIT_VAL | |
184 | ||
185 | /* step 15 */ | |
186 | write32 DBCMD_A, DBCMD_PDXT_VAL | |
187 | ||
188 | /* step 16 */ | |
189 | write32 DBCMD_A, DBCMD_MRS2_VAL | |
190 | ||
191 | /* step 17 */ | |
192 | write32 DBCMD_A, DBCMD_MRS3_VAL | |
193 | ||
194 | /* step 18 */ | |
195 | write32 DBCMD_A, DBCMD_MRS1_VAL | |
196 | ||
197 | /* step 19 */ | |
198 | write32 DBCMD_A, DBCMD_MRS0_VAL | |
199 | ||
200 | /* step 20 */ | |
201 | write32 DBCMD_A, DBCMD_ZQCL_VAL | |
202 | ||
203 | write32 DBCMD_A, DBCMD_REF_VAL | |
204 | write32 DBCMD_A, DBCMD_REF_VAL | |
205 | wait_DBCMD | |
206 | ||
207 | /* step 21 */ | |
208 | write32 DBADJ0_A, DBADJ0_D | |
209 | write32 DBADJ1_A, DBADJ1_D | |
210 | write32 DBADJ2_A, DBADJ2_D | |
211 | ||
212 | /* step 22 */ | |
213 | write32 DBRFCNF0_A, DBRFCNF0_D | |
214 | write32 DBRFCNF1_A, DBRFCNF1_D | |
215 | write32 DBRFCNF2_A, DBRFCNF2_D | |
216 | ||
217 | /* step 23 */ | |
218 | write32 DBCALCNF_A, DBCALCNF_D | |
219 | ||
220 | /* step 24 */ | |
221 | write32 DBRFEN_A, DBRFEN_D | |
222 | write32 DBCMD_A, DBCMD_SRXT_VAL | |
223 | ||
224 | /* step 25 */ | |
225 | write32 DBACEN_A, DBACEN_D | |
226 | ||
227 | /* step 26 */ | |
228 | wait_DBCMD | |
229 | ||
230 | bra exit_ddr | |
231 | nop | |
232 | ||
233 | .align 2 | |
234 | ||
235 | EXPEVT_A: .long 0xff000024 | |
236 | EXPEVT_POWER_ON_RESET: .long 0x00000000 | |
237 | ||
238 | /*------- Reset -------*/ | |
239 | MRSTCR0_A: .long 0xffd50030 | |
240 | MRSTCR0_D: .long 0xfe1ffe7f | |
241 | MRSTCR1_A: .long 0xffd50034 | |
242 | MRSTCR1_D: .long 0xfff3ffff | |
243 | ||
244 | /*------- DDR3IF -------*/ | |
245 | DBCMD_A: .long 0xfe800018 | |
246 | DBKIND_A: .long 0xfe800020 | |
247 | DBCONF_A: .long 0xfe800024 | |
248 | DBTR0_A: .long 0xfe800040 | |
249 | DBTR1_A: .long 0xfe800044 | |
250 | DBTR2_A: .long 0xfe800048 | |
251 | DBTR3_A: .long 0xfe800050 | |
252 | DBTR4_A: .long 0xfe800054 | |
253 | DBTR5_A: .long 0xfe800058 | |
254 | DBTR6_A: .long 0xfe80005c | |
255 | DBTR7_A: .long 0xfe800060 | |
256 | DBTR8_A: .long 0xfe800064 | |
257 | DBTR9_A: .long 0xfe800068 | |
258 | DBTR10_A: .long 0xfe80006c | |
259 | DBTR11_A: .long 0xfe800070 | |
260 | DBTR12_A: .long 0xfe800074 | |
261 | DBTR13_A: .long 0xfe800078 | |
262 | DBTR14_A: .long 0xfe80007c | |
263 | DBTR15_A: .long 0xfe800080 | |
264 | DBTR16_A: .long 0xfe800084 | |
265 | DBTR17_A: .long 0xfe800088 | |
266 | DBTR18_A: .long 0xfe80008c | |
267 | DBTR19_A: .long 0xfe800090 | |
268 | DBRNK0_A: .long 0xfe800100 | |
269 | DBPDCNT0_A: .long 0xfe800200 | |
270 | DBPDCNT1_A: .long 0xfe800204 | |
271 | DBPDCNT2_A: .long 0xfe800208 | |
272 | DBPDCNT3_A: .long 0xfe80020c | |
273 | DBPDLCK_A: .long 0xfe800280 | |
274 | DBPDRGA_A: .long 0xfe800290 | |
275 | DBPDRGD_A: .long 0xfe8002a0 | |
276 | DBADJ0_A: .long 0xfe8000c0 | |
277 | DBADJ1_A: .long 0xfe8000c4 | |
278 | DBADJ2_A: .long 0xfe8000c8 | |
279 | DBRFCNF0_A: .long 0xfe8000e0 | |
280 | DBRFCNF1_A: .long 0xfe8000e4 | |
281 | DBRFCNF2_A: .long 0xfe8000e8 | |
282 | DBCALCNF_A: .long 0xfe8000f4 | |
283 | DBRFEN_A: .long 0xfe800014 | |
284 | DBACEN_A: .long 0xfe800010 | |
285 | DBWAIT_A: .long 0xfe80001c | |
286 | ||
287 | WAIT_OSC_TIME: .long 6000 | |
288 | WAIT_30US: .long 13333 | |
289 | ||
290 | DBCMD_RSTL_VAL: .long 0x20000000 | |
291 | DBCMD_PDEN_VAL: .long 0x1000d73c | |
292 | DBCMD_WAIT_VAL: .long 0x0000d73c | |
293 | DBCMD_RSTH_VAL: .long 0x2100d73c | |
294 | DBCMD_PDXT_VAL: .long 0x110000c8 | |
295 | DBCMD_MRS0_VAL: .long 0x28000930 | |
296 | DBCMD_MRS1_VAL: .long 0x29000004 | |
297 | DBCMD_MRS2_VAL: .long 0x2a000008 | |
298 | DBCMD_MRS3_VAL: .long 0x2b000000 | |
299 | DBCMD_ZQCL_VAL: .long 0x03000200 | |
300 | DBCMD_REF_VAL: .long 0x0c000000 | |
301 | DBCMD_SRXT_VAL: .long 0x19000000 | |
302 | DBKIND_D: .long 0x00000007 | |
303 | DBCONF_D: .long 0x0f030a01 | |
304 | DBTR0_D: .long 0x00000007 | |
305 | DBTR1_D: .long 0x00000006 | |
306 | DBTR2_D: .long 0x00000000 | |
307 | DBTR3_D: .long 0x00000007 | |
308 | DBTR4_D: .long 0x00070007 | |
309 | DBTR5_D: .long 0x0000001b | |
310 | DBTR6_D: .long 0x00000014 | |
311 | DBTR7_D: .long 0x00000005 | |
312 | DBTR8_D: .long 0x00000015 | |
313 | DBTR9_D: .long 0x00000006 | |
314 | DBTR10_D: .long 0x00000008 | |
315 | DBTR11_D: .long 0x00000007 | |
316 | DBTR12_D: .long 0x0000000e | |
317 | DBTR13_D: .long 0x00000056 | |
318 | DBTR14_D: .long 0x00000006 | |
319 | DBTR15_D: .long 0x00000004 | |
320 | DBTR16_D: .long 0x00150002 | |
321 | DBTR17_D: .long 0x000c0017 | |
322 | DBTR18_D: .long 0x00000200 | |
323 | DBTR19_D: .long 0x00000040 | |
324 | DBRNK0_D: .long 0x00000001 | |
325 | DBPDCNT0_D: .long 0x00000001 | |
326 | DBPDCNT1_D: .long 0x00000001 | |
327 | DBPDCNT2_D: .long 0x00000000 | |
328 | DBPDCNT3_D: .long 0x00004010 | |
329 | DBPDLCK_D: .long 0x0000a55a | |
330 | DBPDRGA_D: .long 0x00000028 | |
331 | DBPDRGD_D: .long 0x00017100 | |
332 | ||
333 | DBADJ0_D: .long 0x00000000 | |
334 | DBADJ1_D: .long 0x00000000 | |
335 | DBADJ2_D: .long 0x18061806 | |
336 | DBRFCNF0_D: .long 0x000001ff | |
337 | DBRFCNF1_D: .long 0x08001000 | |
338 | DBRFCNF2_D: .long 0x00000000 | |
339 | DBCALCNF_D: .long 0x0000ffff | |
340 | DBRFEN_D: .long 0x00000001 | |
341 | DBACEN_D: .long 0x00000001 | |
342 | ||
343 | .align 2 | |
344 | exit_ddr: | |
345 | #if defined(CONFIG_SH_32BIT) | |
346 | /*------- set PMB -------*/ | |
347 | write32 PASCR_A, PASCR_29BIT_D | |
348 | write32 MMUCR_A, MMUCR_D | |
349 | ||
350 | /***************************************************************** | |
351 | * ent virt phys v sz c wt | |
352 | * 0 0xa0000000 0x00000000 1 128M 0 1 | |
353 | * 1 0xa8000000 0x48000000 1 128M 0 1 | |
354 | * 5 0x88000000 0x48000000 1 128M 1 1 | |
355 | */ | |
356 | write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D | |
357 | write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D | |
358 | write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D | |
359 | write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D | |
360 | write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D | |
361 | write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D | |
362 | ||
363 | write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D | |
364 | write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D | |
365 | write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D | |
366 | write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D | |
367 | write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D | |
368 | write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D | |
369 | write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D | |
370 | write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D | |
371 | write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D | |
372 | write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D | |
373 | write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D | |
374 | write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D | |
375 | write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D | |
376 | ||
377 | write32 PASCR_A, PASCR_INIT | |
378 | mov.l DUMMY_ADDR, r0 | |
379 | icbi @r0 | |
380 | #endif /* if defined(CONFIG_SH_32BIT) */ | |
381 | ||
382 | exit_pmb: | |
383 | /* CPU is running on ILRAM? */ | |
384 | mov r14, r0 | |
385 | tst #1, r0 | |
386 | bt 1f | |
387 | ||
388 | mov.l _stack_ilram, r15 | |
389 | mov.l _spiboot_main, r0 | |
390 | 100: bsrf r0 | |
391 | nop | |
392 | ||
393 | .align 2 | |
394 | _spiboot_main: .long (spiboot_main - (100b + 4)) | |
395 | _stack_ilram: .long 0xe5204000 | |
396 | ||
397 | 1: | |
398 | write32 CCR_A, CCR_D | |
399 | ||
400 | rts | |
401 | nop | |
402 | ||
403 | .align 2 | |
404 | ||
405 | #if defined(CONFIG_SH_32BIT) | |
406 | /*------- set PMB -------*/ | |
407 | PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) | |
408 | PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) | |
409 | PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) | |
410 | PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) | |
411 | PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) | |
412 | PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) | |
413 | PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) | |
414 | PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) | |
415 | PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) | |
416 | PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) | |
417 | PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) | |
418 | PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) | |
419 | PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) | |
420 | PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) | |
421 | PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) | |
422 | PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) | |
423 | ||
424 | PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) | |
425 | PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) | |
426 | PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) | |
427 | PMB_ADDR_NOT_USE_D: .long 0x00000000 | |
428 | ||
429 | PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) | |
430 | PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) | |
431 | PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) | |
432 | ||
433 | /* ppn ub v s1 s0 c wt */ | |
434 | PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) | |
435 | PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) | |
436 | PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) | |
437 | ||
438 | PASCR_A: .long 0xff000070 | |
439 | DUMMY_ADDR: .long 0xa0000000 | |
440 | PASCR_29BIT_D: .long 0x00000000 | |
441 | PASCR_INIT: .long 0x80000080 | |
442 | MMUCR_A: .long 0xff000010 | |
443 | MMUCR_D: .long 0x00000004 /* clear ITLB */ | |
444 | #endif /* CONFIG_SH_32BIT */ | |
445 | ||
446 | CCR_A: .long CCR | |
447 | CCR_D: .long CCR_CACHE_INIT |