[people/ms/u-boot.git] / board / renesas / sh7757lcr / sh7757lcr.c

/*
 * Copyright (C) 2011  Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmc.h>
#include <spi.h>
#include <spi_flash.h>

int checkboard(void)
{
	puts("BOARD: R0P7757LC0030RL board\n");

	return 0;
}

static void init_gctrl(void)
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	unsigned long graofst;

	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	writel(graofst | 0x20000f00, &gctrl->gracr3);
}

static int init_pcie_bridge_from_spi(void *buf, size_t size)
{
	struct spi_flash *spi;
	int ret;
	unsigned long pcie_addr;

	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (!spi) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	if (is_sh7757_b0())
		pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
	else
		pcie_addr = SH7757LCR_PCIEBRG_ADDR;

	ret = spi_flash_read(spi, pcie_addr, size, buf);
	if (ret) {
		printf("%s: spi_flash read error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	return 0;
}

static void init_pcie_bridge(void)
{
	struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	int i;
	unsigned char *data;
	unsigned short tmp;
	unsigned long pcie_size;

	if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
		return;

	if (is_sh7757_b0())
		pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
	else
		pcie_size = SH7757LCR_PCIEBRG_SIZE;

	data = malloc(pcie_size);
	if (!data) {
		printf("%s: malloc error.\n", __func__);
		return;
	}
	if (init_pcie_bridge_from_spi(data, pcie_size)) {
		free(data);
		return;
	}

	if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
	    data[3] == 0xff) {
		free(data);
		printf("%s: skipped initialization\n", __func__);
		return;
	}

	writew(0xa501, &pciebrg->ctrl_h8s);	/* reset */
	writew(0x0000, &pciebrg->cp_ctrl);
	writew(0x0000, &pciebrg->cp_addr);

	for (i = 0; i < pcie_size; i += 2) {
		tmp = (data[i] << 8) | data[i + 1];
		writew(tmp, &pciebrg->cp_data);
	}

	writew(0xa500, &pciebrg->ctrl_h8s);	/* start */
	if (!is_sh7757_b0())
		writel(0x00000001, &pcie_setup->pbictl3);

	free(data);
}

static void init_usb_phy(void)
{
	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	struct usb1_port_regs *port = USB1_PORT_BASE;
	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;

	writew(0x0100, &phy->reset);		/* set reset */
	/* port0 = USB0, port1 = USB1 */
	writew(0x0002, &phy->portsel);
	writel(0x0001, &port->port1sel);	/* port1 = Host */
	writew(0x0111, &phy->reset);		/* clear reset */

	writew(0x4000, &common0->suspmode);
	writew(0x4000, &common1->suspmode);

#if defined(__LITTLE_ENDIAN)
	writel(0x00000000, &align->ehcidatac);
	writel(0x00000000, &align->ohcidatac);
#endif
}

static void set_mac_to_sh_eth_register(int channel, char *mac_string)
{
	struct ether_mac_regs *ether;
	unsigned char mac[6];
	unsigned long val;

	eth_parse_enetaddr(mac_string, mac);

	if (!channel)
		ether = ETHER0_MAC_BASE;
	else
		ether = ETHER1_MAC_BASE;

	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
	writel(val, &ether->mahr);
	val = (mac[4] << 8) | mac[5];
	writel(val, &ether->malr);
}

static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
{
	struct ether_mac_regs *ether;
	unsigned char mac[6];
	unsigned long val;

	eth_parse_enetaddr(mac_string, mac);

	if (!channel)
		ether = GETHER0_MAC_BASE;
	else
		ether = GETHER1_MAC_BASE;

	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
	writel(val, &ether->mahr);
	val = (mac[4] << 8) | mac[5];
	writel(val, &ether->malr);
}

/*****************************************************************
 * This PMB must be set on this timing. The lowlevel_init is run on
 * Area 0(phys 0x00000000), so we have to map it.
 *
 * The new PMB table is following:
 * ent	virt		phys		v	sz	c	wt
 * 0	0xa0000000	0x40000000	1	128M	0	1
 * 1	0xa8000000	0x48000000	1	128M	0	1
 * 2	0xb0000000	0x50000000	1	128M	0	1
 * 3	0xb8000000	0x58000000	1	128M	0	1
 * 4	0x80000000	0x40000000	1	128M	1	1
 * 5	0x88000000	0x48000000	1	128M	1	1
 * 6	0x90000000	0x50000000	1	128M	1	1
 * 7	0x98000000	0x58000000	1	128M	1	1
 */
static void set_pmb_on_board_init(void)
{
	struct mmu_regs *mmu = MMU_BASE;

	/* clear ITLB */
	writel(0x00000004, &mmu->mmucr);

	/* delete PMB for SPIBOOT */
	writel(0, PMB_ADDR_BASE(0));
	writel(0, PMB_DATA_BASE(0));

	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	/*			ppn  ub v s1 s0  c  wt */
	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
}

int board_init(void)
{
	struct gether_control_regs *gether = GETHER_CONTROL_BASE;

	set_pmb_on_board_init();

	/* enable RMII's MDIO (disable GRMII's MDIO) */
	writel(0x00030000, &gether->gbecont);

	init_gctrl();
	init_usb_phy();

	return 0;
}

int board_mmc_init(bd_t *bis)
{
	return mmcif_mmc_init();
}

static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
	struct spi_flash *spi;
	int ret;

	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (spi == NULL) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
	if (ret) {
		printf("%s: spi_flash read error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	return 0;
}

static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
{
	memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
		SH7757LCR_ETHERNET_MAC_SIZE);
	mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */

	return 0;
}

static void init_ethernet_mac(void)
{
	char mac_string[64];
	char env_string[64];
	int i;
	unsigned char *buf;

	buf = malloc(256);
	if (!buf) {
		printf("%s: malloc error.\n", __func__);
		return;
	}
	get_sh_eth_mac_raw(buf, 256);

	/* Fast Ethernet */
	for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
		get_sh_eth_mac(i, mac_string, buf);
		if (i == 0)
			setenv("ethaddr", mac_string);
		else {
			sprintf(env_string, "eth%daddr", i);
			setenv(env_string, mac_string);
		}

		set_mac_to_sh_eth_register(i, mac_string);
	}

	/* Gigabit Ethernet */
	for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
		get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
		sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
		setenv(env_string, mac_string);

		set_mac_to_sh_giga_eth_register(i, mac_string);
	}

	free(buf);
}

static void init_pcie(void)
{
	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;

	writel(0x00000ff2, &pcie_setup->ladmsk0);
	writel(0x00000001, &pcie_setup->barmap);
	writel(0xffcaa000, &pcie_setup->lad0);
	writel(0x00030000, &pcie_sysbus->endictl0);
	writel(0x00000003, &pcie_sysbus->endictl1);
	writel(0x00000004, &pcie_setup->pbictl2);
}

static void finish_spiboot(void)
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	/*
	 *  SH7757 B0 does not use LBSC.
	 *  So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
	 *  This setting is not cleared by manual reset, So we have to set it
	 *  to 0.
	 */
	writel(0x00000000, &gctrl->spibootcan);
}

int board_late_init(void)
{
	init_ethernet_mac();
	init_pcie_bridge();
	init_pcie();
	finish_spiboot();

	return 0;
}

int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	unsigned long graofst;

	writel(0xfedcba98, &gctrl->wprotect);
	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	writel(graofst | 0xa0000f00, &gctrl->gracr3);

	return 0;
}

U_BOOT_CMD(
	sh_g200,	1,	1,	do_sh_g200,
	"enable sh-g200",
	"enable SH-G200 bus (disable PCIe-G200)"
);

int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int i, ret;
	char mac_string[256];
	struct spi_flash *spi;
	unsigned char *buf;

	if (argc != 5) {
		buf = malloc(256);
		if (!buf) {
			printf("%s: malloc error.\n", __func__);
			return 1;
		}

		get_sh_eth_mac_raw(buf, 256);

		/* print current MAC address */
		for (i = 0; i < 4; i++) {
			get_sh_eth_mac(i, mac_string, buf);
			if (i < 2)
				printf(" ETHERC ch%d = %s\n", i, mac_string);
			else
				printf("GETHERC ch%d = %s\n", i-2, mac_string);
		}
		free(buf);
		return 0;
	}

	/* new setting */
	memset(mac_string, 0xff, sizeof(mac_string));
	sprintf(mac_string, "%s\t%s\t%s\t%s",
		argv[1], argv[2], argv[3], argv[4]);

	/* write MAC data to SPI rom */
	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (!spi) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
				SH7757LCR_SPI_SECTOR_SIZE);
	if (ret) {
		printf("%s: spi_flash erase error.\n", __func__);
		return 1;
	}

	ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
				sizeof(mac_string), mac_string);
	if (ret) {
		printf("%s: spi_flash write error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	puts("The writing of the MAC address to SPI ROM was completed.\n");

	return 0;
}

U_BOOT_CMD(
	write_mac,	5,	1,	do_write_mac,
	"write MAC address for ETHERC/GETHERC",
	"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
);
Commit	Line	Data
8e9c897b YS	1	/*
	2	* Copyright (C) 2011 Renesas Solutions Corp.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
8e9c897b YS	5	*/
	6
	7	#include <common.h>
	8	#include <malloc.h>
	9	#include <asm/processor.h>
	10	#include <asm/io.h>
4f0e8477	11	#include <asm/mmc.h>
ff0960f9	12	#include <spi.h>
8e9c897b YS	13	#include <spi_flash.h>
	14
	15	int checkboard(void)
	16	{
	17	puts("BOARD: R0P7757LC0030RL board\n");
	18
	19	return 0;
	20	}
	21
	22	static void init_gctrl(void)
	23	{
	24	struct gctrl_regs *gctrl = GCTRL_BASE;
	25	unsigned long graofst;
	26
	27	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	28	writel(graofst \| 0x20000f00, &gctrl->gracr3);
	29	}
	30
	31	static int init_pcie_bridge_from_spi(void *buf, size_t size)
	32	{
	33	struct spi_flash *spi;
	34	int ret;
	35	unsigned long pcie_addr;
	36
	37	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	38	if (!spi) {
	39	printf("%s: spi_flash probe error.\n", __func__);
	40	return 1;
	41	}
	42
	43	if (is_sh7757_b0())
	44	pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
	45	else
	46	pcie_addr = SH7757LCR_PCIEBRG_ADDR;
	47
	48	ret = spi_flash_read(spi, pcie_addr, size, buf);
	49	if (ret) {
	50	printf("%s: spi_flash read error.\n", __func__);
	51	spi_flash_free(spi);
	52	return 1;
	53	}
	54	spi_flash_free(spi);
	55
	56	return 0;
	57	}
	58
	59	static void init_pcie_bridge(void)
	60	{
	61	struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
	62	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	63	int i;
	64	unsigned char *data;
	65	unsigned short tmp;
	66	unsigned long pcie_size;
	67
	68	if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
	69	return;
	70
	71	if (is_sh7757_b0())
	72	pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
	73	else
	74	pcie_size = SH7757LCR_PCIEBRG_SIZE;
	75
	76	data = malloc(pcie_size);
77	if (!data) {
78	printf("%s: malloc error.\n", __func__);
79	return;
80	}
81	if (init_pcie_bridge_from_spi(data, pcie_size)) {
82	free(data);
83	return;
84	}
85
86	if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
87	data[3] == 0xff) {
88	free(data);
89	printf("%s: skipped initialization\n", __func__);
90	return;
91	}
92
93	writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
94	writew(0x0000, &pciebrg->cp_ctrl);
95	writew(0x0000, &pciebrg->cp_addr);
96
97	for (i = 0; i < pcie_size; i += 2) {
98	tmp = (data[i] << 8) \| data[i + 1];
99	writew(tmp, &pciebrg->cp_data);
100	}
101
102	writew(0xa500, &pciebrg->ctrl_h8s); /* start */
103	if (!is_sh7757_b0())
104	writel(0x00000001, &pcie_setup->pbictl3);
105
106	free(data);
107	}
108
109	static void init_usb_phy(void)
110	{
111	struct usb_common_regs *common0 = USB0_COMMON_BASE;
112	struct usb_common_regs *common1 = USB1_COMMON_BASE;
113	struct usb0_phy_regs *phy = USB0_PHY_BASE;
114	struct usb1_port_regs *port = USB1_PORT_BASE;
115	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
116
117	writew(0x0100, &phy->reset); /* set reset */
118	/* port0 = USB0, port1 = USB1 */
119	writew(0x0002, &phy->portsel);
120	writel(0x0001, &port->port1sel); /* port1 = Host */
121	writew(0x0111, &phy->reset); /* clear reset */
122
123	writew(0x4000, &common0->suspmode);
124	writew(0x4000, &common1->suspmode);
125
126	#if defined(__LITTLE_ENDIAN)
127	writel(0x00000000, &align->ehcidatac);
128	writel(0x00000000, &align->ohcidatac);
129	#endif
130	}
131
132	static void set_mac_to_sh_eth_register(int channel, char *mac_string)
133	{
134	struct ether_mac_regs *ether;
135	unsigned char mac[6];
136	unsigned long val;
137
138	eth_parse_enetaddr(mac_string, mac);
139
140	if (!channel)
141	ether = ETHER0_MAC_BASE;
142	else
143	ether = ETHER1_MAC_BASE;
144
145	val = (mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3];
146	writel(val, &ether->mahr);
147	val = (mac[4] << 8) \| mac[5];
148	writel(val, &ether->malr);
149	}
150
151	static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
152	{
153	struct ether_mac_regs *ether;
154	unsigned char mac[6];
155	unsigned long val;
156
157	eth_parse_enetaddr(mac_string, mac);
158
159	if (!channel)
160	ether = GETHER0_MAC_BASE;
161	else
162	ether = GETHER1_MAC_BASE;
163
164	val = (mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3];
165	writel(val, &ether->mahr);
166	val = (mac[4] << 8) \| mac[5];
167	writel(val, &ether->malr);
168	}
169
170	/*****************************************************************
171	* This PMB must be set on this timing. The lowlevel_init is run on
172	* Area 0(phys 0x00000000), so we have to map it.
173	*
174	* The new PMB table is following:
175	* ent virt phys v sz c wt
176	* 0 0xa0000000 0x40000000 1 128M 0 1
177	* 1 0xa8000000 0x48000000 1 128M 0 1
178	* 2 0xb0000000 0x50000000 1 128M 0 1
179	* 3 0xb8000000 0x58000000 1 128M 0 1
180	* 4 0x80000000 0x40000000 1 128M 1 1
181	* 5 0x88000000 0x48000000 1 128M 1 1
182	* 6 0x90000000 0x50000000 1 128M 1 1
183	* 7 0x98000000 0x58000000 1 128M 1 1
184	*/
185	static void set_pmb_on_board_init(void)
186	{
187	struct mmu_regs *mmu = MMU_BASE;
188
189	/* clear ITLB */
190	writel(0x00000004, &mmu->mmucr);
191
192	/* delete PMB for SPIBOOT */
193	writel(0, PMB_ADDR_BASE(0));
194	writel(0, PMB_DATA_BASE(0));
195
196	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
197	/* ppn ub v s1 s0 c wt */
198	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
199	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
200	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
201	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
202	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
203	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
204	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
205	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
206	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
207	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
208	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
209	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
210	}
211
212	int board_init(void)
213	{
214	struct gether_control_regs *gether = GETHER_CONTROL_BASE;
215
216	set_pmb_on_board_init();
217
218	/* enable RMII's MDIO (disable GRMII's MDIO) */
219	writel(0x00030000, &gether->gbecont);
220
221	init_gctrl();
222	init_usb_phy();
223
224	return 0;
225	}
226
566f63d5 YS	227	int board_mmc_init(bd_t *bis)
	228	{
	229	return mmcif_mmc_init();
	230	}
	231
8e9c897b YS	232	static int get_sh_eth_mac_raw(unsigned char *buf, int size)
	233	{
	234	struct spi_flash *spi;
	235	int ret;
	236
	237	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	238	if (spi == NULL) {
	239	printf("%s: spi_flash probe error.\n", __func__);
	240	return 1;
	241	}
	242
	243	ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
	244	if (ret) {
	245	printf("%s: spi_flash read error.\n", __func__);
	246	spi_flash_free(spi);
	247	return 1;
	248	}
	249	spi_flash_free(spi);
	250
	251	return 0;
	252	}
	253
	254	static int get_sh_eth_mac(int channel, char mac_string, unsigned char buf)
	255	{
	256	memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
	257	SH7757LCR_ETHERNET_MAC_SIZE);
	258	mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
	259
	260	return 0;
	261	}
	262
	263	static void init_ethernet_mac(void)
	264	{
	265	char mac_string[64];
	266	char env_string[64];
	267	int i;
	268	unsigned char *buf;
	269
	270	buf = malloc(256);
	271	if (!buf) {
	272	printf("%s: malloc error.\n", __func__);
	273	return;
	274	}
	275	get_sh_eth_mac_raw(buf, 256);
	276
	277	/* Fast Ethernet */
	278	for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
	279	get_sh_eth_mac(i, mac_string, buf);
	280	if (i == 0)
	281	setenv("ethaddr", mac_string);
	282	else {
	283	sprintf(env_string, "eth%daddr", i);
	284	setenv(env_string, mac_string);
	285	}
	286
	287	set_mac_to_sh_eth_register(i, mac_string);
	288	}
	289
	290	/* Gigabit Ethernet */
	291	for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
	292	get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
	293	sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
	294	setenv(env_string, mac_string);
	295
296	set_mac_to_sh_giga_eth_register(i, mac_string);
297	}
298
299	free(buf);
300	}
301
302	static void init_pcie(void)
303	{
304	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
305	struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
306
307	writel(0x00000ff2, &pcie_setup->ladmsk0);
308	writel(0x00000001, &pcie_setup->barmap);
309	writel(0xffcaa000, &pcie_setup->lad0);
310	writel(0x00030000, &pcie_sysbus->endictl0);
311	writel(0x00000003, &pcie_sysbus->endictl1);
312	writel(0x00000004, &pcie_setup->pbictl2);
313	}
314
315	static void finish_spiboot(void)
316	{
317	struct gctrl_regs *gctrl = GCTRL_BASE;
318	/*
319	* SH7757 B0 does not use LBSC.
320	* So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
321	* This setting is not cleared by manual reset, So we have to set it
322	* to 0.
323	*/
324	writel(0x00000000, &gctrl->spibootcan);
325	}
326
327	int board_late_init(void)
328	{
329	init_ethernet_mac();
330	init_pcie_bridge();
331	init_pcie();
332	finish_spiboot();
333
334	return 0;
335	}
336
337	int do_sh_g200(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
338	{
339	struct gctrl_regs *gctrl = GCTRL_BASE;
340	unsigned long graofst;
341
342	writel(0xfedcba98, &gctrl->wprotect);
343	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
344	writel(graofst \| 0xa0000f00, &gctrl->gracr3);
345
346	return 0;
347	}
348
349	U_BOOT_CMD(
350	sh_g200, 1, 1, do_sh_g200,
351	"enable sh-g200",
352	"enable SH-G200 bus (disable PCIe-G200)"
353	);
354
355	int do_write_mac(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
356	{
357	int i, ret;
358	char mac_string[256];
359	struct spi_flash *spi;
360	unsigned char *buf;
361
362	if (argc != 5) {
363	buf = malloc(256);
364	if (!buf) {
365	printf("%s: malloc error.\n", __func__);
366	return 1;
367	}
368
369	get_sh_eth_mac_raw(buf, 256);
370
371	/* print current MAC address */
372	for (i = 0; i < 4; i++) {
373	get_sh_eth_mac(i, mac_string, buf);
374	if (i < 2)
375	printf(" ETHERC ch%d = %s\n", i, mac_string);
376	else
377	printf("GETHERC ch%d = %s\n", i-2, mac_string);
378	}
379	free(buf);
380	return 0;
381	}
382
383	/* new setting */
384	memset(mac_string, 0xff, sizeof(mac_string));
385	sprintf(mac_string, "%s\t%s\t%s\t%s",
386	argv[1], argv[2], argv[3], argv[4]);
387
388	/* write MAC data to SPI rom */
389	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
390	if (!spi) {
391	printf("%s: spi_flash probe error.\n", __func__);
392	return 1;
393	}
394
395	ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
396	SH7757LCR_SPI_SECTOR_SIZE);
397	if (ret) {
398	printf("%s: spi_flash erase error.\n", __func__);
399	return 1;
400	}
401
402	ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
403	sizeof(mac_string), mac_string);
404	if (ret) {
405	printf("%s: spi_flash write error.\n", __func__);
406	spi_flash_free(spi);
407	return 1;
408	}
409	spi_flash_free(spi);
410
411	puts("The writing of the MAC address to SPI ROM was completed.\n");
412
413	return 0;
414	}
415
416	U_BOOT_CMD(
417	write_mac, 5, 1, do_write_mac,
418	"write MAC address for ETHERC/GETHERC",
419	"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
420	);