[people/ms/u-boot.git] / board / renesas / ulcb / ulcb.c

/*
 * board/renesas/ulcb/ulcb.c
 *     This file is ULCB board support.
 *
 * Copyright (C) 2017 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>

DECLARE_GLOBAL_DATA_PTR;

#define CPGWPCR	0xE6150904
#define CPGWPR  0xE615090C

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	writel(0xA5A50000, CPGWPCR);
	writel(0xFFFFFFFF, CPGWPR);
}

#define GSX_MSTP112		BIT(12)	/* 3DG */
#define TMU0_MSTP125		BIT(25)	/* secure */
#define TMU1_MSTP124		BIT(24)	/* non-secure */
#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
#define DVFS_MSTP926		BIT(26)
#define HSUSB_MSTP704		BIT(4)	/* HSUSB */

int board_early_init_f(void)
{
	/* TMU0,1 */		/* which use ? */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);

#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	/* DVFS for reset */
	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
#endif
	return 0;
}

/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define	SYSC_PWRSR2	0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define	SYSC_PWRONCR2	0xE618010C

/* HSUSB block registers */
#define HSUSB_REG_LPSTS			0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
#define HSUSB_REG_UGCTRL2		0xE6590184
#define HSUSB_REG_UGCTRL2_USB0SEL	0x30
#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;

#ifdef CONFIG_SH_GPIO_PFC
	/* Init PFC controller */
#if defined(CONFIG_R8A7795)
	r8a7795_pinmux_init();
#elif defined(CONFIG_R8A7796)
	r8a7796_pinmux_init();
#endif
#endif

	/* USB1 pull-up */
	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);

	/* Configure the HSUSB block */
	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
	/* Choice USB0SEL */
	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
	/* low power status */
	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);

#ifdef CONFIG_RENESAS_RAVB
	/* EtherAVB Enable */
	/* GPSR2 */
	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
	gpio_request(GPIO_GFN_AVB_LINK, NULL);
	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
	gpio_request(GPIO_GFN_AVB_MDC, NULL);

	/* IPSR0 */
	gpio_request(GPIO_IFN_AVB_MDC, NULL);
	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
	gpio_request(GPIO_IFN_AVB_LINK, NULL);
	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
	/* IPSR1 */
	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
	/* IPSR2 */
	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
	/* IPSR3 */
	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);

	/* AVB_PHY_RST */
	gpio_request(GPIO_GP_2_10, NULL);
	gpio_direction_output(GPIO_GP_2_10, 0);
	mdelay(20);
	gpio_set_value(GPIO_GP_2_10, 1);
	udelay(1);
#endif

#ifdef CONFIG_MMC
	/* SDHI0 */
	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	gpio_request(GPIO_GFN_SD0_CLK, NULL);
	gpio_request(GPIO_GFN_SD0_CMD, NULL);
	gpio_request(GPIO_GFN_SD0_CD, NULL);
	gpio_request(GPIO_GFN_SD0_WP, NULL);

	gpio_request(GPIO_GP_5_2, NULL);
	gpio_request(GPIO_GP_5_1, NULL);
	gpio_direction_output(GPIO_GP_5_2, 1);	/* power on */
	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */

	/* SDHI1/SDHI2 eMMC */
	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	gpio_request(GPIO_GFN_SD2_CLK, NULL);
#if defined(CONFIG_R8A7795)
	gpio_request(GPIO_GFN_SD2_CMD, NULL);
#elif defined(CONFIG_R8A7796)
	gpio_request(GPIO_FN_SD2_CMD, NULL);
#else
#error Only R8A7795 and R87796 is supported
#endif
	gpio_request(GPIO_GP_5_3, NULL);
	gpio_request(GPIO_GP_5_9, NULL);
	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */
	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */
#endif

	return 0;
}

int dram_init(void)
{
	gd->ram_size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
	gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
	gd->ram_size += PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
	gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
	return 0;
}

const struct rmobile_sysinfo sysinfo = {
	CONFIG_RCAR_BOARD_STRING
};
Commit	Line	Data
bd39050c MV	1	/*
	2	* board/renesas/ulcb/ulcb.c
	3	* This file is ULCB board support.
	4	*
	5	* Copyright (C) 2017 Renesas Electronics Corporation
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#include <common.h>
	11	#include <malloc.h>
	12	#include <netdev.h>
	13	#include <dm.h>
	14	#include <dm/platform_data/serial_sh.h>
	15	#include <asm/processor.h>
	16	#include <asm/mach-types.h>
	17	#include <asm/io.h>
	18	#include <linux/errno.h>
	19	#include <asm/arch/sys_proto.h>
	20	#include <asm/gpio.h>
	21	#include <asm/arch/gpio.h>
	22	#include <asm/arch/rmobile.h>
	23	#include <asm/arch/rcar-mstp.h>
	24	#include <asm/arch/sh_sdhi.h>
	25	#include <i2c.h>
	26	#include <mmc.h>
	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	#define CPGWPCR 0xE6150904
	31	#define CPGWPR 0xE615090C
	32
	33	#define CLK2MHZ(clk) (clk / 1000 / 1000)
	34	void s_init(void)
	35	{
	36	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	37	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	38
	39	/* Watchdog init */
	40	writel(0xA5A5A500, &rwdt->rwtcsra);
	41	writel(0xA5A5A500, &swdt->swtcsra);
	42
	43	writel(0xA5A50000, CPGWPCR);
	44	writel(0xFFFFFFFF, CPGWPR);
	45	}
	46
	47	#define GSX_MSTP112 BIT(12) /* 3DG */
	48	#define TMU0_MSTP125 BIT(25) /* secure */
	49	#define TMU1_MSTP124 BIT(24) /* non-secure */
	50	#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
bd39050c	51	#define DVFS_MSTP926 BIT(26)
ef603233	52	#define HSUSB_MSTP704 BIT(4) /* HSUSB */
bd39050c	53
bd39050c MV	54	int board_early_init_f(void)
	55	{
	56	/* TMU0,1 / / which use ? */
	57	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 \| TMU1_MSTP124);
bd39050c MV	58
	59	#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	60	/* DVFS for reset */
	61	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
	62	#endif
	63	return 0;
	64	}
	65
	66	/* SYSC */
	67	/* R/- 32 Power status register 2(3DG) */
	68	#define SYSC_PWRSR2 0xE6180100
	69	/* -/W 32 Power resume control register 2 (3DG) */
	70	#define SYSC_PWRONCR2 0xE618010C
	71
ef603233 MV	72	/* HSUSB block registers */
	73	#define HSUSB_REG_LPSTS 0xE6590102
	74	#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
	75	#define HSUSB_REG_UGCTRL2 0xE6590184
	76	#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
	77	#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
	78
bd39050c MV	79	int board_init(void)
	80	{
	81	/* adress of boot parameters */
	82	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
	83
793afcde	84	#ifdef CONFIG_SH_GPIO_PFC
bd39050c MV	85	/* Init PFC controller */
	86	#if defined(CONFIG_R8A7795)
	87	r8a7795_pinmux_init();
	88	#elif defined(CONFIG_R8A7796)
	89	r8a7796_pinmux_init();
793afcde	90	#endif
bd39050c MV	91	#endif
	92
	93	/* USB1 pull-up */
	94	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC \| PUEN_USB1_PWEN);
	95
ef603233 MV	96	/* Configure the HSUSB block */
	97	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
	98	/* Choice USB0SEL */
	99	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
	100	HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
	101	/* low power status */
	102	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
	103
3158b6f6	104	#ifdef CONFIG_RENESAS_RAVB
bd39050c MV	105	/* EtherAVB Enable */
	106	/* GPSR2 */
	107	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
	108	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
	109	gpio_request(GPIO_GFN_AVB_LINK, NULL);
	110	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
	111	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
	112	gpio_request(GPIO_GFN_AVB_MDC, NULL);
	113
	114	/* IPSR0 */
	115	gpio_request(GPIO_IFN_AVB_MDC, NULL);
	116	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
	117	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
	118	gpio_request(GPIO_IFN_AVB_LINK, NULL);
	119	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
	120	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
	121	/* IPSR1 */
	122	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
	123	/* IPSR2 */
	124	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
	125	/* IPSR3 */
	126	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
	127
	128	/* AVB_PHY_RST */
	129	gpio_request(GPIO_GP_2_10, NULL);
	130	gpio_direction_output(GPIO_GP_2_10, 0);
	131	mdelay(20);
	132	gpio_set_value(GPIO_GP_2_10, 1);
	133	udelay(1);
	134	#endif
	135
8212f563	136	#ifdef CONFIG_MMC
bd39050c MV	137	/* SDHI0 */
	138	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	139	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	140	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	141	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	142	gpio_request(GPIO_GFN_SD0_CLK, NULL);
	143	gpio_request(GPIO_GFN_SD0_CMD, NULL);
	144	gpio_request(GPIO_GFN_SD0_CD, NULL);
	145	gpio_request(GPIO_GFN_SD0_WP, NULL);
	146
	147	gpio_request(GPIO_GP_5_2, NULL);
	148	gpio_request(GPIO_GP_5_1, NULL);
	149	gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
	150	gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
	151
bd39050c MV	152	/* SDHI1/SDHI2 eMMC */
	153	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	154	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	155	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	156	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	157	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	158	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	159	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	160	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	161	gpio_request(GPIO_GFN_SD2_CLK, NULL);
	162	#if defined(CONFIG_R8A7795)
	163	gpio_request(GPIO_GFN_SD2_CMD, NULL);
	164	#elif defined(CONFIG_R8A7796)
	165	gpio_request(GPIO_FN_SD2_CMD, NULL);
	166	#else
	167	#error Only R8A7795 and R87796 is supported
	168	#endif
	169	gpio_request(GPIO_GP_5_3, NULL);
	170	gpio_request(GPIO_GP_5_9, NULL);
	171	gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
	172	gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
8212f563	173	#endif
bd39050c	174
6f380854	175	return 0;
bd39050c	176	}
bd39050c MV	177
	178	int dram_init(void)
	179	{
	180	gd->ram_size = PHYS_SDRAM_1_SIZE;
	181	#if (CONFIG_NR_DRAM_BANKS >= 2)
	182	gd->ram_size += PHYS_SDRAM_2_SIZE;
	183	#endif
	184	#if (CONFIG_NR_DRAM_BANKS >= 3)
	185	gd->ram_size += PHYS_SDRAM_3_SIZE;
	186	#endif
	187	#if (CONFIG_NR_DRAM_BANKS >= 4)
	188	gd->ram_size += PHYS_SDRAM_4_SIZE;
	189	#endif
	190
	191	return 0;
	192	}
	193
	194	int dram_init_banksize(void)
	195	{
	196	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	197	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	198	#if (CONFIG_NR_DRAM_BANKS >= 2)
	199	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	200	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
	201	#endif
	202	#if (CONFIG_NR_DRAM_BANKS >= 3)
	203	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
	204	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
	205	#endif
	206	#if (CONFIG_NR_DRAM_BANKS >= 4)
	207	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
	208	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
	209	#endif
	210	return 0;
	211	}
	212
	213	const struct rmobile_sysinfo sysinfo = {
	214	CONFIG_RCAR_BOARD_STRING
	215	};