[people/ms/u-boot.git] / board / ronetix / pm9261 / pm9261.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>

#include <lcd.h>
#include <atmel_lcdc.h>
#include <dataflash.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#endif
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void pm9261_nand_hw_init(void)
{
	unsigned long csa;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	/* Enable CS3 */
	csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
	writel(csa, &matrix->csa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);

	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);

	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		AT91_SMC_MODE_DBW_8 |
#endif
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	writel(1 << ATMEL_ID_PIOA |
		1 << ATMEL_ID_PIOC,
		&pmc->pcer);

	/* Configure RDY/BSY */
	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);

	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
}
#endif


#ifdef CONFIG_DRIVER_DM9000
static void pm9261_dm9000_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	/* Configure SMC CS2 for DM9000 */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[2].setup);

	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
		&smc->cs[2].pulse);

	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
		&smc->cs[2].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
		AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
		AT91_SMC_MODE_TDF_CYCLE(1),
		&smc->cs[2].mode);

	/* Configure Interrupt pin as input, no pull-up */
	writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	vl_col:		240,
	vl_row:		320,
	vl_clk:		4965000,
	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
			ATMEL_LCDC_INVFRAME_INVERTED,
	vl_bpix:	3,
	vl_tft:		1,
	vl_hsync_len:	5,
	vl_left_margin:	1,
	vl_right_margin:33,
	vl_vsync_len:	1,
	vl_upper_margin:1,
	vl_lower_margin:0,
	mmio:		ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
}

void lcd_disable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
}

static void pm9261_lcd_hw_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* LCDHSYNC */
	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* LCDDOTCK */
	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* LCDDEN */
	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* LCDCC */
	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* LCDD2 */
	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* LCDD3 */
	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* LCDD4 */
	at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* LCDD5 */
	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* LCDD6 */
	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* LCDD7 */
	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* LCDD10 */
	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* LCDD11 */
	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* LCDD12 */
	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* LCDD13 */
	at91_set_a_periph(AT91_PIO_PORTB, 19, 0);	/* LCDD14 */
	at91_set_a_periph(AT91_PIO_PORTB, 20, 0);	/* LCDD15 */
	at91_set_b_periph(AT91_PIO_PORTB, 23, 0);	/* LCDD18 */
	at91_set_b_periph(AT91_PIO_PORTB, 24, 0);	/* LCDD19 */
	at91_set_b_periph(AT91_PIO_PORTB, 25, 0);	/* LCDD20 */
	at91_set_b_periph(AT91_PIO_PORTB, 26, 0);	/* LCDD21 */
	at91_set_b_periph(AT91_PIO_PORTB, 27, 0);	/* LCDD22 */
	at91_set_b_periph(AT91_PIO_PORTB, 28, 0);	/* LCDD23 */

	writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */

	gd->fb_base = ATMEL_BASE_SRAM;
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

extern flash_info_t flash_info[];

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size, flash_size, dataflash_size;
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	lcd_printf ("support@ronetix.at\n");
	lcd_printf ("%s CPU at %s MHz",
		CONFIG_SYS_AT91_CPU_NAME,
		strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i].size;

	flash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
		flash_size += flash_info[i].size;

	dataflash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
				dataflash_info[i].Device.pages_size;

	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
			"%ld MB DataFlash\n",
		dram_size >> 20,
		nand_size >> 20,
		flash_size >> 20,
		dataflash_size >> 20);
}
#endif /* CONFIG_LCD_INFO */

#endif /* CONFIG_LCD */

int board_early_init_f(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	/* Enable clocks for some PIOs */
	writel(1 << ATMEL_ID_PIOA |
		1 << ATMEL_ID_PIOC,
		&pmc->pcer);

	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* arch number of PM9261-Board */
	gd->bd->bi_arch_number = MACH_TYPE_PM9261;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_CMD_NAND
	pm9261_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_DRIVER_DM9000
	pm9261_dm9000_hw_init();
#endif
#ifdef CONFIG_LCD
	pm9261_lcd_hw_init();
#endif
	return 0;
}

#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
	return dm9000_initialize(bis);
}
#endif

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
				PHYS_SDRAM_SIZE);
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
	/*
	 * Initialize ethernet HW addr prior to starting Linux,
	 * needed for nfsroot
	 */
	eth_init(gd->bd);
#endif
}
#endif

#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard (void)
{
	char buf[32];

	printf ("Board : Ronetix PM9261\n");
	printf ("Crystal frequency: %8s MHz\n",
					strmhz(buf, get_main_clk_rate()));
	printf ("CPU clock        : %8s MHz\n",
					strmhz(buf, get_cpu_clk_rate()));
	printf ("Master clock     : %8s MHz\n",
					strmhz(buf, get_mck_clk_rate()));

	return 0;
}
#endif
Commit	Line	Data
32949232 II	1	/*
32949232 II	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
32949232 II	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
	6	* Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
32949232 II	9	*/
	10
	11	#include <common.h>
	12	#include <asm/sizes.h>
f47316a8	13	#include <asm/io.h>
32949232 II	14	#include <asm/arch/at91sam9_smc.h>
	15	#include <asm/arch/at91_common.h>
	16	#include <asm/arch/at91_pmc.h>
	17	#include <asm/arch/at91_rstc.h>
e3150c77	18	#include <asm/arch/at91_matrix.h>
32949232	19	#include <asm/arch/clk.h>
f47316a8 AD	20	#include <asm/arch/gpio.h>
f47316a8 AD	21
32949232 II	22	#include <lcd.h>
	23	#include <atmel_lcdc.h>
	24	#include <dataflash.h>
	25	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
	26	#include <net.h>
	27	#endif
	28	#include <netdev.h>
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	/* ------------------------------------------------------------------------- */
	33	/*
	34	* Miscelaneous platform dependent initialisations
	35	*/
	36
	37	#ifdef CONFIG_CMD_NAND
	38	static void pm9261_nand_hw_init(void)
	39	{
	40	unsigned long csa;
f47316a8 AD	41	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	42	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
	43	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
32949232 II	44
32949232 II	45	/* Enable CS3 */
e3150c77 AD	46	csa = readl(&matrix->csa) \| AT91_MATRIX_CSA_EBI_CS3A;
e3150c77 AD	47	writel(csa, &matrix->csa);
32949232 II	48
32949232 II	49	/* Configure SMC CS3 for NAND/SmartMedia */
e3150c77 AD	50	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	51	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	52	&smc->cs[3].setup);
	53
	54	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	55	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	56	&smc->cs[3].pulse);
	57
	58	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	59	&smc->cs[3].cycle);
	60
	61	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	62	AT91_SMC_MODE_EXNW_DISABLE \|
32949232	63	#ifdef CONFIG_SYS_NAND_DBW_16
e3150c77	64	AT91_SMC_MODE_DBW_16 \|
32949232	65	#else /* CONFIG_SYS_NAND_DBW_8 */
e3150c77	66	AT91_SMC_MODE_DBW_8 \|
32949232	67	#endif
e3150c77 AD	68	AT91_SMC_MODE_TDF_CYCLE(2),
	69	&smc->cs[3].mode);
	70
f47316a8 AD	71	writel(1 << ATMEL_ID_PIOA \|
f47316a8 AD	72	1 << ATMEL_ID_PIOC,
e3150c77	73	&pmc->pcer);
32949232 II	74
32949232 II	75	/* Configure RDY/BSY */
e3150c77	76	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
32949232 II	77
32949232 II	78	/* Enable NandFlash */
e3150c77	79	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
32949232	80
e3150c77 AD	81	at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
e3150c77 AD	82	at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
32949232 II	83	}
	84	#endif
	85
	86
	87	#ifdef CONFIG_DRIVER_DM9000
	88	static void pm9261_dm9000_hw_init(void)
	89	{
f47316a8 AD	90	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
f47316a8 AD	91	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
e3150c77	92
32949232	93	/* Configure SMC CS2 for DM9000 */
e3150c77 AD	94	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(0) \|
	95	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	96	&smc->cs[2].setup);
	97
	98	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(8) \|
	99	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(8),
	100	&smc->cs[2].pulse);
	101
	102	writel(AT91_SMC_CYCLE_NWE(16) \| AT91_SMC_CYCLE_NRD(16),
	103	&smc->cs[2].cycle);
	104
	105	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	106	AT91_SMC_MODE_EXNW_DISABLE \|
	107	AT91_SMC_MODE_BAT \| AT91_SMC_MODE_DBW_16 \|
	108	AT91_SMC_MODE_TDF_CYCLE(1),
	109	&smc->cs[2].mode);
32949232 II	110
32949232 II	111	/* Configure Interrupt pin as input, no pull-up */
f47316a8	112	writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
e3150c77	113	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
32949232 II	114	}
	115	#endif
	116
	117	#ifdef CONFIG_LCD
	118	vidinfo_t panel_info = {
	119	vl_col: 240,
	120	vl_row: 320,
	121	vl_clk: 4965000,
	122	vl_sync: ATMEL_LCDC_INVLINE_INVERTED \|
	123	ATMEL_LCDC_INVFRAME_INVERTED,
	124	vl_bpix: 3,
	125	vl_tft: 1,
	126	vl_hsync_len: 5,
	127	vl_left_margin: 1,
	128	vl_right_margin:33,
	129	vl_vsync_len: 1,
	130	vl_upper_margin:1,
	131	vl_lower_margin:0,
f47316a8	132	mmio: ATMEL_BASE_LCDC,
32949232 II	133	};
	134
	135	void lcd_enable(void)
	136	{
e3150c77	137	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
32949232 II	138	}
	139
	140	void lcd_disable(void)
	141	{
e3150c77	142	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
32949232 II	143	}
	144
	145	static void pm9261_lcd_hw_init(void)
	146	{
f47316a8	147	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
e3150c77 AD	148
	149	at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
	150	at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
	151	at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
	152	at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
	153	at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
	154	at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
	155	at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
	156	at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
	157	at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
	158	at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
	159	at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
	160	at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
	161	at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
	162	at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
	163	at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
	164	at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
	165	at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
	166	at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
	167	at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
	168	at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
	169	at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
	170	at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
	171
	172	writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
32949232	173
f47316a8	174	gd->fb_base = ATMEL_BASE_SRAM;
32949232 II	175	}
	176
	177	#ifdef CONFIG_LCD_INFO
	178	#include <nand.h>
	179	#include <version.h>
	180
	181	extern flash_info_t flash_info[];
	182
	183	void lcd_show_board_info(void)
	184	{
	185	ulong dram_size, nand_size, flash_size, dataflash_size;
	186	int i;
	187	char temp[32];
	188
	189	lcd_printf ("%s\n", U_BOOT_VERSION);
	190	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	191	lcd_printf ("support@ronetix.at\n");
	192	lcd_printf ("%s CPU at %s MHz",
7c966a8b	193	CONFIG_SYS_AT91_CPU_NAME,
32949232 II	194	strmhz(temp, get_cpu_clk_rate()));
	195
	196	dram_size = 0;
	197	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	198	dram_size += gd->bd->bi_dram[i].size;
	199
	200	nand_size = 0;
	201	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
	202	nand_size += nand_info[i].size;
	203
	204	flash_size = 0;
	205	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
	206	flash_size += flash_info[i].size;
	207
	208	dataflash_size = 0;
	209	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
	210	dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
	211	dataflash_info[i].Device.pages_size;
	212
	213	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
	214	"%ld MB DataFlash\n",
	215	dram_size >> 20,
	216	nand_size >> 20,
	217	flash_size >> 20,
	218	dataflash_size >> 20);
	219	}
	220	#endif /* CONFIG_LCD_INFO */
	221
	222	#endif /* CONFIG_LCD */
	223
0160c1e1	224	int board_early_init_f(void)
32949232	225	{
f47316a8	226	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
e3150c77	227
0160c1e1	228	/* Enable clocks for some PIOs */
f47316a8 AD	229	writel(1 << ATMEL_ID_PIOA \|
f47316a8 AD	230	1 << ATMEL_ID_PIOC,
e3150c77	231	&pmc->pcer);
32949232	232
0160c1e1 AD	233	at91_seriald_hw_init();
	234
	235	return 0;
	236	}
	237
	238	int board_init(void)
	239	{
	240	/* arch number of PM9261-Board */
	241	gd->bd->bi_arch_number = MACH_TYPE_PM9261;
	242
32949232 II	243	/* adress of boot parameters */
	244	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	245
32949232 II	246	#ifdef CONFIG_CMD_NAND
	247	pm9261_nand_hw_init();
	248	#endif
	249	#ifdef CONFIG_HAS_DATAFLASH
	250	at91_spi0_hw_init(1 << 0);
	251	#endif
	252	#ifdef CONFIG_DRIVER_DM9000
	253	pm9261_dm9000_hw_init();
	254	#endif
	255	#ifdef CONFIG_LCD
	256	pm9261_lcd_hw_init();
	257	#endif
	258	return 0;
	259	}
	260
e830b66b II	261	#ifdef CONFIG_DRIVER_DM9000
	262	int board_eth_init(bd_t *bis)
	263	{
	264	return dm9000_initialize(bis);
	265	}
	266	#endif
	267
32949232	268	int dram_init(void)
4f81bf43 AD	269	{
4f81bf43 AD	270	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	271	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
4f81bf43 AD	272	PHYS_SDRAM_SIZE);
	273	return 0;
	274	}
	275
	276	void dram_init_banksize(void)
32949232 II	277	{
	278	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	279	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
32949232 II	280	}
	281
	282	#ifdef CONFIG_RESET_PHY_R
	283	void reset_phy(void)
	284	{
	285	#ifdef CONFIG_DRIVER_DM9000
	286	/*
	287	* Initialize ethernet HW addr prior to starting Linux,
	288	* needed for nfsroot
	289	*/
	290	eth_init(gd->bd);
	291	#endif
	292	}
	293	#endif
	294
	295	#ifdef CONFIG_DISPLAY_BOARDINFO
	296	int checkboard (void)
	297	{
	298	char buf[32];
	299
	300	printf ("Board : Ronetix PM9261\n");
	301	printf ("Crystal frequency: %8s MHz\n",
	302	strmhz(buf, get_main_clk_rate()));
	303	printf ("CPU clock : %8s MHz\n",
	304	strmhz(buf, get_cpu_clk_rate()));
	305	printf ("Master clock : %8s MHz\n",
	306	strmhz(buf, get_mck_clk_rate()));
	307
	308	return 0;
	309	}
	310	#endif