[people/ms/u-boot.git] / board / ronetix / pm9261 / pm9261.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>

#include <lcd.h>
#include <atmel_lcdc.h>
#include <dataflash.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#endif
#include <netdev.h>
#include <asm/mach-types.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void pm9261_nand_hw_init(void)
{
	unsigned long csa;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	/* Enable CS3 */
	csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
	writel(csa, &matrix->csa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);

	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);

	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		AT91_SMC_MODE_DBW_8 |
#endif
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOC);

	/* Configure RDY/BSY */
	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);

	/* Enable NandFlash */
	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);

	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
}
#endif


#ifdef CONFIG_DRIVER_DM9000
static void pm9261_dm9000_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	/* Configure SMC CS2 for DM9000 */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[2].setup);

	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
		&smc->cs[2].pulse);

	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
		&smc->cs[2].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
		AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
		AT91_SMC_MODE_TDF_CYCLE(1),
		&smc->cs[2].mode);

	/* Configure Interrupt pin as input, no pull-up */
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col =		240,
	.vl_row =		320,
	.vl_clk =		4965000,
	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
				ATMEL_LCDC_INVFRAME_INVERTED,
	.vl_bpix =		3,
	.vl_tft =		1,
	.vl_hsync_len =		5,
	.vl_left_margin =	1,
	.vl_right_margin =	33,
	.vl_vsync_len =		1,
	.vl_upper_margin =	1,
	.vl_lower_margin =	0,
	.mmio =			ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
}

void lcd_disable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
}

static void pm9261_lcd_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* LCDHSYNC */
	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* LCDDOTCK */
	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* LCDDEN */
	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* LCDCC */
	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* LCDD2 */
	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* LCDD3 */
	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* LCDD4 */
	at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* LCDD5 */
	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* LCDD6 */
	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* LCDD7 */
	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* LCDD10 */
	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* LCDD11 */
	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* LCDD12 */
	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* LCDD13 */
	at91_set_a_periph(AT91_PIO_PORTB, 19, 0);	/* LCDD14 */
	at91_set_a_periph(AT91_PIO_PORTB, 20, 0);	/* LCDD15 */
	at91_set_b_periph(AT91_PIO_PORTB, 23, 0);	/* LCDD18 */
	at91_set_b_periph(AT91_PIO_PORTB, 24, 0);	/* LCDD19 */
	at91_set_b_periph(AT91_PIO_PORTB, 25, 0);	/* LCDD20 */
	at91_set_b_periph(AT91_PIO_PORTB, 26, 0);	/* LCDD21 */
	at91_set_b_periph(AT91_PIO_PORTB, 27, 0);	/* LCDD22 */
	at91_set_b_periph(AT91_PIO_PORTB, 28, 0);	/* LCDD23 */

	at91_system_clk_enable(AT91_PMC_HCK1);

	gd->fb_base = ATMEL_BASE_SRAM;
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

extern flash_info_t flash_info[];

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size, flash_size, dataflash_size;
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	lcd_printf ("support@ronetix.at\n");
	lcd_printf ("%s CPU at %s MHz",
		CONFIG_SYS_AT91_CPU_NAME,
		strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i]->size;

	flash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
		flash_size += flash_info[i].size;

	dataflash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
				dataflash_info[i].Device.pages_size;

	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
			"%ld MB DataFlash\n",
		dram_size >> 20,
		nand_size >> 20,
		flash_size >> 20,
		dataflash_size >> 20);
}
#endif /* CONFIG_LCD_INFO */

#endif /* CONFIG_LCD */

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOC);

	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* arch number of PM9261-Board */
	gd->bd->bi_arch_number = MACH_TYPE_PM9261;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_CMD_NAND
	pm9261_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_DRIVER_DM9000
	pm9261_dm9000_hw_init();
#endif
#ifdef CONFIG_LCD
	pm9261_lcd_hw_init();
#endif
	return 0;
}

#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
	return dm9000_initialize(bis);
}
#endif

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
				PHYS_SDRAM_SIZE);
	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
	/*
	 * Initialize ethernet HW addr prior to starting Linux,
	 * needed for nfsroot
	 */
	eth_init();
#endif
}
#endif

#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard (void)
{
	char buf[32];

	printf ("Board : Ronetix PM9261\n");
	printf ("Crystal frequency: %8s MHz\n",
					strmhz(buf, get_main_clk_rate()));
	printf ("CPU clock        : %8s MHz\n",
					strmhz(buf, get_cpu_clk_rate()));
	printf ("Master clock     : %8s MHz\n",
					strmhz(buf, get_mck_clk_rate()));

	return 0;
}
#endif
Commit	Line	Data
32949232 II	1	/*
32949232 II	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
32949232 II	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
	6	* Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
32949232 II	9	*/
	10
	11	#include <common.h>
1ace4022	12	#include <linux/sizes.h>
f47316a8	13	#include <asm/io.h>
ac45bb16	14	#include <asm/gpio.h>
32949232 II	15	#include <asm/arch/at91sam9_smc.h>
32949232 II	16	#include <asm/arch/at91_common.h>
32949232	17	#include <asm/arch/at91_rstc.h>
e3150c77	18	#include <asm/arch/at91_matrix.h>
32949232	19	#include <asm/arch/clk.h>
f47316a8 AD	20	#include <asm/arch/gpio.h>
f47316a8 AD	21
32949232 II	22	#include <lcd.h>
	23	#include <atmel_lcdc.h>
	24	#include <dataflash.h>
	25	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
	26	#include <net.h>
	27	#endif
	28	#include <netdev.h>
c62db35d	29	#include <asm/mach-types.h>
32949232 II	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	/* ------------------------------------------------------------------------- */
	34	/*
	35	* Miscelaneous platform dependent initialisations
	36	*/
	37
	38	#ifdef CONFIG_CMD_NAND
	39	static void pm9261_nand_hw_init(void)
	40	{
	41	unsigned long csa;
f47316a8 AD	42	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
f47316a8 AD	43	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
32949232 II	44
32949232 II	45	/* Enable CS3 */
e3150c77 AD	46	csa = readl(&matrix->csa) \| AT91_MATRIX_CSA_EBI_CS3A;
e3150c77 AD	47	writel(csa, &matrix->csa);
32949232 II	48
32949232 II	49	/* Configure SMC CS3 for NAND/SmartMedia */
e3150c77 AD	50	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	51	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	52	&smc->cs[3].setup);
	53
	54	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	55	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	56	&smc->cs[3].pulse);
	57
	58	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	59	&smc->cs[3].cycle);
	60
	61	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	62	AT91_SMC_MODE_EXNW_DISABLE \|
32949232	63	#ifdef CONFIG_SYS_NAND_DBW_16
e3150c77	64	AT91_SMC_MODE_DBW_16 \|
32949232	65	#else /* CONFIG_SYS_NAND_DBW_8 */
e3150c77	66	AT91_SMC_MODE_DBW_8 \|
32949232	67	#endif
e3150c77 AD	68	AT91_SMC_MODE_TDF_CYCLE(2),
	69	&smc->cs[3].mode);
	70
70341e2e WY	71	at91_periph_clk_enable(ATMEL_ID_PIOA);
70341e2e WY	72	at91_periph_clk_enable(ATMEL_ID_PIOC);
32949232 II	73
32949232 II	74	/* Configure RDY/BSY */
ac45bb16	75	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
32949232 II	76
32949232 II	77	/* Enable NandFlash */
ac45bb16	78	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
32949232	79
e3150c77 AD	80	at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
e3150c77 AD	81	at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
32949232 II	82	}
	83	#endif
	84
	85
	86	#ifdef CONFIG_DRIVER_DM9000
	87	static void pm9261_dm9000_hw_init(void)
	88	{
f47316a8	89	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
e3150c77	90
32949232	91	/* Configure SMC CS2 for DM9000 */
e3150c77 AD	92	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(0) \|
	93	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	94	&smc->cs[2].setup);
	95
	96	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(8) \|
	97	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(8),
	98	&smc->cs[2].pulse);
	99
	100	writel(AT91_SMC_CYCLE_NWE(16) \| AT91_SMC_CYCLE_NRD(16),
	101	&smc->cs[2].cycle);
	102
	103	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	104	AT91_SMC_MODE_EXNW_DISABLE \|
	105	AT91_SMC_MODE_BAT \| AT91_SMC_MODE_DBW_16 \|
	106	AT91_SMC_MODE_TDF_CYCLE(1),
	107	&smc->cs[2].mode);
32949232 II	108
32949232 II	109	/* Configure Interrupt pin as input, no pull-up */
70341e2e	110	at91_periph_clk_enable(ATMEL_ID_PIOA);
e3150c77	111	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
32949232 II	112	}
	113	#endif
	114
	115	#ifdef CONFIG_LCD
	116	vidinfo_t panel_info = {
c346e466 JH	117	.vl_col = 240,
	118	.vl_row = 320,
	119	.vl_clk = 4965000,
	120	.vl_sync = ATMEL_LCDC_INVLINE_INVERTED \|
	121	ATMEL_LCDC_INVFRAME_INVERTED,
	122	.vl_bpix = 3,
	123	.vl_tft = 1,
	124	.vl_hsync_len = 5,
	125	.vl_left_margin = 1,
	126	.vl_right_margin = 33,
	127	.vl_vsync_len = 1,
	128	.vl_upper_margin = 1,
	129	.vl_lower_margin = 0,
	130	.mmio = ATMEL_BASE_LCDC,
32949232 II	131	};
	132
	133	void lcd_enable(void)
	134	{
e3150c77	135	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
32949232 II	136	}
	137
	138	void lcd_disable(void)
	139	{
e3150c77	140	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
32949232 II	141	}
	142
	143	static void pm9261_lcd_hw_init(void)
	144	{
e3150c77 AD	145	at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
	146	at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
	147	at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
	148	at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
	149	at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
	150	at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
	151	at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
	152	at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
	153	at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
	154	at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
	155	at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
	156	at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
	157	at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
	158	at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
	159	at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
	160	at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
	161	at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
	162	at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
	163	at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
	164	at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
	165	at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
	166	at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
	167
70341e2e	168	at91_system_clk_enable(AT91_PMC_HCK1);
32949232	169
f47316a8	170	gd->fb_base = ATMEL_BASE_SRAM;
32949232 II	171	}
	172
	173	#ifdef CONFIG_LCD_INFO
	174	#include <nand.h>
	175	#include <version.h>
	176
	177	extern flash_info_t flash_info[];
	178
	179	void lcd_show_board_info(void)
	180	{
	181	ulong dram_size, nand_size, flash_size, dataflash_size;
	182	int i;
	183	char temp[32];
	184
	185	lcd_printf ("%s\n", U_BOOT_VERSION);
	186	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	187	lcd_printf ("support@ronetix.at\n");
	188	lcd_printf ("%s CPU at %s MHz",
7c966a8b	189	CONFIG_SYS_AT91_CPU_NAME,
32949232 II	190	strmhz(temp, get_cpu_clk_rate()));
	191
	192	dram_size = 0;
	193	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	194	dram_size += gd->bd->bi_dram[i].size;
	195
	196	nand_size = 0;
	197	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
b616d9b0	198	nand_size += nand_info[i]->size;
32949232 II	199
	200	flash_size = 0;
	201	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
	202	flash_size += flash_info[i].size;
	203
	204	dataflash_size = 0;
	205	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
	206	dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
	207	dataflash_info[i].Device.pages_size;
	208
	209	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
	210	"%ld MB DataFlash\n",
	211	dram_size >> 20,
	212	nand_size >> 20,
	213	flash_size >> 20,
	214	dataflash_size >> 20);
	215	}
	216	#endif /* CONFIG_LCD_INFO */
	217
	218	#endif /* CONFIG_LCD */
	219
0160c1e1	220	int board_early_init_f(void)
32949232	221	{
70341e2e WY	222	at91_periph_clk_enable(ATMEL_ID_PIOA);
70341e2e WY	223	at91_periph_clk_enable(ATMEL_ID_PIOC);
32949232	224
0160c1e1 AD	225	at91_seriald_hw_init();
	226
	227	return 0;
	228	}
	229
	230	int board_init(void)
	231	{
	232	/* arch number of PM9261-Board */
	233	gd->bd->bi_arch_number = MACH_TYPE_PM9261;
	234
32949232 II	235	/* adress of boot parameters */
	236	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	237
32949232 II	238	#ifdef CONFIG_CMD_NAND
	239	pm9261_nand_hw_init();
	240	#endif
	241	#ifdef CONFIG_HAS_DATAFLASH
	242	at91_spi0_hw_init(1 << 0);
	243	#endif
	244	#ifdef CONFIG_DRIVER_DM9000
	245	pm9261_dm9000_hw_init();
	246	#endif
	247	#ifdef CONFIG_LCD
	248	pm9261_lcd_hw_init();
	249	#endif
	250	return 0;
	251	}
	252
e830b66b II	253	#ifdef CONFIG_DRIVER_DM9000
	254	int board_eth_init(bd_t *bis)
	255	{
	256	return dm9000_initialize(bis);
	257	}
	258	#endif
	259
32949232	260	int dram_init(void)
4f81bf43 AD	261	{
4f81bf43 AD	262	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	263	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
4f81bf43 AD	264	PHYS_SDRAM_SIZE);
	265	return 0;
	266	}
	267
76b00aca	268	int dram_init_banksize(void)
32949232 II	269	{
	270	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	271	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
76b00aca SG	272
76b00aca SG	273	return 0;
32949232 II	274	}
	275
	276	#ifdef CONFIG_RESET_PHY_R
	277	void reset_phy(void)
	278	{
	279	#ifdef CONFIG_DRIVER_DM9000
	280	/*
	281	* Initialize ethernet HW addr prior to starting Linux,
	282	* needed for nfsroot
	283	*/
d2eaec60	284	eth_init();
32949232 II	285	#endif
	286	}
	287	#endif
	288
	289	#ifdef CONFIG_DISPLAY_BOARDINFO
	290	int checkboard (void)
	291	{
	292	char buf[32];
	293
	294	printf ("Board : Ronetix PM9261\n");
	295	printf ("Crystal frequency: %8s MHz\n",
	296	strmhz(buf, get_main_clk_rate()));
	297	printf ("CPU clock : %8s MHz\n",
	298	strmhz(buf, get_cpu_clk_rate()));
	299	printf ("Master clock : %8s MHz\n",
	300	strmhz(buf, get_mck_clk_rate()));
	301
	302	return 0;
	303	}
	304	#endif