[people/ms/u-boot.git] / board / ronetix / pm9263 / pm9263.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#include <dataflash.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void pm9263_nand_hw_init(void)
{
	unsigned long csa;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	/* Enable CS3 */
	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
	writel(csa, &matrix->csa[0]);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
		&smc->cs[3].setup);

	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);

	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		AT91_SMC_MODE_DBW_8 |
#endif
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	/* Configure RDY/BSY */
	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);

	/* Enable NandFlash */
	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

#ifdef CONFIG_MACB
static void pm9263_macb_hw_init(void)
{
	/*
	 * PB27 enables the 50MHz oscillator for Ethernet PHY
	 * 1 - enable
	 * 0 - disable
	 */
	at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
	at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */

	at91_periph_clk_enable(ATMEL_ID_EMAC);

	/*
	 * Disable pull-up on:
	 *	RXDV (PC25) => PHY normal mode (not Test mode)
	 *	ERX0 (PE25) => PHY ADDR0
	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */

	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);

	/* Re-enable pull-up */
	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);

	at91_macb_hw_init();
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col =		240,
	.vl_row =		320,
	.vl_clk =		4965000,
	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
					ATMEL_LCDC_INVFRAME_INVERTED,
	.vl_bpix =		3,
	.vl_tft =		1,
	.vl_hsync_len =		5,
	.vl_left_margin =	1,
	.vl_right_margin =	33,
	.vl_vsync_len =		1,
	.vl_upper_margin =	1,
	.vl_lower_margin =	0,
	.mmio =			ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
}

void lcd_disable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
}

#ifdef CONFIG_LCD_IN_PSRAM

#define PSRAM_CRE_PIN	AT91_PIO_PORTB, 29
#define PSRAM_CTRL_REG	(PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)

/* Initialize the PSRAM memory */
static int pm9263_lcd_hw_psram_init(void)
{
	unsigned long csa;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	/* Enable CS3  3.3v, no pull-ups */
	csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
		AT91_MATRIX_CSA_VDDIOMSEL_3_3V;

	writel(csa, &matrix->csa[1]);

	/* Configure SMC1 CS0 for PSRAM - 16-bit */
	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[0].setup);

	writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
		AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
		&smc->cs[0].pulse);

	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
		&smc->cs[0].cycle);

	writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
		&smc->cs[0].mode);

	/* setup PB29 as output */
	at91_set_pio_output(PSRAM_CRE_PIN, 1);

	at91_set_pio_value(PSRAM_CRE_PIN, 0);	/* set PSRAM_CRE_PIN to '0' */

	/* PSRAM: write BCR */
	readw(PSRAM_CTRL_REG);
	readw(PSRAM_CTRL_REG);
	writew(1, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
	writew(0x9d4f, PSRAM_CTRL_REG);	/* write the BCR */

	/* write RCR of the PSRAM */
	readw(PSRAM_CTRL_REG);
	readw(PSRAM_CTRL_REG);
	writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
	/* set RCR; 0x10-async mode,0x90-page mode */
	writew(0x90, PSRAM_CTRL_REG);

	/*
	 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
	 * MT45W2M16B - CRE must be 0
	 * MT45W2M16A - CRE must be 1
	 */
	writew(0x1234, PHYS_PSRAM);
	writew(0x5678, PHYS_PSRAM + 2);

	/* test if the chip is MT45W2M16B */
	if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
		/* try with CRE=1 (MT45W2M16A) */
		at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */

		/* write RCR of the PSRAM */
		readw(PSRAM_CTRL_REG);
		readw(PSRAM_CTRL_REG);
		writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
		/* set RCR;0x10-async mode,0x90-page mode */
		writew(0x90, PSRAM_CTRL_REG);


		writew(0x1234, PHYS_PSRAM);
		writew(0x5678, PHYS_PSRAM+2);
		if ((readw(PHYS_PSRAM) != 0x1234)
		  || (readw(PHYS_PSRAM + 2) != 0x5678))
			return 1;

	}

	/* Bus matrix */
	writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
	writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);

	return 0;
}
#endif

static void pm9263_lcd_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */

	at91_periph_clk_enable(ATMEL_ID_LCDC);

	/* Power Control */
	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);	/* power down */

#ifdef CONFIG_LCD_IN_PSRAM
	/* initialize te PSRAM */
	int stat = pm9263_lcd_hw_psram_init();

	gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
#else
	gd->fb_base = ATMEL_BASE_SRAM0;
#endif

}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

extern flash_info_t flash_info[];

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size, flash_size, dataflash_size;
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	lcd_printf ("support@ronetix.at\n");
	lcd_printf ("%s CPU at %s MHz",
		CONFIG_SYS_AT91_CPU_NAME,
		strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i]->size;

	flash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
		flash_size += flash_info[i].size;

	dataflash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
				dataflash_info[i].Device.pages_size;

	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
			"4 MB PSRAM, %ld MB DataFlash\n",
		dram_size >> 20,
		nand_size >> 20,
		flash_size >> 20,
		dataflash_size >> 20);
}
#endif /* CONFIG_LCD_INFO */

#endif /* CONFIG_LCD */

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOCDE);

	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* arch number of AT91SAM9263EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_PM9263;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_CMD_NAND
	pm9263_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
	pm9263_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
	at91_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
	pm9263_lcd_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
				PHYS_SDRAM_SIZE);
	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
}
#endif

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
#endif
	return rc;
}

#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard (void)
{
	char *ss;

	printf ("Board : Ronetix PM9263\n");

	switch (gd->fb_base) {
	case PHYS_PSRAM:
		ss = "(PSRAM)";
		break;

	case ATMEL_BASE_SRAM0:
		ss = "(Internal SRAM)";
		break;

	default:
		ss = "";
		break;
	}
	printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );

	printf ("\n");
	return 0;
}
#endif
Commit	Line	Data
f0a2c7b4 II	1	/*
f0a2c7b4 II	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
f0a2c7b4 II	4	* Lead Tech Design <www.leadtechdesign.com>
	5	* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
	6	* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
f0a2c7b4 II	9	*/
	10
	11	#include <common.h>
1ace4022	12	#include <linux/sizes.h>
684a567a	13	#include <asm/io.h>
ac45bb16	14	#include <asm/gpio.h>
f0a2c7b4 II	15	#include <asm/arch/at91sam9_smc.h>
f0a2c7b4 II	16	#include <asm/arch/at91_common.h>
f0a2c7b4	17	#include <asm/arch/at91_rstc.h>
20d98c2c	18	#include <asm/arch/at91_matrix.h>
f0a2c7b4	19	#include <asm/arch/clk.h>
684a567a	20	#include <asm/arch/gpio.h>
f0a2c7b4 II	21	#include <lcd.h>
	22	#include <atmel_lcdc.h>
	23	#include <dataflash.h>
	24	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
	25	#include <net.h>
	26	#endif
	27	#include <netdev.h>
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	/* ------------------------------------------------------------------------- */
	32	/*
	33	* Miscelaneous platform dependent initialisations
	34	*/
	35
	36	#ifdef CONFIG_CMD_NAND
	37	static void pm9263_nand_hw_init(void)
	38	{
	39	unsigned long csa;
684a567a AD	40	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC0;
684a567a AD	41	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
f0a2c7b4 II	42
f0a2c7b4 II	43	/* Enable CS3 */
20d98c2c AD	44	csa = readl(&matrix->csa[0]) \| AT91_MATRIX_CSA_EBI_CS3A;
20d98c2c AD	45	writel(csa, &matrix->csa[0]);
f0a2c7b4 II	46
f0a2c7b4 II	47	/* Configure SMC CS3 for NAND/SmartMedia */
20d98c2c AD	48	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(1) \|
	49	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(1),
	50	&smc->cs[3].setup);
	51
	52	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	53	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	54	&smc->cs[3].pulse);
	55
	56	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	57	&smc->cs[3].cycle);
	58
	59	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	60	AT91_SMC_MODE_EXNW_DISABLE \|
f0a2c7b4	61	#ifdef CONFIG_SYS_NAND_DBW_16
20d98c2c	62	AT91_SMC_MODE_DBW_16 \|
f0a2c7b4	63	#else /* CONFIG_SYS_NAND_DBW_8 */
20d98c2c	64	AT91_SMC_MODE_DBW_8 \|
f0a2c7b4	65	#endif
20d98c2c AD	66	AT91_SMC_MODE_TDF_CYCLE(2),
20d98c2c AD	67	&smc->cs[3].mode);
f0a2c7b4 II	68
f0a2c7b4 II	69	/* Configure RDY/BSY */
ac45bb16	70	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
f0a2c7b4 II	71
f0a2c7b4 II	72	/* Enable NandFlash */
ac45bb16	73	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
f0a2c7b4 II	74	}
	75	#endif
	76
	77	#ifdef CONFIG_MACB
	78	static void pm9263_macb_hw_init(void)
	79	{
	80	/*
	81	* PB27 enables the 50MHz oscillator for Ethernet PHY
	82	* 1 - enable
	83	* 0 - disable
	84	*/
20d98c2c AD	85	at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
20d98c2c AD	86	at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
f0a2c7b4	87
70341e2e	88	at91_periph_clk_enable(ATMEL_ID_EMAC);
f0a2c7b4 II	89
	90	/*
	91	* Disable pull-up on:
	92	* RXDV (PC25) => PHY normal mode (not Test mode)
	93	* ERX0 (PE25) => PHY ADDR0
	94	* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	95	*
	96	* PHY has internal pull-down
	97	*/
f0a2c7b4	98
20d98c2c AD	99	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
	100	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
	101	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
f0a2c7b4 II	102
f0a2c7b4 II	103	/* Re-enable pull-up */
20d98c2c AD	104	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
	105	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
	106	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
f0a2c7b4 II	107
	108	at91_macb_hw_init();
	109	}
	110	#endif
	111
	112	#ifdef CONFIG_LCD
	113	vidinfo_t panel_info = {
1b34e880 JH	114	.vl_col = 240,
	115	.vl_row = 320,
	116	.vl_clk = 4965000,
	117	.vl_sync = ATMEL_LCDC_INVLINE_INVERTED \|
	118	ATMEL_LCDC_INVFRAME_INVERTED,
	119	.vl_bpix = 3,
	120	.vl_tft = 1,
	121	.vl_hsync_len = 5,
	122	.vl_left_margin = 1,
	123	.vl_right_margin = 33,
	124	.vl_vsync_len = 1,
	125	.vl_upper_margin = 1,
	126	.vl_lower_margin = 0,
	127	.mmio = ATMEL_BASE_LCDC,
f0a2c7b4 II	128	};
	129
	130	void lcd_enable(void)
	131	{
20d98c2c	132	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
f0a2c7b4 II	133	}
	134
	135	void lcd_disable(void)
	136	{
20d98c2c	137	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
f0a2c7b4 II	138	}
	139
	140	#ifdef CONFIG_LCD_IN_PSRAM
	141
20d98c2c	142	#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
f0a2c7b4 II	143	#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
	144
	145	/* Initialize the PSRAM memory */
	146	static int pm9263_lcd_hw_psram_init(void)
	147	{
7a11c7f9	148	unsigned long csa;
684a567a AD	149	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC1;
684a567a AD	150	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
7a11c7f9 JCPV	151
7a11c7f9 JCPV	152	/* Enable CS3 3.3v, no pull-ups */
20d98c2c AD	153	csa = readl(&matrix->csa[1]) \| AT91_MATRIX_CSA_DBPUC \|
	154	AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
	155
	156	writel(csa, &matrix->csa[1]);
7a11c7f9 JCPV	157
7a11c7f9 JCPV	158	/* Configure SMC1 CS0 for PSRAM - 16-bit */
20d98c2c AD	159	writel(AT91_SMC_SETUP_NWE(0) \| AT91_SMC_SETUP_NCS_WR(0) \|
	160	AT91_SMC_SETUP_NRD(0) \| AT91_SMC_SETUP_NCS_RD(0),
	161	&smc->cs[0].setup);
	162
	163	writel(AT91_SMC_PULSE_NWE(7) \| AT91_SMC_PULSE_NCS_WR(7) \|
	164	AT91_SMC_PULSE_NRD(2) \| AT91_SMC_PULSE_NCS_RD(7),
	165	&smc->cs[0].pulse);
	166
	167	writel(AT91_SMC_CYCLE_NWE(8) \| AT91_SMC_CYCLE_NRD(8),
	168	&smc->cs[0].cycle);
	169
	170	writel(AT91_SMC_MODE_DBW_16 \| AT91_SMC_MODE_PMEN \| AT91_SMC_MODE_PS_32,
	171	&smc->cs[0].mode);
f0a2c7b4 II	172
f0a2c7b4 II	173	/* setup PB29 as output */
20d98c2c	174	at91_set_pio_output(PSRAM_CRE_PIN, 1);
f0a2c7b4	175
20d98c2c	176	at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
f0a2c7b4 II	177
f0a2c7b4 II	178	/* PSRAM: write BCR */
0a59b711 AG	179	readw(PSRAM_CTRL_REG);
0a59b711 AG	180	readw(PSRAM_CTRL_REG);
f0a2c7b4 II	181	writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
	182	writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
	183
	184	/* write RCR of the PSRAM */
0a59b711 AG	185	readw(PSRAM_CTRL_REG);
0a59b711 AG	186	readw(PSRAM_CTRL_REG);
f0a2c7b4 II	187	writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
	188	/* set RCR; 0x10-async mode,0x90-page mode */
	189	writew(0x90, PSRAM_CTRL_REG);
	190
	191	/*
	192	* test to see if the PSRAM is MT45W2M16A or MT45W2M16B
	193	* MT45W2M16B - CRE must be 0
	194	* MT45W2M16A - CRE must be 1
	195	*/
	196	writew(0x1234, PHYS_PSRAM);
	197	writew(0x5678, PHYS_PSRAM + 2);
	198
	199	/* test if the chip is MT45W2M16B */
	200	if ((readw(PHYS_PSRAM) != 0x1234) \|\| (readw(PHYS_PSRAM+2) != 0x5678)) {
	201	/* try with CRE=1 (MT45W2M16A) */
20d98c2c	202	at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
f0a2c7b4 II	203
f0a2c7b4 II	204	/* write RCR of the PSRAM */
0a59b711 AG	205	readw(PSRAM_CTRL_REG);
0a59b711 AG	206	readw(PSRAM_CTRL_REG);
f0a2c7b4 II	207	writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
	208	/* set RCR;0x10-async mode,0x90-page mode */
	209	writew(0x90, PSRAM_CTRL_REG);
	210
	211
	212	writew(0x1234, PHYS_PSRAM);
	213	writew(0x5678, PHYS_PSRAM+2);
	214	if ((readw(PHYS_PSRAM) != 0x1234)
20d98c2c	215	\|\| (readw(PHYS_PSRAM + 2) != 0x5678))
f0a2c7b4 II	216	return 1;
	217
	218	}
	219
	220	/* Bus matrix */
20d98c2c AD	221	writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
20d98c2c AD	222	writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
f0a2c7b4 II	223
	224	return 0;
	225	}
	226	#endif
	227
	228	static void pm9263_lcd_hw_init(void)
	229	{
20d98c2c AD	230	at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
	231	at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
	232	at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
	233	at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
	234	at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
	235	at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
	236	at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
	237	at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
	238	at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
	239	at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
	240	at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
	241	at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
	242	at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
	243	at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
	244	at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
	245	at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
	246	at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
	247	at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
	248	at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
	249	at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
	250	at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
	251	at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
	252	at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
	253
70341e2e	254	at91_periph_clk_enable(ATMEL_ID_LCDC);
f0a2c7b4 II	255
f0a2c7b4 II	256	/* Power Control */
20d98c2c AD	257	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
20d98c2c AD	258	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
f0a2c7b4 II	259
	260	#ifdef CONFIG_LCD_IN_PSRAM
	261	/* initialize te PSRAM */
	262	int stat = pm9263_lcd_hw_psram_init();
	263
684a567a	264	gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
f0a2c7b4	265	#else
684a567a	266	gd->fb_base = ATMEL_BASE_SRAM0;
f0a2c7b4 II	267	#endif
	268
	269	}
	270
	271	#ifdef CONFIG_LCD_INFO
	272	#include <nand.h>
	273	#include <version.h>
	274
	275	extern flash_info_t flash_info[];
	276
	277	void lcd_show_board_info(void)
	278	{
	279	ulong dram_size, nand_size, flash_size, dataflash_size;
	280	int i;
	281	char temp[32];
	282
	283	lcd_printf ("%s\n", U_BOOT_VERSION);
	284	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	285	lcd_printf ("support@ronetix.at\n");
	286	lcd_printf ("%s CPU at %s MHz",
7c966a8b	287	CONFIG_SYS_AT91_CPU_NAME,
f0a2c7b4 II	288	strmhz(temp, get_cpu_clk_rate()));
	289
	290	dram_size = 0;
	291	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	292	dram_size += gd->bd->bi_dram[i].size;
	293
	294	nand_size = 0;
	295	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
b616d9b0	296	nand_size += nand_info[i]->size;
f0a2c7b4 II	297
	298	flash_size = 0;
	299	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
	300	flash_size += flash_info[i].size;
	301
	302	dataflash_size = 0;
	303	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
	304	dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
	305	dataflash_info[i].Device.pages_size;
	306
	307	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
	308	"4 MB PSRAM, %ld MB DataFlash\n",
	309	dram_size >> 20,
	310	nand_size >> 20,
	311	flash_size >> 20,
	312	dataflash_size >> 20);
	313	}
	314	#endif /* CONFIG_LCD_INFO */
	315
	316	#endif /* CONFIG_LCD */
	317
52b26016	318	int board_early_init_f(void)
f0a2c7b4	319	{
70341e2e WY	320	at91_periph_clk_enable(ATMEL_ID_PIOA);
	321	at91_periph_clk_enable(ATMEL_ID_PIOB);
	322	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
f0a2c7b4	323
52b26016 AD	324	at91_seriald_hw_init();
	325
	326	return 0;
	327	}
	328
	329	int board_init(void)
	330	{
	331	/* arch number of AT91SAM9263EK-Board */
	332	gd->bd->bi_arch_number = MACH_TYPE_PM9263;
	333
f0a2c7b4 II	334	/* adress of boot parameters */
	335	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	336
f0a2c7b4 II	337	#ifdef CONFIG_CMD_NAND
	338	pm9263_nand_hw_init();
	339	#endif
	340	#ifdef CONFIG_HAS_DATAFLASH
	341	at91_spi0_hw_init(1 << 0);
	342	#endif
	343	#ifdef CONFIG_MACB
	344	pm9263_macb_hw_init();
	345	#endif
	346	#ifdef CONFIG_USB_OHCI_NEW
	347	at91_uhp_hw_init();
	348	#endif
	349	#ifdef CONFIG_LCD
	350	pm9263_lcd_hw_init();
	351	#endif
	352	return 0;
	353	}
	354
	355	int dram_init(void)
9a2a05a4 AD	356	{
9a2a05a4 AD	357	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	358	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
9a2a05a4 AD	359	PHYS_SDRAM_SIZE);
	360	return 0;
	361	}
	362
76b00aca	363	int dram_init_banksize(void)
f0a2c7b4 II	364	{
	365	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	366	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
76b00aca SG	367
76b00aca SG	368	return 0;
f0a2c7b4 II	369	}
	370
	371	#ifdef CONFIG_RESET_PHY_R
	372	void reset_phy(void)
	373	{
f0a2c7b4 II	374	}
	375	#endif
	376
	377	int board_eth_init(bd_t *bis)
	378	{
	379	int rc = 0;
	380	#ifdef CONFIG_MACB
684a567a	381	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
f0a2c7b4 II	382	#endif
	383	return rc;
	384	}
	385
	386	#ifdef CONFIG_DISPLAY_BOARDINFO
	387	int checkboard (void)
	388	{
	389	char *ss;
f0a2c7b4 II	390
f0a2c7b4 II	391	printf ("Board : Ronetix PM9263\n");
f0a2c7b4 II	392
	393	switch (gd->fb_base) {
	394	case PHYS_PSRAM:
	395	ss = "(PSRAM)";
	396	break;
	397
684a567a	398	case ATMEL_BASE_SRAM0:
f0a2c7b4 II	399	ss = "(Internal SRAM)";
	400	break;
	401
	402	default:
	403	ss = "";
	404	break;
	405	}
	406	printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
	407
	408	printf ("\n");
	409	return 0;
	410	}
	411	#endif