[people/ms/u-boot.git] / board / sacsng / clkinit.h

/*
 * (C) Copyright 2002
 * Custom IDEAS, Inc. <www.cideas.com>
 * Jon Diekema <diekema@cideas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#define SLRCLK_EN_MASK  0x00040000 /* PA13 - SLRCLK_EN*     */

#define MIN_SAMPLE_RATE       4000 /* Minimum sample rate */
#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
#define MAX_64x_SAMPLE_RATE  86805 /* Maximum  64x sample rate */

#define KHZ          ((uint)1000)
#define MHZ          ((uint)(1000 * KHZ))

#define MCLK_BRG     3        /* MCLK, Master CLocK for the A/D & D/A   */
#define SCLK_BRG     7        /* SCLK, Sample CLocK for the A/D & D/A   */
#define LRCLK_BRG    5        /* LRCLK, L/R CLocK for the A/D & D/A     */
			      /*   0 == BRG1 (used for SMC1)            */
			      /*   1 == BRG2 (used for SMC2)            */
			      /*   2 == BRG3 (used for SCC1)            */
			      /*   3 == BRG4 (MCLK)                     */
			      /*   4 == BRG5                            */
			      /*   5 == BRG6 (LRCLK)                    */
			      /*   6 == BRG7                            */
			      /*   7 == BRG8 (SCLK)                     */

#define MCLK_DIVISOR  4       /*  SCLK = MCLK / MCLK_DIVISOR */
#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
			      /* LRCLK = SCLK / SCLK_DIVISOR */

#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing      */
#define RUN_SCLK_ON_BRG_INT      /* Run SCLK on BRG_INT instead of MCLK   */
				 /* The 8260 (Mask B.3) seems to have     */
				 /* problems generating SCLK from MCLK    */
				 /* via CLK9.                             */
#define RUN_LRCLK_ON_BRG_INT     /* Run LRCLK on BRG_INT instead of SCLK  */
				 /* The 8260 (Mask B.3) seems to have     */
				 /* problems generating LRCLK from SCLK   */

#define NUM_LRCLKS_TO_STABILIZE 1  /* Number of LRCLK period (sample)     */
				   /* to wait for the clock to stabilize  */

#define CPM_CLK      (gd->bd->bi_cpmfreq)
#define DFBRG        4
#define BRG_INT_CLK  (CPM_CLK * 2 / DFBRG)
			      /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
			      /* BRG = CPM * 2 / 4                */
			      /* BRG = CPM / 2                    */

#define CPM_BRG_EXTC_MASK	((uint)0x0000C000)
#define CPM_BRG_EXTC_SHIFT      14

#define CPM_BRG_DIV16_MASK	((uint)0x00000001)
#define CPM_BRG_DIV16_SHIFT     1

#define CPM_BRG_EXTC_BRGCLK     0
#define CPM_BRG_EXTC_CLK3       1
#define CPM_BRG_EXTC_CLK9       CPM_BRG_EXTC_CLK3
#define CPM_BRG_EXTC_CLK5       2
#define CPM_BRG_EXTC_CLK15      CPM_BRG_EXTC_CLK5

#define IM_BRGC1 ((uint *)0xf00119f0)
#define IM_BRGC2 ((uint *)0xf00119f4)
#define IM_BRGC3 ((uint *)0xf00119f8)
#define IM_BRGC4 ((uint *)0xf00119fc)
#define IM_BRGC5 ((uint *)0xf00115f0)
#define IM_BRGC6 ((uint *)0xf00115f4)
#define IM_BRGC7 ((uint *)0xf00115f8)
#define IM_BRGC8 ((uint *)0xf00115fc)

/*
 * External declarations
 */

extern int Daq64xSampling;

extern void Daq_BRG_Reset(uint brg);
extern void Daq_BRG_Run(uint brg);

extern void Daq_BRG_Disable(uint brg);
extern void Daq_BRG_Enable(uint brg);

extern uint Daq_BRG_Get_Div16(uint brg);
extern void Daq_BRG_Set_Div16(uint brg, uint div16);

extern uint Daq_BRG_Get_Count(uint brg);
extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);

extern uint Daq_BRG_Get_ExtClk(uint brg);
extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);

extern uint Daq_BRG_Rate(uint brg);

extern uint Daq_Get_SampleRate(void);

extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
extern void Daq_Stop_Clocks(void);
extern void Daq_Start_Clocks(int sample_rate);
extern void Daq_Display_Clocks(void);
Commit	Line	Data
17bd4a84 WD	1	/*
	2	* (C) Copyright 2002
	3	* Custom IDEAS, Inc. <www.cideas.com>
	4	* Jon Diekema <diekema@cideas.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
17bd4a84 WD	7	*/
17bd4a84 WD	8
17bd4a84 WD	9	#define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */
	10
	11	#define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */
	12	#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
	13	#define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */
	14
	15	#define KHZ ((uint)1000)
	16	#define MHZ ((uint)(1000 * KHZ))
	17
	18	#define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */
	19	#define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */
	20	#define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */
	21	/* 0 == BRG1 (used for SMC1) */
	22	/* 1 == BRG2 (used for SMC2) */
	23	/* 2 == BRG3 (used for SCC1) */
	24	/* 3 == BRG4 (MCLK) */
	25	/* 4 == BRG5 */
	26	/* 5 == BRG6 (LRCLK) */
	27	/* 6 == BRG7 */
	28	/* 7 == BRG8 (SCLK) */
	29
	30	#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */
	31	#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
8bde7f77	32	/* LRCLK = SCLK / SCLK_DIVISOR */
17bd4a84 WD	33
	34	#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */
	35	#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */
8bde7f77 WD	36	/* The 8260 (Mask B.3) seems to have */
8bde7f77 WD	37	/* problems generating SCLK from MCLK */
17bd4a84 WD	38	/* via CLK9. */
17bd4a84 WD	39	#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */
8bde7f77 WD	40	/* The 8260 (Mask B.3) seems to have */
8bde7f77 WD	41	/* problems generating LRCLK from SCLK */
17bd4a84	42
eb9401e3 WD	43	#define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */
	44	/* to wait for the clock to stabilize */
	45
17bd4a84 WD	46	#define CPM_CLK (gd->bd->bi_cpmfreq)
	47	#define DFBRG 4
	48	#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG)
8bde7f77 WD	49	/* BRG = CPM * 2 / DFBRG (Sect 9.8) */
	50	/* BRG = CPM * 2 / 4 */
	51	/* BRG = CPM / 2 */
17bd4a84 WD	52
	53	#define CPM_BRG_EXTC_MASK ((uint)0x0000C000)
	54	#define CPM_BRG_EXTC_SHIFT 14
	55
	56	#define CPM_BRG_DIV16_MASK ((uint)0x00000001)
	57	#define CPM_BRG_DIV16_SHIFT 1
	58
	59	#define CPM_BRG_EXTC_BRGCLK 0
	60	#define CPM_BRG_EXTC_CLK3 1
	61	#define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3
	62	#define CPM_BRG_EXTC_CLK5 2
	63	#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5
	64
eb9401e3 WD	65	#define IM_BRGC1 ((uint *)0xf00119f0)
	66	#define IM_BRGC2 ((uint *)0xf00119f4)
	67	#define IM_BRGC3 ((uint *)0xf00119f8)
	68	#define IM_BRGC4 ((uint *)0xf00119fc)
	69	#define IM_BRGC5 ((uint *)0xf00115f0)
	70	#define IM_BRGC6 ((uint *)0xf00115f4)
	71	#define IM_BRGC7 ((uint *)0xf00115f8)
	72	#define IM_BRGC8 ((uint *)0xf00115fc)
	73
17bd4a84 WD	74	/*
	75	* External declarations
	76	*/
	77
	78	extern int Daq64xSampling;
	79
	80	extern void Daq_BRG_Reset(uint brg);
	81	extern void Daq_BRG_Run(uint brg);
	82
	83	extern void Daq_BRG_Disable(uint brg);
	84	extern void Daq_BRG_Enable(uint brg);
	85
	86	extern uint Daq_BRG_Get_Div16(uint brg);
	87	extern void Daq_BRG_Set_Div16(uint brg, uint div16);
	88
	89	extern uint Daq_BRG_Get_Count(uint brg);
	90	extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
	91
	92	extern uint Daq_BRG_Get_ExtClk(uint brg);
	93	extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
	94	extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
	95
	96	extern uint Daq_BRG_Rate(uint brg);
	97
	98	extern uint Daq_Get_SampleRate(void);
17bd4a84 WD	99
	100	extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
	101	extern void Daq_Stop_Clocks(void);
	102	extern void Daq_Start_Clocks(int sample_rate);
	103	extern void Daq_Display_Clocks(void);