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a2ac68fb CK |
1 | /* |
2 | * Copyright (C) 2013 Samsung Electronics | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
7da76512 | 8 | #include <usb.h> |
903fd795 | 9 | #include <asm/gpio.h> |
a2ac68fb | 10 | #include <asm/arch/pinmux.h> |
cc2b1012 | 11 | #include <asm/arch/dwmmc.h> |
a2ac68fb CK |
12 | #include <asm/arch/power.h> |
13 | ||
14 | DECLARE_GLOBAL_DATA_PTR; | |
15 | ||
7da76512 IS |
16 | #ifdef CONFIG_USB_EHCI_EXYNOS |
17 | int board_usb_init(int index, enum usb_init_type init) | |
18 | { | |
7da76512 IS |
19 | /* Configure gpios for usb 3503 hub: |
20 | * disconnect, toggle reset and connect | |
21 | */ | |
7f196101 SG |
22 | gpio_request(EXYNOS5_GPIO_D17, "usb_connect"); |
23 | gpio_request(EXYNOS5_GPIO_X35, "usb_reset"); | |
f6ae1ca0 AS |
24 | gpio_direction_output(EXYNOS5_GPIO_D17, 0); |
25 | gpio_direction_output(EXYNOS5_GPIO_X35, 0); | |
7da76512 | 26 | |
f6ae1ca0 AS |
27 | gpio_direction_output(EXYNOS5_GPIO_X35, 1); |
28 | gpio_direction_output(EXYNOS5_GPIO_D17, 1); | |
7da76512 IS |
29 | |
30 | return 0; | |
31 | } | |
32 | #endif | |
33 | ||
a2ac68fb CK |
34 | int board_init(void) |
35 | { | |
36 | gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); | |
37 | return 0; | |
38 | } | |
39 | ||
40 | int dram_init(void) | |
41 | { | |
42 | int i; | |
43 | u32 addr; | |
44 | ||
45 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
46 | addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); | |
47 | gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); | |
48 | } | |
49 | return 0; | |
50 | } | |
51 | ||
52 | int power_init_board(void) | |
53 | { | |
54 | set_ps_hold_ctrl(); | |
55 | return 0; | |
56 | } | |
57 | ||
76b00aca | 58 | int dram_init_banksize(void) |
a2ac68fb CK |
59 | { |
60 | int i; | |
61 | u32 addr, size; | |
62 | ||
63 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
64 | addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); | |
65 | size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); | |
66 | ||
67 | gd->bd->bi_dram[i].start = addr; | |
68 | gd->bd->bi_dram[i].size = size; | |
69 | } | |
76b00aca SG |
70 | |
71 | return 0; | |
a2ac68fb CK |
72 | } |
73 | ||
cc2b1012 IS |
74 | #ifdef CONFIG_GENERIC_MMC |
75 | int board_mmc_init(bd_t *bis) | |
76 | { | |
77 | int ret; | |
78 | /* dwmmc initializattion for available channels */ | |
79 | ret = exynos_dwmmc_init(gd->fdt_blob); | |
80 | if (ret) | |
81 | debug("dwmmc init failed\n"); | |
82 | ||
83 | return ret; | |
84 | } | |
85 | #endif | |
86 | ||
a2ac68fb CK |
87 | static int board_uart_init(void) |
88 | { | |
89 | int err = 0, uart_id; | |
90 | ||
91 | for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { | |
92 | err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); | |
93 | if (err) { | |
94 | debug("UART%d not configured\n", | |
95 | (uart_id - PERIPH_ID_UART0)); | |
96 | return err; | |
97 | } | |
98 | } | |
99 | return err; | |
100 | } | |
101 | ||
102 | #ifdef CONFIG_BOARD_EARLY_INIT_F | |
103 | int board_early_init_f(void) | |
104 | { | |
105 | int err; | |
106 | ||
107 | err = board_uart_init(); | |
108 | if (err) { | |
109 | debug("UART init failed\n"); | |
110 | return err; | |
111 | } | |
112 | return err; | |
113 | } | |
114 | #endif | |
115 | ||
116 | #ifdef CONFIG_DISPLAY_BOARDINFO | |
117 | int checkboard(void) | |
118 | { | |
119 | printf("\nBoard: Arndale\n"); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | #endif | |
fafbc6c0 AP |
124 | |
125 | #ifdef CONFIG_S5P_PA_SYSRAM | |
126 | void smp_set_core_boot_addr(unsigned long addr, int corenr) | |
127 | { | |
128 | writel(addr, CONFIG_S5P_PA_SYSRAM); | |
129 | ||
130 | /* make sure this write is really executed */ | |
131 | __asm__ volatile ("dsb\n"); | |
132 | } | |
133 | #endif |