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fe8c2806 WD |
1 | /* |
2 | * Memory Setup stuff - taken from blob memsetup.S | |
3 | * | |
4 | * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and | |
5 | * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) | |
6 | * | |
7 | * Modified for the Samsung development board by | |
8 | * (C) Copyright 2002 | |
792a09eb | 9 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
fe8c2806 WD |
10 | * |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | ||
fe8c2806 WD |
31 | #include <config.h> |
32 | #include <version.h> | |
33 | ||
34 | ||
35 | /* some parameters for the board */ | |
36 | ||
37 | /* | |
38 | * | |
39 | * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S | |
40 | * | |
41 | * Copyright (C) 2001 Samsung Electronics by chc, 010406 | |
42 | * | |
43 | * S3C2400 specific tweaks. | |
44 | * | |
45 | */ | |
46 | ||
47 | /* memory controller */ | |
48 | #define BWSCON 0x14000000 | |
49 | #define BANKCON3 0x14000010 /* for cs8900, ethernet */ | |
50 | ||
51 | /* Bank0 */ | |
52 | #define B0_Tacs 0x0 /* 0 clk */ | |
53 | #define B0_Tcos 0x0 /* 0 clk */ | |
54 | #define B0_Tacc 0x7 /* 14 clk */ | |
55 | #define B0_Tcoh 0x0 /* 0 clk */ | |
56 | #define B0_Tah 0x0 /* 0 clk */ | |
57 | #define B0_Tacp 0x0 | |
58 | #define B0_PMC 0x0 /* normal */ | |
59 | ||
60 | /* Bank1 */ | |
61 | #define B1_Tacs 0x0 /* 0 clk */ | |
62 | #define B1_Tcos 0x0 /* 0 clk */ | |
63 | #define B1_Tacc 0x7 /* 14 clk */ | |
64 | #define B1_Tcoh 0x0 /* 0 clk */ | |
65 | #define B1_Tah 0x0 /* 0 clk */ | |
66 | #define B1_Tacp 0x0 | |
67 | #define B1_PMC 0x0 /* normal */ | |
68 | ||
69 | /* Bank2 */ | |
70 | #define B2_Tacs 0x0 /* 0 clk */ | |
71 | #define B2_Tcos 0x0 /* 0 clk */ | |
72 | #define B2_Tacc 0x7 /* 14 clk */ | |
73 | #define B2_Tcoh 0x0 /* 0 clk */ | |
74 | #define B2_Tah 0x0 /* 0 clk */ | |
75 | #define B2_Tacp 0x0 | |
76 | #define B2_PMC 0x0 /* normal */ | |
77 | ||
78 | /* Bank3 - setup for the cs8900 */ | |
79 | #define B3_Tacs 0x0 /* 0 clk */ | |
80 | #define B3_Tcos 0x3 /* 4 clk */ | |
81 | #define B3_Tacc 0x7 /* 14 clk */ | |
82 | #define B3_Tcoh 0x1 /* 1 clk */ | |
83 | #define B3_Tah 0x0 /* 0 clk */ | |
84 | #define B3_Tacp 0x3 /* 6 clk */ | |
85 | #define B3_PMC 0x0 /* normal */ | |
86 | ||
87 | /* Bank4 */ | |
88 | #define B4_Tacs 0x0 /* 0 clk */ | |
89 | #define B4_Tcos 0x0 /* 0 clk */ | |
90 | #define B4_Tacc 0x7 /* 14 clk */ | |
91 | #define B4_Tcoh 0x0 /* 0 clk */ | |
92 | #define B4_Tah 0x0 /* 0 clk */ | |
93 | #define B4_Tacp 0x0 | |
94 | #define B4_PMC 0x0 /* normal */ | |
95 | ||
96 | /* Bank5 */ | |
97 | #define B5_Tacs 0x0 /* 0 clk */ | |
98 | #define B5_Tcos 0x0 /* 0 clk */ | |
99 | #define B5_Tacc 0x7 /* 14 clk */ | |
100 | #define B5_Tcoh 0x0 /* 0 clk */ | |
101 | #define B5_Tah 0x0 /* 0 clk */ | |
102 | #define B5_Tacp 0x0 | |
103 | #define B5_PMC 0x0 /* normal */ | |
104 | ||
105 | /* Bank6 */ | |
106 | #define B6_MT 0x3 /* SDRAM */ | |
107 | #define B6_Trcd 0x1 /* 3clk */ | |
108 | #define B6_SCAN 0x1 /* 9 bit */ | |
109 | ||
110 | /* Bank7 */ | |
111 | #define B7_MT 0x3 /* SDRAM */ | |
112 | #define B7_Trcd 0x1 /* 3clk */ | |
113 | #define B7_SCAN 0x1 /* 9 bit */ | |
114 | ||
115 | /* refresh parameter */ | |
116 | #define REFEN 0x1 /* enable refresh */ | |
117 | #define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ | |
118 | #define Trp 0x0 /* 2 clk */ | |
119 | #define Trc 0x3 /* 7 clk */ | |
1636d1c8 | 120 | #define Tchr 0x2 /* 3 clk */ |
fe8c2806 WD |
121 | |
122 | #define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */ | |
123 | ||
124 | ||
125 | _TEXT_BASE: | |
126 | .word TEXT_BASE | |
127 | ||
400558b5 WD |
128 | .globl lowlevel_init |
129 | lowlevel_init: | |
fe8c2806 WD |
130 | /* memory control configuration */ |
131 | /* make r0 relative the current location so that it */ | |
132 | /* reads SMRDATA out of FLASH rather than memory ! */ | |
133 | ldr r0, =SMRDATA | |
134 | ldr r1, _TEXT_BASE | |
135 | sub r0, r0, r1 | |
136 | ldr r1, =BWSCON /* Bus Width Status Controller */ | |
137 | add r2, r0, #52 | |
138 | 0: | |
139 | ldr r3, [r0], #4 | |
140 | str r3, [r1], #4 | |
141 | cmp r2, r0 | |
142 | bne 0b | |
143 | ||
144 | /* everything is fine now */ | |
145 | mov pc, lr | |
146 | ||
147 | .ltorg | |
148 | /* the literal pools origin */ | |
149 | ||
150 | SMRDATA: | |
151 | .word 0x2211d114 /* d->Ethernet, BUSWIDTH=32 */ | |
152 | .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */ | |
153 | .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */ | |
154 | .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */ | |
155 | .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */ | |
156 | .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */ | |
157 | .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */ | |
158 | .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */ | |
159 | .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */ | |
160 | .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) | |
161 | .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */ | |
162 | .word 0x30 /* MRSR6, CL=3clk */ | |
163 | .word 0x30 /* MRSR7 */ |