[people/ms/u-boot.git] / board / samsung / smdkv310 / smdkv310.c

/*
 * Copyright (C) 2011 Samsung Electronics
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mmc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>

DECLARE_GLOBAL_DATA_PTR;

static void smc9115_pre_init(void)
{
	u32 smc_bw_conf, smc_bc_conf;

	/* gpio configuration GPK0CON */
	gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));

	/* Ethernet needs bus width of 16 bits */
	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
	smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
			| SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
			| SROMC_BC_TAH(0x0F)  | SROMC_BC_TACP(0x0F)
			| SROMC_BC_PMC(0x0F);

	/* Select and configure the SROMC bank */
	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}

int board_init(void)
{
	smc9115_pre_init();

	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
	return 0;
}

int dram_init(void)
{
	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
							PHYS_SDRAM_1_SIZE);
	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
							PHYS_SDRAM_2_SIZE);
	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
							PHYS_SDRAM_3_SIZE);
	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
							PHYS_SDRAM_4_SIZE);

	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_SMC911X
	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
	return rc;
}

#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
	printf("\nBoard: SMDKV310\n");
	return 0;
}
#endif

#ifdef CONFIG_MMC
int board_mmc_init(bd_t *bis)
{
	int i, err;

	/*
	 * MMC2 SD card GPIO:
	 *
	 * GPK2[0]	SD_2_CLK(2)
	 * GPK2[1]	SD_2_CMD(2)
	 * GPK2[2]	SD_2_CDn
	 * GPK2[3:6]	SD_2_DATA[0:3](2)
	 */
	for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
		/* GPK2[0:6] special function 2 */
		gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));

		/* GPK2[0:6] drv 4x */
		gpio_set_drv(i, S5P_GPIO_DRV_4X);

		/* GPK2[0:1] pull disable */
		if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
			gpio_set_pull(i, S5P_GPIO_PULL_NONE);
			continue;
		}

		/* GPK2[2:6] pull up */
		gpio_set_pull(i, S5P_GPIO_PULL_UP);
	}
	err = s5p_mmc_init(2, 4);
	return err;
}
#endif

static int board_uart_init(void)
{
	int err;

	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
	if (err) {
		debug("UART0 not configured\n");
		return err;
	}

	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
	if (err) {
		debug("UART1 not configured\n");
		return err;
	}

	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
	if (err) {
		debug("UART2 not configured\n");
		return err;
	}

	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
	if (err) {
		debug("UART3 not configured\n");
		return err;
	}

	return 0;
}

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	int err;
	err = board_uart_init();
	if (err) {
		debug("UART init failed\n");
		return err;
	}
	return err;
}
#endif
Commit	Line	Data
e21185ba CK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
e21185ba CK	5	*/
	6
	7	#include <common.h>
903fd795	8	#include <asm/gpio.h>
e21185ba CK	9	#include <asm/io.h>
	10	#include <netdev.h>
	11	#include <asm/arch/cpu.h>
e21185ba	12	#include <asm/arch/mmc.h>
198a40b9 RS	13	#include <asm/arch/periph.h>
198a40b9 RS	14	#include <asm/arch/pinmux.h>
e21185ba CK	15	#include <asm/arch/sromc.h>
	16
	17	DECLARE_GLOBAL_DATA_PTR;
e21185ba CK	18
	19	static void smc9115_pre_init(void)
	20	{
	21	u32 smc_bw_conf, smc_bc_conf;
	22
	23	/* gpio configuration GPK0CON */
f6ae1ca0	24	gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
e21185ba CK	25
	26	/* Ethernet needs bus width of 16 bits */
	27	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
	28	smc_bc_conf = SROMC_BC_TACS(0x0F) \| SROMC_BC_TCOS(0x0F)
	29	\| SROMC_BC_TACC(0x0F) \| SROMC_BC_TCOH(0x0F)
	30	\| SROMC_BC_TAH(0x0F) \| SROMC_BC_TACP(0x0F)
	31	\| SROMC_BC_PMC(0x0F);
	32
	33	/* Select and configure the SROMC bank */
	34	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
	35	}
	36
	37	int board_init(void)
	38	{
e21185ba CK	39	smc9115_pre_init();
e21185ba CK	40
e21185ba CK	41	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
	42	return 0;
	43	}
	44
	45	int dram_init(void)
	46	{
	47	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
	48	+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
	49	+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
	50	+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
	51
	52	return 0;
	53	}
	54
76b00aca	55	int dram_init_banksize(void)
e21185ba CK	56	{
e21185ba CK	57	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
6b949ba8	58	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
9436a0c9	59	PHYS_SDRAM_1_SIZE);
e21185ba	60	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
6b949ba8	61	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
9436a0c9	62	PHYS_SDRAM_2_SIZE);
e21185ba	63	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
6b949ba8	64	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
9436a0c9	65	PHYS_SDRAM_3_SIZE);
e21185ba	66	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
6b949ba8	67	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
9436a0c9	68	PHYS_SDRAM_4_SIZE);
76b00aca SG	69
76b00aca SG	70	return 0;
e21185ba CK	71	}
	72
	73	int board_eth_init(bd_t *bis)
	74	{
	75	int rc = 0;
	76	#ifdef CONFIG_SMC911X
	77	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	78	#endif
	79	return rc;
	80	}
	81
	82	#ifdef CONFIG_DISPLAY_BOARDINFO
	83	int checkboard(void)
	84	{
	85	printf("\nBoard: SMDKV310\n");
	86	return 0;
	87	}
	88	#endif
	89
4aa2ba3a	90	#ifdef CONFIG_MMC
e21185ba CK	91	int board_mmc_init(bd_t *bis)
	92	{
	93	int i, err;
	94
	95	/*
	96	* MMC2 SD card GPIO:
	97	*
	98	* GPK2[0] SD_2_CLK(2)
	99	* GPK2[1] SD_2_CMD(2)
	100	* GPK2[2] SD_2_CDn
	101	* GPK2[3:6] SD_2_DATA[0:3](2)
	102	*/
f6ae1ca0	103	for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
e21185ba	104	/* GPK2[0:6] special function 2 */
f6ae1ca0	105	gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
e21185ba CK	106
e21185ba CK	107	/* GPK2[0:6] drv 4x */
f6ae1ca0	108	gpio_set_drv(i, S5P_GPIO_DRV_4X);
e21185ba CK	109
e21185ba CK	110	/* GPK2[0:1] pull disable */
f6ae1ca0 AS	111	if (i == EXYNOS4_GPIO_K20 \|\| i == EXYNOS4_GPIO_K21) {
f6ae1ca0 AS	112	gpio_set_pull(i, S5P_GPIO_PULL_NONE);
e21185ba CK	113	continue;
	114	}
	115
	116	/* GPK2[2:6] pull up */
f6ae1ca0	117	gpio_set_pull(i, S5P_GPIO_PULL_UP);
e21185ba CK	118	}
	119	err = s5p_mmc_init(2, 4);
	120	return err;
	121	}
	122	#endif
198a40b9 RS	123
	124	static int board_uart_init(void)
	125	{
	126	int err;
	127
	128	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
	129	if (err) {
	130	debug("UART0 not configured\n");
	131	return err;
	132	}
	133
	134	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
	135	if (err) {
	136	debug("UART1 not configured\n");
	137	return err;
	138	}
	139
	140	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
	141	if (err) {
	142	debug("UART2 not configured\n");
	143	return err;
	144	}
	145
	146	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
	147	if (err) {
	148	debug("UART3 not configured\n");
	149	return err;
	150	}
	151
	152	return 0;
	153	}
	154
	155	#ifdef CONFIG_BOARD_EARLY_INIT_F
	156	int board_early_init_f(void)
	157	{
	158	int err;
	159	err = board_uart_init();
	160	if (err) {
	161	debug("UART init failed\n");
	162	return err;
	163	}
	164	return err;
	165	}
	166	#endif