[people/ms/u-boot.git] / board / samsung / trats / trats.c

/*
 * Copyright (C) 2011 Samsung Electronics
 * Heungjun Kim <riverful.kim@samsung.com>
 * Kyungmin Park <kyungmin.park@samsung.com>
 * Donghwa Lee <dh09.lee@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <lcd.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/cpu.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/watchdog.h>
#include <asm/arch/power.h>
#include <power/pmic.h>
#include <usb/dwc2_udc.h>
#include <power/max8997_pmic.h>
#include <power/max8997_muic.h>
#include <power/battery.h>
#include <power/max17042_fg.h>
#include <libtizen.h>
#include <usb.h>
#include <usb_mass_storage.h>

#include "setup.h"

DECLARE_GLOBAL_DATA_PTR;

unsigned int board_rev;

#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
	return board_rev;
}
#endif

static void check_hw_revision(void);
struct dwc2_plat_otg_data s5pc210_otg_data;

int exynos_init(void)
{
	check_hw_revision();
	printf("HW Revision:\t0x%x\n", board_rev);

	return 0;
}

void i2c_init_board(void)
{
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
	int err;

	/* I2C_8 -> FG */
	gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
	gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
	gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
	gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
#endif
}

#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
static void trats_low_power_mode(void)
{
	struct exynos4_clock *clk =
	    (struct exynos4_clock *)samsung_get_base_clock();
	struct exynos4_power *pwr =
	    (struct exynos4_power *)samsung_get_base_power();

	/* Power down CORE1 */
	/* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
	writel(0x0, &pwr->arm_core1_configuration);

	/* Change the APLL frequency */
	/* ENABLE (1 enable) | LOCKED (1 locked)  */
	/* [31]              | [29]               */
	/* FSEL      | MDIV          | PDIV            | SDIV */
	/* [27]      | [25:16]       | [13:8]          | [2:0]      */
	writel(0xa0c80604, &clk->apll_con0);

	/* Change CPU0 clock divider */
	/* CORE2_RATIO  | APLL_RATIO   | PCLK_DBG_RATIO | ATB_RATIO  */
	/* [30:28]      | [26:24]      | [22:20]        | [18:16]    */
	/* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO   | CORE_RATIO */
	/* [14:12]      | [10:8]       | [6:4]          | [2:0]      */
	writel(0x00000100, &clk->div_cpu0);

	/* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
	while (readl(&clk->div_stat_cpu0) & 0x1111111)
		continue;

	/* Change clock divider ratio for DMC */
	/* DMCP_RATIO                  | DMCD_RATIO  */
	/* [22:20]                     | [18:16]     */
	/* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO   | ACP_RATIO */
	/* [14:12]   | [10:8]     | [6:4]            | [2:0]     */
	writel(0x13113117, &clk->div_dmc0);

	/* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
	while (readl(&clk->div_stat_dmc0) & 0x11111111)
		continue;

	/* Turn off unnecessary power domains */
	writel(0x0, &pwr->xxti_configuration);	/* XXTI */
	writel(0x0, &pwr->cam_configuration);	/* CAM */
	writel(0x0, &pwr->tv_configuration);    /* TV */
	writel(0x0, &pwr->mfc_configuration);   /* MFC */
	writel(0x0, &pwr->g3d_configuration);   /* G3D */
	writel(0x0, &pwr->gps_configuration);   /* GPS */
	writel(0x0, &pwr->gps_alive_configuration);	/* GPS_ALIVE */

	/* Turn off unnecessary clocks */
	writel(0x0, &clk->gate_ip_cam);	/* CAM */
	writel(0x0, &clk->gate_ip_tv);          /* TV */
	writel(0x0, &clk->gate_ip_mfc);	/* MFC */
	writel(0x0, &clk->gate_ip_g3d);	/* G3D */
	writel(0x0, &clk->gate_ip_image);	/* IMAGE */
	writel(0x0, &clk->gate_ip_gps);	/* GPS */
}
#endif

int exynos_power_init(void)
{
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
	int chrg, ret;
	struct power_battery *pb;
	struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;

	/*
	 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
	 * to logical I2C adapter 0
	 *
	 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
	 * to logical I2C adapter 1
	 */
	ret = power_fg_init(I2C_9);
	ret |= power_muic_init(I2C_5);
	ret |= power_bat_init(0);
	if (ret)
		return ret;

	p_fg = pmic_get("MAX17042_FG");
	if (!p_fg) {
		puts("MAX17042_FG: Not found\n");
		return -ENODEV;
	}

	p_chrg = pmic_get("MAX8997_PMIC");
	if (!p_chrg) {
		puts("MAX8997_PMIC: Not found\n");
		return -ENODEV;
	}

	p_muic = pmic_get("MAX8997_MUIC");
	if (!p_muic) {
		puts("MAX8997_MUIC: Not found\n");
		return -ENODEV;
	}

	p_bat = pmic_get("BAT_TRATS");
	if (!p_bat) {
		puts("BAT_TRATS: Not found\n");
		return -ENODEV;
	}

	p_fg->parent =  p_bat;
	p_chrg->parent = p_bat;
	p_muic->parent = p_bat;

	p_bat->low_power_mode = trats_low_power_mode;
	p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);

	pb = p_bat->pbat;
	chrg = p_muic->chrg->chrg_type(p_muic);
	debug("CHARGER TYPE: %d\n", chrg);

	if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
		puts("No battery detected\n");
		return 0;
	}

	p_fg->fg->fg_battery_check(p_fg, p_bat);

	if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
		puts("CHARGE Battery !\n");
#endif

	return 0;
}

static unsigned int get_hw_revision(void)
{
	int hwrev = 0;
	char str[10];
	int i;

	/* hw_rev[3:0] == GPE1[3:0] */
	for (i = 0; i < 4; i++) {
		int pin = i + EXYNOS4_GPIO_E10;

		sprintf(str, "hw_rev%d", i);
		gpio_request(pin, str);
		gpio_cfg_pin(pin, S5P_GPIO_INPUT);
		gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
	}

	udelay(1);

	for (i = 0; i < 4; i++)
		hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);

	debug("hwrev 0x%x\n", hwrev);

	return hwrev;
}

static void check_hw_revision(void)
{
	int hwrev;

	hwrev = get_hw_revision();

	board_rev |= hwrev;
}


#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
	int ret = 0;
	u32 val = 0;
	struct pmic *p = pmic_get("MAX8997_PMIC");
	if (!p)
		return -ENODEV;

	if (pmic_probe(p))
		return -1;

	if (on) {
		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
				      ENSAFEOUT1, LDO_ON);
		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);

		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
	} else {
		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);

		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
				      ENSAFEOUT1, LDO_OFF);
	}

	if (ret) {
		puts("MAX8997 LDO setting error!\n");
		return -1;
	}
#endif

	return 0;
}

struct dwc2_plat_otg_data s5pc210_otg_data = {
	.phy_control	= s5pc210_phy_control,
	.regs_phy	= EXYNOS4_USBPHY_BASE,
	.regs_otg	= EXYNOS4_USBOTG_BASE,
	.usb_phy_ctrl	= EXYNOS4_USBPHY_CONTROL,
	.usb_flags	= PHY0_SLEEP,
};

int board_usb_init(int index, enum usb_init_type init)
{
	debug("USB_udc_probe\n");
	return dwc2_udc_probe(&s5pc210_otg_data);
}

int g_dnl_board_usb_cable_connected(void)
{
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
	struct pmic *muic = pmic_get("MAX8997_MUIC");
	if (!muic)
		return 0;

	return !!muic->chrg->chrg_type(muic);
#else
	return false;
#endif

}
#endif

static void pmic_reset(void)
{
	gpio_direction_output(EXYNOS4_GPIO_X07, 1);
	gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
}

static void board_clock_init(void)
{
	struct exynos4_clock *clk =
		(struct exynos4_clock *)samsung_get_base_clock();

	writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
	writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
	writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
	writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);

	writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
	writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
	writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
	writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
	writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
	writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
	writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
	writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
	writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
	writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
	writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
	writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);

	writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
	writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
	writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
	writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
	writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
	writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
	writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
	writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
	writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
	writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
	writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
	writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);

	writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
	writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
	writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
	writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
	writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
	writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
	writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
	writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
	writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
	writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
	writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
	writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
}

static void board_power_init(void)
{
	struct exynos4_power *pwr =
		(struct exynos4_power *)samsung_get_base_power();

	/* PS HOLD */
	writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);

	/* Set power down */
	writel(0, (unsigned int)&pwr->cam_configuration);
	writel(0, (unsigned int)&pwr->tv_configuration);
	writel(0, (unsigned int)&pwr->mfc_configuration);
	writel(0, (unsigned int)&pwr->g3d_configuration);
	writel(0, (unsigned int)&pwr->lcd1_configuration);
	writel(0, (unsigned int)&pwr->gps_configuration);
	writel(0, (unsigned int)&pwr->gps_alive_configuration);

	/* It is necessary to power down core 1 */
	/* to successfully boot CPU1 in kernel */
	writel(0, (unsigned int)&pwr->arm_core1_configuration);
}

static void exynos_uart_init(void)
{
	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
	gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
	gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
	gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
}

int exynos_early_init_f(void)
{
	wdt_stop();
	pmic_reset();
	board_clock_init();
	exynos_uart_init();
	board_power_init();

	return 0;
}

void exynos_reset_lcd(void)
{
	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
	udelay(10000);
	gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
	udelay(10000);
	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
}

int lcd_power(void)
{
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
	int ret = 0;
	struct pmic *p = pmic_get("MAX8997_PMIC");
	if (!p)
		return -ENODEV;

	if (pmic_probe(p))
		return 0;

	/* LDO15 voltage: 2.2v */
	ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
	/* LDO13 voltage: 3.0v */
	ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);

	if (ret) {
		puts("MAX8997 LDO setting error!\n");
		return -1;
	}
#endif
	return 0;
}

int mipi_power(void)
{
#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
	int ret = 0;
	struct pmic *p = pmic_get("MAX8997_PMIC");
	if (!p)
		return -ENODEV;

	if (pmic_probe(p))
		return 0;

	/* LDO3 voltage: 1.1v */
	ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
	/* LDO4 voltage: 1.8v */
	ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);

	if (ret) {
		puts("MAX8997 LDO setting error!\n");
		return -1;
	}
#endif
	return 0;
}

#ifdef CONFIG_LCD
void exynos_lcd_misc_init(vidinfo_t *vid)
{
#ifdef CONFIG_TIZEN
	get_tizen_logo_info(vid);
#endif
#ifdef CONFIG_S6E8AX0
	s6e8ax0_init();
	setenv("lcdinfo", "lcd=s6e8ax0");
#endif
}
#endif
Commit	Line	Data
89f95492 HK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	* Heungjun Kim <riverful.kim@samsung.com>
	4	* Kyungmin Park <kyungmin.park@samsung.com>
51b1cd6d	5	* Donghwa Lee <dh09.lee@samsung.com>
89f95492	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
89f95492 HK	8	*/
	9
	10	#include <common.h>
51b1cd6d	11	#include <lcd.h>
89f95492	12	#include <asm/io.h>
903fd795	13	#include <asm/gpio.h>
89f95492	14	#include <asm/arch/cpu.h>
d651e88a	15	#include <asm/arch/pinmux.h>
89f95492	16	#include <asm/arch/clock.h>
51b1cd6d	17	#include <asm/arch/mipi_dsim.h>
89f95492 HK	18	#include <asm/arch/watchdog.h>
89f95492 HK	19	#include <asm/arch/power.h>
c7336815	20	#include <power/pmic.h>
5d5716ee	21	#include <usb/dwc2_udc.h>
c7336815	22	#include <power/max8997_pmic.h>
7dcda99d	23	#include <power/max8997_muic.h>
61365ffc	24	#include <power/battery.h>
5a77358c	25	#include <power/max17042_fg.h>
fe601647	26	#include <libtizen.h>
16297cfb	27	#include <usb.h>
83301b4f	28	#include <usb_mass_storage.h>
89f95492 HK	29
	30	#include "setup.h"
	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
	34	unsigned int board_rev;
	35
	36	#ifdef CONFIG_REVISION_TAG
	37	u32 get_board_rev(void)
	38	{
	39	return board_rev;
	40	}
	41	#endif
	42
	43	static void check_hw_revision(void);
c0982871	44	struct dwc2_plat_otg_data s5pc210_otg_data;
a241d6ef	45
fe601647	46	int exynos_init(void)
89f95492	47	{
89f95492 HK	48	check_hw_revision();
	49	printf("HW Revision:\t0x%x\n", board_rev);
	50
89f95492 HK	51	return 0;
	52	}
	53
fd8dca83 ŁM	54	void i2c_init_board(void)
fd8dca83 ŁM	55	{
fc47cf9d	56	#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
2d8f1e27	57	int err;
fd8dca83	58
2d8f1e27	59	/* I2C_8 -> FG */
7f196101 SG	60	gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
7f196101 SG	61	gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
f6ae1ca0 AS	62	gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
f6ae1ca0 AS	63	gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
fc47cf9d	64	#endif
fd8dca83 ŁM	65	}
fd8dca83 ŁM	66
fc47cf9d	67	#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
69ad72a1 ŁM	68	static void trats_low_power_mode(void)
	69	{
	70	struct exynos4_clock *clk =
	71	(struct exynos4_clock *)samsung_get_base_clock();
	72	struct exynos4_power *pwr =
	73	(struct exynos4_power *)samsung_get_base_power();
	74
	75	/* Power down CORE1 */
	76	/* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
	77	writel(0x0, &pwr->arm_core1_configuration);
	78
	79	/* Change the APLL frequency */
	80	/* ENABLE (1 enable) \| LOCKED (1 locked) */
	81	/* [31] \| [29] */
	82	/* FSEL \| MDIV \| PDIV \| SDIV */
	83	/* [27] \| [25:16] \| [13:8] \| [2:0] */
	84	writel(0xa0c80604, &clk->apll_con0);
	85
	86	/* Change CPU0 clock divider */
	87	/* CORE2_RATIO \| APLL_RATIO \| PCLK_DBG_RATIO \| ATB_RATIO */
	88	/* [30:28] \| [26:24] \| [22:20] \| [18:16] */
	89	/* PERIPH_RATIO \| COREM1_RATIO \| COREM0_RATIO \| CORE_RATIO */
	90	/* [14:12] \| [10:8] \| [6:4] \| [2:0] */
	91	writel(0x00000100, &clk->div_cpu0);
	92
	93	/* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
	94	while (readl(&clk->div_stat_cpu0) & 0x1111111)
	95	continue;
	96
	97	/* Change clock divider ratio for DMC */
	98	/* DMCP_RATIO \| DMCD_RATIO */
	99	/* [22:20] \| [18:16] */
	100	/* DMC_RATIO \| DPHY_RATIO \| ACP_PCLK_RATIO \| ACP_RATIO */
	101	/* [14:12] \| [10:8] \| [6:4] \| [2:0] */
	102	writel(0x13113117, &clk->div_dmc0);
	103
	104	/* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
	105	while (readl(&clk->div_stat_dmc0) & 0x11111111)
	106	continue;
	107
	108	/* Turn off unnecessary power domains */
	109	writel(0x0, &pwr->xxti_configuration); /* XXTI */
	110	writel(0x0, &pwr->cam_configuration); /* CAM */
	111	writel(0x0, &pwr->tv_configuration); /* TV */
	112	writel(0x0, &pwr->mfc_configuration); /* MFC */
	113	writel(0x0, &pwr->g3d_configuration); /* G3D */
	114	writel(0x0, &pwr->gps_configuration); /* GPS */
	115	writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
	116
	117	/* Turn off unnecessary clocks */
	118	writel(0x0, &clk->gate_ip_cam); /* CAM */
	119	writel(0x0, &clk->gate_ip_tv); /* TV */
	120	writel(0x0, &clk->gate_ip_mfc); /* MFC */
	121	writel(0x0, &clk->gate_ip_g3d); /* G3D */
	122	writel(0x0, &clk->gate_ip_image); /* IMAGE */
	123	writel(0x0, &clk->gate_ip_gps); /* GPS */
	124	}
fc47cf9d	125	#endif
a52a7b14	126
fe601647	127	int exynos_power_init(void)
d47ab982	128	{
fc47cf9d	129	#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
bdee9c85 ŁM	130	int chrg, ret;
	131	struct power_battery *pb;
	132	struct pmic p_fg, p_chrg, p_muic, p_bat;
d47ab982	133
2936df1f ŁM	134	/*
	135	* For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
	136	* to logical I2C adapter 0
	137	*
	138	* The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
	139	* to logical I2C adapter 1
	140	*/
5dfbd7ba	141	ret = power_fg_init(I2C_9);
2d8f1e27	142	ret \|= power_muic_init(I2C_5);
61365ffc	143	ret \|= power_bat_init(0);
d47ab982 ŁM	144	if (ret)
	145	return ret;
	146
bdee9c85 ŁM	147	p_fg = pmic_get("MAX17042_FG");
	148	if (!p_fg) {
	149	puts("MAX17042_FG: Not found\n");
	150	return -ENODEV;
	151	}
	152
	153	p_chrg = pmic_get("MAX8997_PMIC");
	154	if (!p_chrg) {
	155	puts("MAX8997_PMIC: Not found\n");
	156	return -ENODEV;
	157	}
	158
	159	p_muic = pmic_get("MAX8997_MUIC");
	160	if (!p_muic) {
	161	puts("MAX8997_MUIC: Not found\n");
	162	return -ENODEV;
	163	}
	164
	165	p_bat = pmic_get("BAT_TRATS");
	166	if (!p_bat) {
	167	puts("BAT_TRATS: Not found\n");
	168	return -ENODEV;
	169	}
	170
	171	p_fg->parent = p_bat;
	172	p_chrg->parent = p_bat;
	173	p_muic->parent = p_bat;
	174
	175	p_bat->low_power_mode = trats_low_power_mode;
	176	p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
	177
	178	pb = p_bat->pbat;
	179	chrg = p_muic->chrg->chrg_type(p_muic);
	180	debug("CHARGER TYPE: %d\n", chrg);
	181
	182	if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
	183	puts("No battery detected\n");
4a188365	184	return 0;
bdee9c85 ŁM	185	}
	186
	187	p_fg->fg->fg_battery_check(p_fg, p_bat);
	188
	189	if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
	190	puts("CHARGE Battery !\n");
fc47cf9d	191	#endif
bdee9c85	192
d47ab982 ŁM	193	return 0;
	194	}
	195
89f95492 HK	196	static unsigned int get_hw_revision(void)
89f95492 HK	197	{
89f95492	198	int hwrev = 0;
7f196101	199	char str[10];
89f95492 HK	200	int i;
	201
	202	/* hw_rev[3:0] == GPE1[3:0] */
7f196101 SG	203	for (i = 0; i < 4; i++) {
	204	int pin = i + EXYNOS4_GPIO_E10;
	205
	206	sprintf(str, "hw_rev%d", i);
	207	gpio_request(pin, str);
	208	gpio_cfg_pin(pin, S5P_GPIO_INPUT);
	209	gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
89f95492 HK	210	}
	211
	212	udelay(1);
	213
	214	for (i = 0; i < 4; i++)
f6ae1ca0	215	hwrev \|= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
89f95492 HK	216
	217	debug("hwrev 0x%x\n", hwrev);
	218
	219	return hwrev;
	220	}
	221
	222	static void check_hw_revision(void)
	223	{
	224	int hwrev;
	225
	226	hwrev = get_hw_revision();
	227
	228	board_rev \|= hwrev;
	229	}
	230
89f95492 HK	231
	232	#ifdef CONFIG_USB_GADGET
	233	static int s5pc210_phy_control(int on)
	234	{
fc47cf9d	235	#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
89f95492	236	int ret = 0;
a0f5b5a3	237	u32 val = 0;
c7336815 ŁM	238	struct pmic *p = pmic_get("MAX8997_PMIC");
	239	if (!p)
	240	return -ENODEV;
89f95492 HK	241
	242	if (pmic_probe(p))
	243	return -1;
	244
	245	if (on) {
04ce68ee ŁM	246	ret \|= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
04ce68ee ŁM	247	ENSAFEOUT1, LDO_ON);
a0f5b5a3 ŁM	248	ret \|= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
	249	ret \|= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO \| val);
	250
	251	ret \|= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
	252	ret \|= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO \| val);
89f95492	253	} else {
a0f5b5a3 ŁM	254	ret \|= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
	255	ret \|= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO \| val);
	256
	257	ret \|= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
	258	ret \|= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO \| val);
04ce68ee ŁM	259	ret \|= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
04ce68ee ŁM	260	ENSAFEOUT1, LDO_OFF);
89f95492 HK	261	}
	262
	263	if (ret) {
04ce68ee	264	puts("MAX8997 LDO setting error!\n");
89f95492 HK	265	return -1;
89f95492 HK	266	}
fc47cf9d	267	#endif
89f95492 HK	268
	269	return 0;
	270	}
	271
c0982871	272	struct dwc2_plat_otg_data s5pc210_otg_data = {
89f95492 HK	273	.phy_control = s5pc210_phy_control,
	274	.regs_phy = EXYNOS4_USBPHY_BASE,
	275	.regs_otg = EXYNOS4_USBOTG_BASE,
	276	.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
	277	.usb_flags = PHY0_SLEEP,
	278	};
a241d6ef	279
bba67914	280	int board_usb_init(int index, enum usb_init_type init)
a241d6ef ŁM	281	{
a241d6ef ŁM	282	debug("USB_udc_probe\n");
a4bb9b36	283	return dwc2_udc_probe(&s5pc210_otg_data);
a241d6ef	284	}
0938f5b2	285
75504e95	286	int g_dnl_board_usb_cable_connected(void)
0938f5b2	287	{
fc47cf9d	288	#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
0938f5b2 PM	289	struct pmic *muic = pmic_get("MAX8997_MUIC");
	290	if (!muic)
	291	return 0;
	292
	293	return !!muic->chrg->chrg_type(muic);
fc47cf9d SG	294	#else
	295	return false;
	296	#endif
	297
0938f5b2 PM	298	}
0938f5b2 PM	299	#endif
89f95492 HK	300
	301	static void pmic_reset(void)
	302	{
f6ae1ca0 AS	303	gpio_direction_output(EXYNOS4_GPIO_X07, 1);
f6ae1ca0 AS	304	gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
89f95492 HK	305	}
	306
	307	static void board_clock_init(void)
	308	{
	309	struct exynos4_clock *clk =
	310	(struct exynos4_clock *)samsung_get_base_clock();
	311
	312	writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
	313	writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
	314	writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
	315	writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
	316
	317	writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
	318	writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
	319	writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
	320	writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
	321	writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
	322	writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
	323	writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
	324	writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
	325	writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
	326	writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
	327	writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
	328	writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
	329
	330	writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
	331	writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
	332	writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
	333	writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
	334	writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
	335	writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
	336	writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
	337	writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
	338	writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
	339	writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
	340	writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
	341	writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
	342
	343	writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
	344	writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
	345	writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
	346	writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
	347	writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
	348	writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
	349	writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
	350	writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
	351	writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
	352	writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
	353	writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
	354	writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
	355	}
	356
89f95492 HK	357	static void board_power_init(void)
	358	{
	359	struct exynos4_power *pwr =
	360	(struct exynos4_power *)samsung_get_base_power();
	361
	362	/* PS HOLD */
	363	writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
	364
	365	/* Set power down */
	366	writel(0, (unsigned int)&pwr->cam_configuration);
	367	writel(0, (unsigned int)&pwr->tv_configuration);
	368	writel(0, (unsigned int)&pwr->mfc_configuration);
	369	writel(0, (unsigned int)&pwr->g3d_configuration);
	370	writel(0, (unsigned int)&pwr->lcd1_configuration);
	371	writel(0, (unsigned int)&pwr->gps_configuration);
	372	writel(0, (unsigned int)&pwr->gps_alive_configuration);
ab23304d PW	373
	374	/* It is necessary to power down core 1 */
	375	/* to successfully boot CPU1 in kernel */
	376	writel(0, (unsigned int)&pwr->arm_core1_configuration);
89f95492 HK	377	}
89f95492 HK	378
fe601647	379	static void exynos_uart_init(void)
89f95492	380	{
89f95492	381	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
7f196101	382	gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
f6ae1ca0 AS	383	gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
f6ae1ca0 AS	384	gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
89f95492 HK	385	}
89f95492 HK	386
fe601647	387	int exynos_early_init_f(void)
89f95492	388	{
85948a8b	389	wdt_stop();
89f95492 HK	390	pmic_reset();
89f95492 HK	391	board_clock_init();
fe601647	392	exynos_uart_init();
89f95492 HK	393	board_power_init();
	394
	395	return 0;
	396	}
51b1cd6d	397
29fd5704	398	void exynos_reset_lcd(void)
51b1cd6d	399	{
7f196101	400	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
f6ae1ca0	401	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
51b1cd6d	402	udelay(10000);
f6ae1ca0	403	gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
51b1cd6d	404	udelay(10000);
f6ae1ca0	405	gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
51b1cd6d DL	406	}
51b1cd6d DL	407
fe601647	408	int lcd_power(void)
51b1cd6d	409	{
fc47cf9d	410	#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
51b1cd6d	411	int ret = 0;
c7336815 ŁM	412	struct pmic *p = pmic_get("MAX8997_PMIC");
	413	if (!p)
	414	return -ENODEV;
51b1cd6d DL	415
	416	if (pmic_probe(p))
	417	return 0;
	418
	419	/* LDO15 voltage: 2.2v */
	420	ret \|= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c \| EN_LDO);
	421	/* LDO13 voltage: 3.0v */
	422	ret \|= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c \| EN_LDO);
	423
	424	if (ret) {
	425	puts("MAX8997 LDO setting error!\n");
	426	return -1;
	427	}
fc47cf9d	428	#endif
51b1cd6d DL	429	return 0;
	430	}
	431
fe601647	432	int mipi_power(void)
51b1cd6d	433	{
fc47cf9d	434	#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
51b1cd6d	435	int ret = 0;
c7336815 ŁM	436	struct pmic *p = pmic_get("MAX8997_PMIC");
	437	if (!p)
	438	return -ENODEV;
51b1cd6d DL	439
	440	if (pmic_probe(p))
	441	return 0;
	442
	443	/* LDO3 voltage: 1.1v */
	444	ret \|= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 \| EN_LDO);
	445	/* LDO4 voltage: 1.8v */
	446	ret \|= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 \| EN_LDO);
	447
	448	if (ret) {
	449	puts("MAX8997 LDO setting error!\n");
	450	return -1;
	451	}
fc47cf9d	452	#endif
51b1cd6d DL	453	return 0;
	454	}
	455
ea743e65	456	#ifdef CONFIG_LCD
fe601647	457	void exynos_lcd_misc_init(vidinfo_t *vid)
51b1cd6d	458	{
90464971 DL	459	#ifdef CONFIG_TIZEN
	460	get_tizen_logo_info(vid);
	461	#endif
fe601647	462	#ifdef CONFIG_S6E8AX0
51b1cd6d	463	s6e8ax0_init();
51b1cd6d	464	setenv("lcdinfo", "lcd=s6e8ax0");
00e64ab6	465	#endif
679549d1	466	}
ea743e65	467	#endif