[people/ms/u-boot.git] / board / sandburst / metrobox / metrobox.c

/*
 *  Copyright (c) 2005
 *  Travis B. Sawyer,  Sandburst Corporation, tsawyer@sandburst.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <config.h>
#include <common.h>
#include <command.h>
#include "metrobox.h"
#include "metrobox_version.h"
#include <timestamp.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
#include "../common/sb_common.h"
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
#include <net.h>
#endif

void fpga_init (void);

METROBOX_BOARD_ID_ST board_id_as[] =
{	{"Undefined"},			    /* Not specified */
	{"2x10Gb"},			    /* 2 ports, 10 GbE */
	{"20x1Gb"},			    /* 20 ports, 1 GbE */
	{"Reserved"},			     /* Reserved for future use */
};

/*************************************************************************
 *  board_early_init_f
 *
 *  Setup chip selects, initialize the Opto-FPGA, initialize
 *  interrupt polarity and triggers.
 ************************************************************************/
int board_early_init_f (void)
{
	ppc440_gpio_regs_t *gpio_regs;

	/* Enable GPIO interrupts */
	mtsdr(SDR0_PFC0, 0x00103E00);

	/* Setup access for LEDs, and system topology info */
	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;

	/* Turn on all the leds for now */
	gpio_regs->out = SBCOMMON_GPIO_LEDS;

	/*--------------------------------------------------------------------+
	  | Initialize EBC CONFIG
	  +-------------------------------------------------------------------*/
	mtebc(EBC0_CFG,
	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |
	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
	      EBC_CFG_PR_32);

	/*--------------------------------------------------------------------+
	  | 1/2 MB FLASH. Initialize bank 0 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(PB0AP,
	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);

	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
	/*--------------------------------------------------------------------+
	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(PB1AP,
	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);

	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);

	/*--------------------------------------------------------------------+
	  | Compact Flash, uses 2 Chip Selects (2 & 6)
	  +-------------------------------------------------------------------*/
	mtebc(PB2AP,
	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);

	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);

	/*--------------------------------------------------------------------+
	  | OPTO & OFEM FPGA. Initialize bank 3 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(PB3AP,
	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);

	mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*--------------------------------------------------------------------+
	  | MAC A for metrobox
	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
	  | Initialize bank 4 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(PB4AP,
	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);

	mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*--------------------------------------------------------------------+
	  | Metrobox MAC B  Initialize bank 5 with default values.
	  | KA REF FPGA	 Initialize bank 5 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(PB5AP,
	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);

	mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*--------------------------------------------------------------------+
	  | Compact Flash, uses 2 Chip Selects (2 & 6)
	  +-------------------------------------------------------------------*/
	mtebc(PB6AP,
	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);

	mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);

	/*--------------------------------------------------------------------+
	  | BME-32. Initialize bank 7 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(PB7AP,
	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);

	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*--------------------------------------------------------------------+
	 * Setup the interrupt controller polarities, triggers, etc.
	 +-------------------------------------------------------------------*/
	/*
	 * Because of the interrupt handling rework to handle 440GX interrupts
	 * with the common code, we needed to change names of the UIC registers.
	 * Here the new relationship:
	 *
	 * U-Boot name	440GX name
	 * -----------------------
	 * UIC0		UICB0
	 * UIC1		UIC0
	 * UIC2		UIC1
	 * UIC3		UIC2
	 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
	mtdcr (UIC1ER, 0x00000000);	/* disable all */
	mtdcr (UIC1CR, 0x00000000);	/* all non- critical */
	mtdcr (UIC1PR, 0xfffffe03);	/* polarity */
	mtdcr (UIC1TR, 0x01c00000);	/* trigger edge vs level */
	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */

	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
	mtdcr (UIC2ER, 0x00000000);	/* disable all */
	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC2PR, 0xffffc8ff);	/* polarity */
	mtdcr (UIC2TR, 0x00ff0000);	/* trigger edge vs level */
	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC2SR, 0xffffffff);	/* clear all */

	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
	mtdcr (UIC3ER, 0x00000000);	/* disable all */
	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC3PR, 0xffff83ff);	/* polarity */
	mtdcr (UIC3TR, 0x00ff8c0f);	/* trigger edge vs level */
	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC3SR, 0xffffffff);	/* clear all */

	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
	mtdcr (UIC0ER, 0x00000000);	/* disable all */
	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC0PR, 0xfc000000);
	mtdcr (UIC0TR, 0x00000000);
	mtdcr (UIC0VR, 0x00000001);

	fpga_init();

	return 0;
}

/*************************************************************************
 *  checkboard
 *
 *  Dump pertinent info to the console
 ************************************************************************/
int checkboard (void)
{
	sys_info_t sysinfo;
	unsigned char brd_rev, brd_id;
	unsigned short sernum;
	unsigned char opto_rev, opto_id;
	OPTO_FPGA_REGS_ST *opto_ps;

	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;

	opto_rev = (unsigned char)((opto_ps->revision_ul &
				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);

	opto_id = (unsigned char)((opto_ps->revision_ul &
				   SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
				  >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);

	brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
				   SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
				  >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);

	brd_id = (unsigned char)((opto_ps->boardinfo_ul &
				  SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
				 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);

	get_sys_info (&sysinfo);

	sernum = sbcommon_get_serial_number();
	printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
	printf ("%s\n", METROBOX_U_BOOT_REL_STR);

	printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
	if (sbcommon_get_master()) {
		printf("Slot 0 - Master\nSlave board");
		if (sbcommon_secondary_present())
			printf(" present\n");
		else
			printf(" not detected\n");
	} else {
		printf("Slot 1 - Slave\n\n");
	}

	printf ("OptoFPGA ID:\t0x%02X\tRev:  0x%02X\n", opto_id, opto_rev);
	printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, board_id_as[brd_id].name);

	/* Fix the ack in the bme 32 */
	udelay(5000);
	out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
	asm("eieio");


	return (0);
}

/*************************************************************************
 *  misc_init_f
 *
 *  Initialize I2C bus one to gain access to the fans
 ************************************************************************/
int misc_init_f (void)
{
	/* Turn on fans */
	sbcommon_fans();

	return (0);
}

/*************************************************************************
 *  misc_init_r
 *
 *  Do nothing.
 ************************************************************************/
int misc_init_r (void)
{
	unsigned short sernum;
	char envstr[255];
	uchar enetaddr[6];
	unsigned char opto_rev;
	OPTO_FPGA_REGS_ST *opto_ps;

	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;

	if(NULL != getenv("secondserial")) {
	    puts("secondserial is set, switching to second serial port\n");
	    setenv("stderr", "serial1");
	    setenv("stdout", "serial1");
	    setenv("stdin", "serial1");
	}

	setenv("ubrelver", METROBOX_U_BOOT_REL_STR);

	memset(envstr, 0, 255);
	sprintf (envstr, "Built %s %s by %s",
		 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
	setenv("bldstr", envstr);
	saveenv();

	if( getenv("autorecover")) {
		setenv("autorecover", NULL);
		saveenv();
		sernum = sbcommon_get_serial_number();

		printf("\nSetting up environment for automatic filesystem recovery\n");
		/*
		 * Setup default bootargs
		 */
		memset(envstr, 0, 255);
		sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
			"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
			sernum, sernum);
		setenv("bootargs", envstr);

		/*
		 * Setup Default boot command
		 */
		setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
		       "fatload ide 0 8100000 pramdisk;"
		       "bootm 8000000 8100000");

		printf("Done.  Please type allow the system to continue to boot\n");
	}

	if( getenv("fakeled")) {
		setenv("bootdelay", "-1");
		saveenv();
		printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
		opto_rev = (unsigned char)((opto_ps->revision_ul &
					    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
					   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);

		if(0x12 <= opto_rev) {
			opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
		}
	}

#ifdef CONFIG_HAS_ETH0
	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
		board_get_enetaddr(0, enetaddr);
		eth_setenv_enetaddr("ethaddr", enetaddr);
	}
#endif

#ifdef CONFIG_HAS_ETH1
	if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
		board_get_enetaddr(1, enetaddr);
		eth_setenv_enetaddr("eth1addr", enetaddr);
	}
#endif

#ifdef CONFIG_HAS_ETH2
	if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
		board_get_enetaddr(2, enetaddr);
		eth_setenv_enetaddr("eth2addr", enetaddr);
	}
#endif

#ifdef CONFIG_HAS_ETH3
	if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
		board_get_enetaddr(3, enetaddr);
		eth_setenv_enetaddr("eth3addr", enetaddr);
	}
#endif

	return (0);
}

/*************************************************************************
 *  ide_set_reset
 ************************************************************************/
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
	OPTO_FPGA_REGS_ST *opto_ps;
	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;

	if (on) {		/* assert RESET */
	    opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
	} else {		/* release RESET */
	    opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
	}
}
#endif /* CONFIG_IDE_RESET */

/*************************************************************************
 *  fpga_init
 ************************************************************************/
void fpga_init(void)
{
	OPTO_FPGA_REGS_ST *opto_ps;
	unsigned char opto_rev;
	unsigned long tmp;

	/* Ensure we have power all around */
	udelay(500);

	/*
	 * Take appropriate hw bits out of reset
	 */
	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;

	tmp =
	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
	    SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
	opto_ps->reset_ul = tmp;
	/*
	 * Turn on the 'Slow Blink' for the System Error Led.
	 * Ensure FPGA rev is up to at least rev 0x12
	 */
	opto_rev = (unsigned char)((opto_ps->revision_ul &
				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
	if(0x12 <= opto_rev) {
	    opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
	}

	asm("eieio");

	return;
}

int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	unsigned short sernum;
	char envstr[255];

	sernum = sbcommon_get_serial_number();

	memset(envstr, 0, 255);
	/*
	 * Setup our ip address
	 */
	sprintf(envstr, "10.100.60.%d", sernum);

	setenv("ipaddr", envstr);
	/*
	 * Setup the host ip address
	 */
	setenv("serverip", "10.100.17.10");

	/*
	 * Setup default bootargs
	 */
	memset(envstr, 0, 255);

	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
		"rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
		"nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
		":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
		sernum, sernum, sernum);

	setenv("bootargs_nfs", envstr);
	setenv("bootargs", envstr);

	/*
	 * Setup CF bootargs
	 */
	memset(envstr, 0, 255);
	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
		"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
		sernum, sernum);

	setenv("bootargs_cf", envstr);

	/*
	 * Setup Default boot command
	 */
	setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
	setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");

	/*
	 * Setup compact flash boot command
	 */
	setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");

	saveenv();


	return(1);
}

int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	unsigned short sernum;
	char envstr[255];

	sernum = sbcommon_get_serial_number();

	printf("\nSetting up environment for filesystem recovery\n");
	/*
	 * Setup default bootargs
	 */
	memset(envstr, 0, 255);
	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
		"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
		sernum, sernum);

	setenv("bootargs", envstr);

	/*
	 * Setup Default boot command
	 */
	setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
	       "fatload ide 0 8100000 pramdisk;"
	       "bootm 8000000 8100000");

	printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
	       " please type fsrecover.sh<cr>\n");

	return(1);
}

U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
	   "Set environment to factory defaults", "");

U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
	   "Set environment to allow for fs recovery", "");
Commit	Line	Data
b79316f2 SR	1	/*
	2	* Copyright (c) 2005
	3	* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23	#include <config.h>
	24	#include <common.h>
	25	#include <command.h>
	26	#include "metrobox.h"
	27	#include "metrobox_version.h"
561858ee	28	#include <timestamp.h>
b79316f2 SR	29	#include <asm/processor.h>
	30	#include <asm/io.h>
	31	#include <spd_sdram.h>
	32	#include <i2c.h>
b79316f2	33	#include "../common/sb_common.h"
d2567be9 WD	34	#if defined(CONFIG_HAS_ETH0) \|\| defined(CONFIG_HAS_ETH1) \|\| \
	35	defined(CONFIG_HAS_ETH2) \|\| defined(CONFIG_HAS_ETH3)
	36	#include <net.h>
	37	#endif
b79316f2	38
b79316f2 SR	39	void fpga_init (void);
	40
	41	METROBOX_BOARD_ID_ST board_id_as[] =
	42	{ {"Undefined"}, /* Not specified */
	43	{"2x10Gb"}, /* 2 ports, 10 GbE */
	44	{"20x1Gb"}, /* 20 ports, 1 GbE */
	45	{"Reserved"}, /* Reserved for future use */
	46	};
	47
b79316f2 SR	48	/*************************************************************************
	49	* board_early_init_f
	50	*
	51	* Setup chip selects, initialize the Opto-FPGA, initialize
	52	* interrupt polarity and triggers.
b79316f2 SR	53	************************************************************************/
	54	int board_early_init_f (void)
	55	{
	56	ppc440_gpio_regs_t *gpio_regs;
	57
	58	/* Enable GPIO interrupts */
d1c3b275	59	mtsdr(SDR0_PFC0, 0x00103E00);
b79316f2 SR	60
b79316f2 SR	61	/* Setup access for LEDs, and system topology info */
6d0f6bcf	62	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
b79316f2 SR	63	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
	64	gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
	65
	66	/* Turn on all the leds for now */
	67	gpio_regs->out = SBCOMMON_GPIO_LEDS;
	68
	69	/*--------------------------------------------------------------------+
	70	\| Initialize EBC CONFIG
	71	+-------------------------------------------------------------------*/
d1c3b275	72	mtebc(EBC0_CFG,
b79316f2 SR	73	EBC_CFG_LE_UNLOCK \| EBC_CFG_PTD_ENABLE \|
	74	EBC_CFG_RTC_64PERCLK \| EBC_CFG_ATC_PREVIOUS \|
	75	EBC_CFG_DTC_PREVIOUS \| EBC_CFG_CTC_PREVIOUS \|
	76	EBC_CFG_EMC_DEFAULT \| EBC_CFG_PME_DISABLE \|
	77	EBC_CFG_PR_32);
	78
	79	/*--------------------------------------------------------------------+
	80	\| 1/2 MB FLASH. Initialize bank 0 with default values.
	81	+-------------------------------------------------------------------*/
d1c3b275	82	mtebc(PB0AP,
b79316f2 SR	83	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(8) \|
	84	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_CSN_ENCODE(1) \|
	85	EBC_BXAP_OEN_ENCODE(1)\| EBC_BXAP_WBN_ENCODE(1) \|
	86	EBC_BXAP_WBF_ENCODE(1)\| EBC_BXAP_TH_ENCODE(1) \|
	87	EBC_BXAP_RE_DISABLED \| EBC_BXAP_BEM_WRITEONLY \|
	88	EBC_BXAP_PEN_DISABLED);
	89
d1c3b275	90	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) \|
b79316f2 SR	91	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT);
	92	/*--------------------------------------------------------------------+
	93	\| 8KB NVRAM/RTC. Initialize bank 1 with default values.
	94	+-------------------------------------------------------------------*/
d1c3b275	95	mtebc(PB1AP,
b79316f2 SR	96	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(10) \|
	97	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_CSN_ENCODE(1) \|
	98	EBC_BXAP_OEN_ENCODE(1)\| EBC_BXAP_WBN_ENCODE(1) \|
	99	EBC_BXAP_WBF_ENCODE(1)\| EBC_BXAP_TH_ENCODE(1) \|
	100	EBC_BXAP_RE_DISABLED \| EBC_BXAP_BEM_WRITEONLY \|
	101	EBC_BXAP_PEN_DISABLED);
	102
d1c3b275	103	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) \|
b79316f2 SR	104	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT);
	105
	106	/*--------------------------------------------------------------------+
	107	\| Compact Flash, uses 2 Chip Selects (2 & 6)
	108	+-------------------------------------------------------------------*/
d1c3b275	109	mtebc(PB2AP,
b79316f2 SR	110	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(8) \|
	111	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_CSN_ENCODE(1) \|
	112	EBC_BXAP_OEN_ENCODE(1)\| EBC_BXAP_WBN_ENCODE(1) \|
	113	EBC_BXAP_WBF_ENCODE(0)\| EBC_BXAP_TH_ENCODE(1) \|
	114	EBC_BXAP_RE_DISABLED \| EBC_BXAP_BEM_WRITEONLY \|
	115	EBC_BXAP_PEN_DISABLED);
	116
d1c3b275	117	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) \|
b79316f2 SR	118	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT);
	119
	120	/*--------------------------------------------------------------------+
	121	\| OPTO & OFEM FPGA. Initialize bank 3 with default values.
	122	+-------------------------------------------------------------------*/
d1c3b275	123	mtebc(PB3AP,
b79316f2 SR	124	EBC_BXAP_RE_ENABLED \| EBC_BXAP_SOR_NONDELAYED \|
	125	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(3) \|
	126	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(0) \|
	127	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_PEN_DISABLED \|
	128	EBC_BXAP_OEN_ENCODE(1) \| EBC_BXAP_BEM_RW);
	129
d1c3b275	130	mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) \|
b79316f2 SR	131	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
	132
	133	/*--------------------------------------------------------------------+
	134	\| MAC A for metrobox
	135	\| MAC A & B for Kamino. OFEM FPGA decodes the addresses
	136	\| Initialize bank 4 with default values.
	137	+-------------------------------------------------------------------*/
d1c3b275	138	mtebc(PB4AP,
b79316f2 SR	139	EBC_BXAP_RE_ENABLED \| EBC_BXAP_SOR_NONDELAYED \|
	140	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(3) \|
	141	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(0) \|
	142	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_PEN_DISABLED \|
	143	EBC_BXAP_OEN_ENCODE(1) \| EBC_BXAP_BEM_RW);
	144
d1c3b275	145	mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) \|
b79316f2 SR	146	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
	147
	148	/*--------------------------------------------------------------------+
	149	\| Metrobox MAC B Initialize bank 5 with default values.
	150	\| KA REF FPGA Initialize bank 5 with default values.
	151	+-------------------------------------------------------------------*/
d1c3b275	152	mtebc(PB5AP,
b79316f2 SR	153	EBC_BXAP_RE_ENABLED \| EBC_BXAP_SOR_NONDELAYED \|
	154	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(3) \|
	155	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(0) \|
	156	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_PEN_DISABLED \|
	157	EBC_BXAP_OEN_ENCODE(1) \| EBC_BXAP_BEM_RW);
	158
d1c3b275	159	mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) \|
b79316f2 SR	160	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
	161
	162	/*--------------------------------------------------------------------+
	163	\| Compact Flash, uses 2 Chip Selects (2 & 6)
	164	+-------------------------------------------------------------------*/
d1c3b275	165	mtebc(PB6AP,
b79316f2 SR	166	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(8) \|
	167	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_CSN_ENCODE(1) \|
	168	EBC_BXAP_OEN_ENCODE(1)\| EBC_BXAP_WBN_ENCODE(1) \|
	169	EBC_BXAP_WBF_ENCODE(0)\| EBC_BXAP_TH_ENCODE(1) \|
	170	EBC_BXAP_RE_DISABLED \| EBC_BXAP_BEM_WRITEONLY \|
	171	EBC_BXAP_PEN_DISABLED);
	172
d1c3b275	173	mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) \|
b79316f2 SR	174	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT);
	175
	176	/*--------------------------------------------------------------------+
	177	\| BME-32. Initialize bank 7 with default values.
	178	+-------------------------------------------------------------------*/
d1c3b275	179	mtebc(PB7AP,
b79316f2 SR	180	EBC_BXAP_RE_ENABLED \| EBC_BXAP_SOR_NONDELAYED \|
	181	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(3) \|
	182	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(0) \|
	183	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_PEN_DISABLED \|
	184	EBC_BXAP_OEN_ENCODE(1) \| EBC_BXAP_BEM_RW);
	185
d1c3b275	186	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) \|
b79316f2 SR	187	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
b79316f2 SR	188
b79316f2 SR	189	/*--------------------------------------------------------------------+
	190	* Setup the interrupt controller polarities, triggers, etc.
	191	+-------------------------------------------------------------------*/
5de85140 SR	192	/*
	193	* Because of the interrupt handling rework to handle 440GX interrupts
	194	* with the common code, we needed to change names of the UIC registers.
	195	* Here the new relationship:
	196	*
	197	* U-Boot name 440GX name
	198	* -----------------------
	199	* UIC0 UICB0
	200	* UIC1 UIC0
	201	* UIC2 UIC1
	202	* UIC3 UIC2
	203	*/
952e7760 SR	204	mtdcr (UIC1SR, 0xffffffff); /* clear all */
	205	mtdcr (UIC1ER, 0x00000000); /* disable all */
	206	mtdcr (UIC1CR, 0x00000000); /* all non- critical */
	207	mtdcr (UIC1PR, 0xfffffe03); /* polarity */
	208	mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
	209	mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
	210	mtdcr (UIC1SR, 0xffffffff); /* clear all */
	211
	212	mtdcr (UIC2SR, 0xffffffff); /* clear all */
	213	mtdcr (UIC2ER, 0x00000000); /* disable all */
	214	mtdcr (UIC2CR, 0x00000000); /* all non-critical */
	215	mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
	216	mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
	217	mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
	218	mtdcr (UIC2SR, 0xffffffff); /* clear all */
	219
	220	mtdcr (UIC3SR, 0xffffffff); /* clear all */
	221	mtdcr (UIC3ER, 0x00000000); /* disable all */
	222	mtdcr (UIC3CR, 0x00000000); /* all non-critical */
	223	mtdcr (UIC3PR, 0xffff83ff); /* polarity */
	224	mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
	225	mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
	226	mtdcr (UIC3SR, 0xffffffff); /* clear all */
	227
	228	mtdcr (UIC0SR, 0xfc000000); /* clear all */
	229	mtdcr (UIC0ER, 0x00000000); /* disable all */
	230	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
	231	mtdcr (UIC0PR, 0xfc000000);
	232	mtdcr (UIC0TR, 0x00000000);
	233	mtdcr (UIC0VR, 0x00000001);
b79316f2 SR	234
	235	fpga_init();
	236
	237	return 0;
	238	}
	239
b79316f2 SR	240	/*************************************************************************
	241	* checkboard
	242	*
	243	* Dump pertinent info to the console
b79316f2 SR	244	************************************************************************/
	245	int checkboard (void)
	246	{
	247	sys_info_t sysinfo;
	248	unsigned char brd_rev, brd_id;
	249	unsigned short sernum;
	250	unsigned char opto_rev, opto_id;
	251	OPTO_FPGA_REGS_ST *opto_ps;
	252
6d0f6bcf	253	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
b79316f2 SR	254
	255	opto_rev = (unsigned char)((opto_ps->revision_ul &
	256	SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
	257	>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
	258
	259	opto_id = (unsigned char)((opto_ps->revision_ul &
	260	SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
	261	>> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
	262
	263	brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
	264	SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
	265	>> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
	266
	267	brd_id = (unsigned char)((opto_ps->boardinfo_ul &
	268	SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
	269	>> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
	270
	271	get_sys_info (&sysinfo);
	272
	273	sernum = sbcommon_get_serial_number();
	274	printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
	275	printf ("%s\n", METROBOX_U_BOOT_REL_STR);
	276
561858ee	277	printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
b79316f2 SR	278	if (sbcommon_get_master()) {
	279	printf("Slot 0 - Master\nSlave board");
	280	if (sbcommon_secondary_present())
	281	printf(" present\n");
	282	else
	283	printf(" not detected\n");
	284	} else {
	285	printf("Slot 1 - Slave\n\n");
	286	}
	287
	288	printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
bde63587	289	printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
b79316f2	290
b79316f2 SR	291	/* Fix the ack in the bme 32 */
b79316f2 SR	292	udelay(5000);
6d0f6bcf	293	out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
b79316f2 SR	294	asm("eieio");
	295
	296
	297	return (0);
	298	}
	299
b79316f2 SR	300	/*************************************************************************
	301	* misc_init_f
	302	*
	303	* Initialize I2C bus one to gain access to the fans
b79316f2 SR	304	************************************************************************/
	305	int misc_init_f (void)
	306	{
b79316f2 SR	307	/* Turn on fans */
	308	sbcommon_fans();
	309
	310	return (0);
	311	}
3d078ce6	312
b79316f2 SR	313	/*************************************************************************
	314	* misc_init_r
	315	*
	316	* Do nothing.
b79316f2 SR	317	************************************************************************/
	318	int misc_init_r (void)
	319	{
	320	unsigned short sernum;
	321	char envstr[255];
d8d21e69	322	uchar enetaddr[6];
b79316f2 SR	323	unsigned char opto_rev;
	324	OPTO_FPGA_REGS_ST *opto_ps;
	325
6d0f6bcf	326	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
b79316f2 SR	327
	328	if(NULL != getenv("secondserial")) {
	329	puts("secondserial is set, switching to second serial port\n");
	330	setenv("stderr", "serial1");
	331	setenv("stdout", "serial1");
	332	setenv("stdin", "serial1");
	333	}
	334
	335	setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
	336
	337	memset(envstr, 0, 255);
561858ee PT	338	sprintf (envstr, "Built %s %s by %s",
561858ee PT	339	U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
b79316f2 SR	340	setenv("bldstr", envstr);
	341	saveenv();
	342
	343	if( getenv("autorecover")) {
	344	setenv("autorecover", NULL);
	345	saveenv();
	346	sernum = sbcommon_get_serial_number();
	347
	348	printf("\nSetting up environment for automatic filesystem recovery\n");
	349	/*
	350	* Setup default bootargs
	351	*/
	352	memset(envstr, 0, 255);
	353	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
	354	"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
	355	sernum, sernum);
	356	setenv("bootargs", envstr);
	357
	358	/*
	359	* Setup Default boot command
	360	*/
	361	setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
	362	"fatload ide 0 8100000 pramdisk;"
	363	"bootm 8000000 8100000");
	364
	365	printf("Done. Please type allow the system to continue to boot\n");
	366	}
	367
	368	if( getenv("fakeled")) {
	369	setenv("bootdelay", "-1");
	370	saveenv();
	371	printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
	372	opto_rev = (unsigned char)((opto_ps->revision_ul &
	373	SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
	374	>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
	375
	376	if(0x12 <= opto_rev) {
	377	opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
	378	}
	379	}
	380
d8d21e69 MF	381	#ifdef CONFIG_HAS_ETH0
	382	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
	383	board_get_enetaddr(0, enetaddr);
0baeca4b	384	eth_setenv_enetaddr("ethaddr", enetaddr);
d8d21e69 MF	385	}
	386	#endif
	387
	388	#ifdef CONFIG_HAS_ETH1
	389	if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
	390	board_get_enetaddr(1, enetaddr);
0baeca4b	391	eth_setenv_enetaddr("eth1addr", enetaddr);
d8d21e69 MF	392	}
	393	#endif
	394
	395	#ifdef CONFIG_HAS_ETH2
	396	if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
	397	board_get_enetaddr(2, enetaddr);
0baeca4b	398	eth_setenv_enetaddr("eth2addr", enetaddr);
d8d21e69 MF	399	}
	400	#endif
	401
	402	#ifdef CONFIG_HAS_ETH3
	403	if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
	404	board_get_enetaddr(3, enetaddr);
0baeca4b	405	eth_setenv_enetaddr("eth3addr", enetaddr);
d8d21e69 MF	406	}
	407	#endif
	408
b79316f2 SR	409	return (0);
	410	}
	411
b79316f2 SR	412	/*************************************************************************
b79316f2 SR	413	* ide_set_reset
b79316f2 SR	414	************************************************************************/
	415	#ifdef CONFIG_IDE_RESET
	416	void ide_set_reset(int on)
	417	{
	418	OPTO_FPGA_REGS_ST *opto_ps;
6d0f6bcf	419	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
b79316f2 SR	420
	421	if (on) { /* assert RESET */
	422	opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
	423	} else { /* release RESET */
	424	opto_ps->reset_ul \|= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
	425	}
	426	}
	427	#endif /* CONFIG_IDE_RESET */
	428
	429	/*************************************************************************
	430	* fpga_init
b79316f2 SR	431	************************************************************************/
	432	void fpga_init(void)
	433	{
	434	OPTO_FPGA_REGS_ST *opto_ps;
	435	unsigned char opto_rev;
	436	unsigned long tmp;
	437
	438	/* Ensure we have power all around */
	439	udelay(500);
	440
	441	/*
	442	* Take appropriate hw bits out of reset
	443	*/
6d0f6bcf	444	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
b79316f2 SR	445
	446	tmp =
	447	SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK \|
	448	SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK \|
	449	SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK \|
	450	SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK \|
	451	SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK \|
	452	SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK \|
	453	SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK \|
	454	SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK \|
	455	SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK \|
	456	SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK \|
	457	SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK \|
	458	SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK \|
	459	SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK \|
	460	SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK \|
	461	SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK \|
	462	SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK \|
	463	SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK \|
	464	SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
	465	opto_ps->reset_ul = tmp;
	466	/*
	467	* Turn on the 'Slow Blink' for the System Error Led.
	468	* Ensure FPGA rev is up to at least rev 0x12
	469	*/
	470	opto_rev = (unsigned char)((opto_ps->revision_ul &
	471	SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
	472	>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
	473	if(0x12 <= opto_rev) {
	474	opto_ps->control_ul \|= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
	475	}
	476
	477	asm("eieio");
	478
	479	return;
	480	}
	481
54841ab5	482	int metroboxSetupVars(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
b79316f2 SR	483	{
	484	unsigned short sernum;
	485	char envstr[255];
	486
	487	sernum = sbcommon_get_serial_number();
	488
	489	memset(envstr, 0, 255);
	490	/*
	491	* Setup our ip address
	492	*/
	493	sprintf(envstr, "10.100.60.%d", sernum);
	494
	495	setenv("ipaddr", envstr);
	496	/*
	497	* Setup the host ip address
	498	*/
	499	setenv("serverip", "10.100.17.10");
	500
	501	/*
	502	* Setup default bootargs
	503	*/
	504	memset(envstr, 0, 255);
	505
	506	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
	507	"rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
	508	"nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
	509	":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
	510	sernum, sernum, sernum);
	511
	512	setenv("bootargs_nfs", envstr);
	513	setenv("bootargs", envstr);
	514
	515	/*
	516	* Setup CF bootargs
	517	*/
	518	memset(envstr, 0, 255);
	519	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
	520	"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
	521	sernum, sernum);
	522
	523	setenv("bootargs_cf", envstr);
	524
	525	/*
	526	* Setup Default boot command
	527	*/
	528	setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
	529	setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
	530
	531	/*
	532	* Setup compact flash boot command
	533	*/
	534	setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
	535
	536	saveenv();
	537
	538
	539	return(1);
	540	}
	541
54841ab5	542	int metroboxRecover(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
b79316f2 SR	543	{
	544	unsigned short sernum;
	545	char envstr[255];
	546
	547	sernum = sbcommon_get_serial_number();
	548
	549	printf("\nSetting up environment for filesystem recovery\n");
	550	/*
	551	* Setup default bootargs
	552	*/
	553	memset(envstr, 0, 255);
	554	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
	555	"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
	556	sernum, sernum);
	557
	558	setenv("bootargs", envstr);
	559
	560	/*
	561	* Setup Default boot command
	562	*/
	563	setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
	564	"fatload ide 0 8100000 pramdisk;"
	565	"bootm 8000000 8100000");
	566
	567	printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
	568	" please type fsrecover.sh<cr>\n");
	569
	570	return(1);
	571	}
	572
b79316f2	573	U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
a89c33db	574	"Set environment to factory defaults", "");
b79316f2 SR	575
b79316f2 SR	576	U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
a89c33db	577	"Set environment to allow for fs recovery", "");