[people/ms/u-boot.git] / board / sbc8349 / pci.c

/*
 * pci.c -- WindRiver SBC8349 PCI board support.
 * Copyright (c) 2006 Wind River Systems, Inc.
 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
 *
 * Based on MPC8349 PCI support but w/o PIB related code.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>

DECLARE_GLOBAL_DATA_PTR;

static struct pci_region pci1_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
		size: CONFIG_SYS_PCI1_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI1_IO_BASE,
		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
		size: CONFIG_SYS_PCI1_IO_SIZE,
		flags: PCI_REGION_IO
	},
	{
		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
		size: CONFIG_SYS_PCI1_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
};

/*
 * pci_init_board()
 *
 * NOTICE: PCI2 is not supported. There is only one
 * physical PCI slot on the board.
 *
 */
void
pci_init_board(void)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	struct pci_region *reg[] = { pci1_regions };

	/* Enable all 8 PCI_CLK_OUTPUTS */
	clk->occr = 0xff000000;
	udelay(2000);

	/* Configure PCI Local Access Windows */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;

	udelay(2000);

	mpc83xx_pci_init(1, reg);
}
Commit	Line	Data
91e25769 PG	1	/*
	2	* pci.c -- WindRiver SBC8349 PCI board support.
	3	* Copyright (c) 2006 Wind River Systems, Inc.
9993e196	4	* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
91e25769 PG	5	*
	6	* Based on MPC8349 PCI support but w/o PIB related code.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
91e25769 PG	9	*/
	10
	11	#include <asm/mmu.h>
9993e196	12	#include <asm/io.h>
91e25769	13	#include <common.h>
9993e196	14	#include <mpc83xx.h>
91e25769	15	#include <pci.h>
91e25769	16	#include <i2c.h>
9993e196	17	#include <asm/fsl_i2c.h>
91e25769 PG	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
9993e196 KP	21	static struct pci_region pci1_regions[] = {
	22	{
	23	bus_start: CONFIG_SYS_PCI1_MEM_BASE,
	24	phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
	25	size: CONFIG_SYS_PCI1_MEM_SIZE,
	26	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
	27	},
	28	{
	29	bus_start: CONFIG_SYS_PCI1_IO_BASE,
	30	phys_start: CONFIG_SYS_PCI1_IO_PHYS,
	31	size: CONFIG_SYS_PCI1_IO_SIZE,
	32	flags: PCI_REGION_IO
	33	},
	34	{
	35	bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
	36	phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
	37	size: CONFIG_SYS_PCI1_MMIO_SIZE,
	38	flags: PCI_REGION_MEM
91e25769	39	},
91e25769 PG	40	};
91e25769 PG	41
9993e196	42	/*
91e25769 PG	43	* pci_init_board()
	44	*
	45	* NOTICE: PCI2 is not supported. There is only one
	46	* physical PCI slot on the board.
	47	*
	48	*/
	49	void
	50	pci_init_board(void)
	51	{
9993e196 KP	52	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
	53	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
	54	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	55	struct pci_region *reg[] = { pci1_regions };
91e25769	56
9993e196	57	/* Enable all 8 PCI_CLK_OUTPUTS */
91e25769 PG	58	clk->occr = 0xff000000;
	59	udelay(2000);
	60
9993e196	61	/* Configure PCI Local Access Windows */
6d0f6bcf	62	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
91e25769 PG	63	pci_law[0].ar = LAWAR_EN \| LAWAR_SIZE_1G;
91e25769 PG	64
6d0f6bcf	65	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
91e25769 PG	66	pci_law[1].ar = LAWAR_EN \| LAWAR_SIZE_4M;
91e25769 PG	67
9993e196	68	udelay(2000);
5b8bc606	69
6aa3d3bf	70	mpc83xx_pci_init(1, reg);
5b8bc606	71	}