[people/ms/u-boot.git] / board / sbc8349 / sbc8349.c

/*
 * sbc8349.c -- WindRiver SBC8349 board support.
 * Copyright (c) 2006-2007 Wind River Systems, Inc.
 *
 * Paul Gortmaker <paul.gortmaker@windriver.com>
 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spd_sdram.h>
#include <miiphy.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

int fixed_sdram(void);
void sdram_init(void);

#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
void ddr_enable_ecc(unsigned int dram_size);
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f (void)
{
	return 0;
}
#endif

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)

int dram_init(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/* set total bus SDRAM size(bytes)  -- DDR */
	gd->ram_size = msize * 1024 * 1024;

	return 0;
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	u32 msize = CONFIG_SYS_DDR_SIZE;
	u32 ddr_size = msize << 20;	/* DDR size in bytes */
	u32 ddr_size_log2 = __ilog2(msize);

	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);

#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currently any ddr size other than 256 is not supported
#endif

#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
	im->ddr.csbnds[2].csbnds =
		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
				CSBNDS_EA_SHIFT) & CSBNDS_EA);
	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;

	/* currently we use only one CS, so disable the other banks */
	im->ddr.cs_config[0] = 0;
	im->ddr.cs_config[1] = 0;
	im->ddr.cs_config[3] = 0;

	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;

	im->ddr.sdram_cfg =
		SDRAM_CFG_SREN
#if defined(CONFIG_DDR_2T_TIMING)
		| SDRAM_CFG_2T_EN
#endif
		| SDRAM_CFG_SDRAM_TYPE_DDR1;
#if defined (CONFIG_DDR_32BIT)
	/* for 32-bit mode burst length is 8 */
	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
#endif
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;

	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	udelay(200);

	/* enable DDR controller */
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	return msize;
}
#endif/*!CONFIG_SYS_SPD_EEPROM*/


int checkboard (void)
{
	puts("Board: Wind River SBC834x\n");
	return 0;
}

/*
 * if board is fitted with SDRAM
 */
#if defined(CONFIG_SYS_BR2_PRELIM)  \
	&& defined(CONFIG_SYS_OR2_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
/*
 * Initialize SDRAM memory on the Local Bus.
 */

void sdram_init(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile fsl_lbc_t *lbc = &immap->im_lbc;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;

	puts("\n   SDRAM on Local Bus: ");
	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
	 */

	/* setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
	asm("sync");
	/*1 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*2 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*3 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*4 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*5 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*6 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*7 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*8 times*/
	*sdram_addr = 0xff;
	udelay(100);

	/* 0x58636733; mode register write operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);
}
#else
void sdram_init(void)
{
	puts("   SDRAM on Local Bus: Disabled in config\n");
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif

	return 0;
}
#endif
Commit	Line	Data
91e25769 PG	1	/*
	2	* sbc8349.c -- WindRiver SBC8349 board support.
	3	* Copyright (c) 2006-2007 Wind River Systems, Inc.
	4	*
	5	* Paul Gortmaker <paul.gortmaker@windriver.com>
	6	* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
91e25769 PG	9	*/
	10
	11	#include <common.h>
	12	#include <ioports.h>
	13	#include <mpc83xx.h>
	14	#include <asm/mpc8349_pci.h>
	15	#include <i2c.h>
91e25769	16	#include <spd_sdram.h>
a30a549a	17	#include <miiphy.h>
b3458d2c	18	#if defined(CONFIG_OF_LIBFDT)
2408b3f2	19	#include <libfdt.h>
91e25769 PG	20	#endif
91e25769 PG	21
088454cd SG	22	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	23
91e25769 PG	24	int fixed_sdram(void);
	25	void sdram_init(void);
	26
0f898604	27	#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
91e25769 PG	28	void ddr_enable_ecc(unsigned int dram_size);
	29	#endif
	30
	31	#ifdef CONFIG_BOARD_EARLY_INIT_F
	32	int board_early_init_f (void)
	33	{
	34	return 0;
	35	}
	36	#endif
	37
	38	#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
	39
f1683aa7	40	int dram_init(void)
91e25769	41	{
6d0f6bcf	42	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
91e25769 PG	43	u32 msize = 0;
	44
	45	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
	46	return -1;
	47
91e25769	48	/* DDR SDRAM - Main SODIMM */
6d0f6bcf	49	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
91e25769 PG	50	#if defined(CONFIG_SPD_EEPROM)
	51	msize = spd_sdram();
	52	#else
	53	msize = fixed_sdram();
	54	#endif
	55	/*
	56	* Initialize SDRAM if it is on local bus.
	57	*/
	58	sdram_init();
	59
	60	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	61	/*
	62	* Initialize and enable DDR ECC.
	63	*/
	64	ddr_enable_ecc(msize * 1024 * 1024);
	65	#endif
088454cd SG	66	/* set total bus SDRAM size(bytes) -- DDR */
	67	gd->ram_size = msize * 1024 * 1024;
	68
	69	return 0;
91e25769 PG	70	}
	71
	72	#if !defined(CONFIG_SPD_EEPROM)
	73	/*************************************************************************
	74	* fixed sdram init -- doesn't use serial presence detect.
	75	************************************************************************/
	76	int fixed_sdram(void)
	77	{
6d0f6bcf	78	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
2e651b24 JH	79	u32 msize = CONFIG_SYS_DDR_SIZE;
	80	u32 ddr_size = msize << 20; /* DDR size in bytes */
	81	u32 ddr_size_log2 = __ilog2(msize);
	82
6d0f6bcf	83	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
91e25769 PG	84	im->sysconf.ddrlaw[0].ar = LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
91e25769 PG	85
6d0f6bcf	86	#if (CONFIG_SYS_DDR_SIZE != 256)
91e25769 PG	87	#warning Currently any ddr size other than 256 is not supported
91e25769 PG	88	#endif
2e651b24 JH	89
	90	#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
	91	#warning Chip select bounds is only configurable in 16MB increments
	92	#endif
	93	im->ddr.csbnds[2].csbnds =
	94	((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) \|
	95	(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
	96	CSBNDS_EA_SHIFT) & CSBNDS_EA);
	97	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
91e25769 PG	98
	99	/* currently we use only one CS, so disable the other banks */
	100	im->ddr.cs_config[0] = 0;
	101	im->ddr.cs_config[1] = 0;
	102	im->ddr.cs_config[3] = 0;
	103
6d0f6bcf JCPV	104	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
6d0f6bcf JCPV	105	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
91e25769 PG	106
	107	im->ddr.sdram_cfg =
	108	SDRAM_CFG_SREN
	109	#if defined(CONFIG_DDR_2T_TIMING)
	110	\| SDRAM_CFG_2T_EN
	111	#endif
bbea46f7	112	\| SDRAM_CFG_SDRAM_TYPE_DDR1;
91e25769 PG	113	#if defined (CONFIG_DDR_32BIT)
	114	/* for 32-bit mode burst length is 8 */
	115	im->ddr.sdram_cfg \|= (SDRAM_CFG_32_BE \| SDRAM_CFG_8_BE);
	116	#endif
6d0f6bcf	117	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
91e25769	118
6d0f6bcf	119	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
91e25769 PG	120	udelay(200);
	121
	122	/* enable DDR controller */
	123	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	124	return msize;
	125	}
6d0f6bcf	126	#endif/!CONFIG_SYS_SPD_EEPROM/
91e25769 PG	127
	128
	129	int checkboard (void)
	130	{
	131	puts("Board: Wind River SBC834x\n");
	132	return 0;
	133	}
	134
	135	/*
	136	* if board is fitted with SDRAM
	137	*/
6d0f6bcf JCPV	138	#if defined(CONFIG_SYS_BR2_PRELIM) \
	139	&& defined(CONFIG_SYS_OR2_PRELIM) \
	140	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
	141	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
91e25769 PG	142	/*
	143	* Initialize SDRAM memory on the Local Bus.
	144	*/
	145
	146	void sdram_init(void)
	147	{
6d0f6bcf	148	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
f51cdaf1	149	volatile fsl_lbc_t *lbc = &immap->im_lbc;
6d0f6bcf	150	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
91e25769 PG	151
91e25769 PG	152	puts("\n SDRAM on Local Bus: ");
6d0f6bcf	153	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
91e25769 PG	154
	155	/*
	156	* Setup SDRAM Base and Option Registers, already done in cpu_init.c
	157	*/
	158
	159	/* setup mtrpt, lsrt and lbcr for LB bus */
6d0f6bcf JCPV	160	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	161	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	162	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
91e25769 PG	163	asm("sync");
	164
	165	/*
	166	* Configure the SDRAM controller Machine Mode Register.
	167	*/
6d0f6bcf	168	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
91e25769	169
6d0f6bcf	170	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
91e25769 PG	171	asm("sync");
	172	*sdram_addr = 0xff;
	173	udelay(100);
	174
6d0f6bcf	175	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
91e25769 PG	176	asm("sync");
	177	/1 times/
	178	*sdram_addr = 0xff;
	179	udelay(100);
	180	/2 times/
	181	*sdram_addr = 0xff;
	182	udelay(100);
	183	/3 times/
	184	*sdram_addr = 0xff;
	185	udelay(100);
	186	/4 times/
	187	*sdram_addr = 0xff;
	188	udelay(100);
	189	/5 times/
	190	*sdram_addr = 0xff;
	191	udelay(100);
	192	/6 times/
	193	*sdram_addr = 0xff;
	194	udelay(100);
	195	/7 times/
	196	*sdram_addr = 0xff;
	197	udelay(100);
	198	/8 times/
	199	*sdram_addr = 0xff;
	200	udelay(100);
	201
	202	/* 0x58636733; mode register write operation */
6d0f6bcf	203	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
91e25769 PG	204	asm("sync");
	205	*sdram_addr = 0xff;
	206	udelay(100);
	207
6d0f6bcf	208	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
91e25769 PG	209	asm("sync");
	210	*sdram_addr = 0xff;
	211	udelay(100);
	212	}
	213	#else
	214	void sdram_init(void)
	215	{
	216	puts(" SDRAM on Local Bus: Disabled in config\n");
	217	}
	218	#endif
	219
2408b3f2	220	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	221	int ft_board_setup(void blob, bd_t bd)
91e25769	222	{
2408b3f2 PG	223	ft_cpu_setup(blob, bd);
	224	#ifdef CONFIG_PCI
	225	ft_pci_setup(blob, bd);
	226	#endif
e895a4b0 SG	227
e895a4b0 SG	228	return 0;
91e25769 PG	229	}
91e25769 PG	230	#endif