[people/ms/u-boot.git] / board / sbc8548 / law.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>

/*
 * LAW(Local Access Window) configuration:
 *
 * 0x0000_0000	0x0fff_ffff	DDR			256M
 * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M
 * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M
 * 0xe000_0000	0xe000_ffff	CCSR			1M
 * 0xe200_0000	0xe27f_ffff	PCI1 IO			8M
 * 0xe280_0000	0xe2ff_ffff	PCIe IO			8M
 * 0xec00_0000	0xefff_ffff	FLASH (2nd bank)	64M
 * 0xf000_0000	0xf7ff_ffff	SDRAM			128M
 * 0xf8b0_0000	0xf80f_ffff	EEPROM			1M
 * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M
 *
 * If swapped CS0/CS6 via JP12+SW2.8:
 * 0xef80_0000	0xefff_ffff	FLASH (2nd bank)	8M
 * 0xfc00_0000	0xffff_ffff	FLASH (boot bank)	64M
 *
 * Notes:
 *	CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 *	If flash is 8M at default position (last 8M), no LAW needed.
 */

struct law_entry law_table[] = {
#ifdef CONFIG_SYS_ALT_BOOT
	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
#else
	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#endif
#ifndef CONFIG_SPD_EEPROM
	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
#ifdef CONFIG_SYS_LBC_SDRAM_BASE
	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
#else
	/* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
	SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
#endif
};

int num_law_entries = ARRAY_SIZE(law_table);
Commit	Line	Data
e2b159d0 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
e2b159d0 KG	8	*/
	9
	10	#include <common.h>
	11	#include <asm/fsl_law.h>
	12	#include <asm/mmu.h>
	13
	14	/*
	15	* LAW(Local Access Window) configuration:
	16	*
	17	* 0x0000_0000 0x0fff_ffff DDR 256M
	18	* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
fdc7eb90	19	* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
e2b159d0	20	* 0xe000_0000 0xe000_ffff CCSR 1M
fdc7eb90 PG	21	* 0xe200_0000 0xe27f_ffff PCI1 IO 8M
fdc7eb90 PG	22	* 0xe280_0000 0xe2ff_ffff PCIe IO 8M
3fd673cf	23	* 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
e2b159d0 KG	24	* 0xf000_0000 0xf7ff_ffff SDRAM 128M
e2b159d0 KG	25	* 0xf8b0_0000 0xf80f_ffff EEPROM 1M
e2b159d0 KG	26	* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
e2b159d0 KG	27	*
f0aec4ea PG	28	* If swapped CS0/CS6 via JP12+SW2.8:
	29	* 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
	30	* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
	31	*
e2b159d0	32	* Notes:
53677ef1	33	* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
e2b159d0 KG	34	* If flash is 8M at default position (last 8M), no LAW needed.
	35	*/
	36
	37	struct law_entry law_table[] = {
f0aec4ea PG	38	#ifdef CONFIG_SYS_ALT_BOOT
	39	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
	40	#else
3fd673cf	41	SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
f0aec4ea	42	#endif
e2b159d0	43	#ifndef CONFIG_SPD_EEPROM
6d0f6bcf	44	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
fdc7eb90	45	#endif
7e44f2b7	46	#ifdef CONFIG_SYS_LBC_SDRAM_BASE
e2b159d0	47	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
6d0f6bcf	48	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
7e44f2b7 PG	49	#else
	50	/* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
	51	SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
	52	#endif
e2b159d0 KG	53	};
	54
	55	int num_law_entries = ARRAY_SIZE(law_table);