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11c45ebd JH |
1 | /* |
2 | * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> | |
3 | * Copyright 2007 Embedded Specialties, Inc. | |
4 | * | |
5 | * Copyright 2004, 2007 Freescale Semiconductor. | |
6 | * | |
7 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #include <pci.h> | |
30 | #include <asm/processor.h> | |
31 | #include <asm/immap_85xx.h> | |
32 | #include <asm/immap_fsl_pci.h> | |
33b9079b | 33 | #include <asm/fsl_ddr_sdram.h> |
a30a549a | 34 | #include <spd_sdram.h> |
11c45ebd JH |
35 | #include <miiphy.h> |
36 | #include <libfdt.h> | |
37 | #include <fdt_support.h> | |
38 | ||
39 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
40 | extern void ddr_enable_ecc(unsigned int dram_size); | |
41 | #endif | |
42 | ||
43 | DECLARE_GLOBAL_DATA_PTR; | |
44 | ||
11c45ebd JH |
45 | void local_bus_init(void); |
46 | void sdram_init(void); | |
47 | long int fixed_sdram (void); | |
48 | ||
49 | int board_early_init_f (void) | |
50 | { | |
51 | return 0; | |
52 | } | |
53 | ||
54 | int checkboard (void) | |
55 | { | |
6d0f6bcf JCPV |
56 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
57 | volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); | |
58 | volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; | |
11c45ebd JH |
59 | |
60 | printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", | |
347b7938 | 61 | (*rev) >> 4); |
11c45ebd JH |
62 | |
63 | /* | |
64 | * Initialize local bus. | |
65 | */ | |
66 | local_bus_init (); | |
67 | ||
68 | /* | |
69 | * Fix CPU2 errata: A core hang possible while executing a | |
70 | * msync instruction and a snoopable transaction from an I/O | |
71 | * master tagged to make quick forward progress is present. | |
72 | */ | |
73 | ecm->eebpcr |= (1 << 16); | |
74 | ||
75 | /* | |
76 | * Hack TSEC 3 and 4 IO voltages. | |
77 | */ | |
78 | gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ | |
79 | ||
80 | ecm->eedr = 0xffffffff; /* clear ecm errors */ | |
81 | ecm->eeer = 0xffffffff; /* enable ecm errors */ | |
82 | return 0; | |
83 | } | |
84 | ||
9973e3c6 | 85 | phys_size_t |
11c45ebd JH |
86 | initdram(int board_type) |
87 | { | |
88 | long dram_size = 0; | |
89 | ||
90 | puts("Initializing\n"); | |
91 | ||
92 | #if defined(CONFIG_DDR_DLL) | |
93 | { | |
94 | /* | |
95 | * Work around to stabilize DDR DLL MSYNC_IN. | |
96 | * Errata DDR9 seems to have been fixed. | |
97 | * This is now the workaround for Errata DDR11: | |
98 | * Override DLL = 1, Course Adj = 1, Tap Select = 0 | |
99 | */ | |
100 | ||
6d0f6bcf | 101 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
11c45ebd JH |
102 | |
103 | gur->ddrdllcr = 0x81000000; | |
104 | asm("sync;isync;msync"); | |
105 | udelay(200); | |
106 | } | |
107 | #endif | |
108 | ||
109 | #if defined(CONFIG_SPD_EEPROM) | |
33b9079b KG |
110 | dram_size = fsl_ddr_sdram(); |
111 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); | |
112 | dram_size *= 0x100000; | |
11c45ebd JH |
113 | #else |
114 | dram_size = fixed_sdram (); | |
115 | #endif | |
116 | ||
117 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
118 | /* | |
119 | * Initialize and enable DDR ECC. | |
120 | */ | |
121 | ddr_enable_ecc(dram_size); | |
122 | #endif | |
123 | /* | |
124 | * SDRAM Initialization | |
125 | */ | |
126 | sdram_init(); | |
127 | ||
128 | puts(" DDR: "); | |
129 | return dram_size; | |
130 | } | |
131 | ||
132 | /* | |
133 | * Initialize Local Bus | |
134 | */ | |
135 | void | |
136 | local_bus_init(void) | |
137 | { | |
6d0f6bcf JCPV |
138 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
139 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); | |
11c45ebd JH |
140 | |
141 | uint clkdiv; | |
142 | uint lbc_hz; | |
143 | sys_info_t sysinfo; | |
144 | ||
145 | get_sys_info(&sysinfo); | |
146 | clkdiv = (lbc->lcrr & 0x0f) * 2; | |
147 | lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; | |
148 | ||
149 | gur->lbiuiplldcr1 = 0x00078080; | |
150 | if (clkdiv == 16) { | |
151 | gur->lbiuiplldcr0 = 0x7c0f1bf0; | |
152 | } else if (clkdiv == 8) { | |
153 | gur->lbiuiplldcr0 = 0x6c0f1bf0; | |
154 | } else if (clkdiv == 4) { | |
155 | gur->lbiuiplldcr0 = 0x5c0f1bf0; | |
156 | } | |
157 | ||
158 | lbc->lcrr |= 0x00030000; | |
159 | ||
160 | asm("sync;isync;msync"); | |
161 | ||
162 | lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ | |
163 | lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ | |
164 | } | |
165 | ||
166 | /* | |
167 | * Initialize SDRAM memory on the Local Bus. | |
168 | */ | |
169 | void | |
170 | sdram_init(void) | |
171 | { | |
6d0f6bcf | 172 | #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) |
11c45ebd JH |
173 | |
174 | uint idx; | |
6d0f6bcf JCPV |
175 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
176 | uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; | |
11c45ebd JH |
177 | uint lsdmr_common; |
178 | ||
179 | puts(" SDRAM: "); | |
180 | ||
6d0f6bcf | 181 | print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
11c45ebd JH |
182 | |
183 | /* | |
184 | * Setup SDRAM Base and Option Registers | |
185 | */ | |
6d0f6bcf | 186 | lbc->or3 = CONFIG_SYS_OR3_PRELIM; |
11c45ebd JH |
187 | asm("msync"); |
188 | ||
6d0f6bcf | 189 | lbc->br3 = CONFIG_SYS_BR3_PRELIM; |
11c45ebd JH |
190 | asm("msync"); |
191 | ||
6d0f6bcf | 192 | lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
11c45ebd JH |
193 | asm("msync"); |
194 | ||
195 | ||
6d0f6bcf JCPV |
196 | lbc->lsrt = CONFIG_SYS_LBC_LSRT; |
197 | lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; | |
11c45ebd JH |
198 | asm("msync"); |
199 | ||
200 | /* | |
201 | * MPC8548 uses "new" 15-16 style addressing. | |
202 | */ | |
6d0f6bcf JCPV |
203 | lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; |
204 | lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; | |
11c45ebd JH |
205 | |
206 | /* | |
207 | * Issue PRECHARGE ALL command. | |
208 | */ | |
6d0f6bcf | 209 | lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; |
11c45ebd JH |
210 | asm("sync;msync"); |
211 | *sdram_addr = 0xff; | |
212 | ppcDcbf((unsigned long) sdram_addr); | |
213 | udelay(100); | |
214 | ||
215 | /* | |
216 | * Issue 8 AUTO REFRESH commands. | |
217 | */ | |
218 | for (idx = 0; idx < 8; idx++) { | |
6d0f6bcf | 219 | lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; |
11c45ebd JH |
220 | asm("sync;msync"); |
221 | *sdram_addr = 0xff; | |
222 | ppcDcbf((unsigned long) sdram_addr); | |
223 | udelay(100); | |
224 | } | |
225 | ||
226 | /* | |
227 | * Issue 8 MODE-set command. | |
228 | */ | |
6d0f6bcf | 229 | lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; |
11c45ebd JH |
230 | asm("sync;msync"); |
231 | *sdram_addr = 0xff; | |
232 | ppcDcbf((unsigned long) sdram_addr); | |
233 | udelay(100); | |
234 | ||
235 | /* | |
236 | * Issue NORMAL OP command. | |
237 | */ | |
6d0f6bcf | 238 | lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; |
11c45ebd JH |
239 | asm("sync;msync"); |
240 | *sdram_addr = 0xff; | |
241 | ppcDcbf((unsigned long) sdram_addr); | |
242 | udelay(200); /* Overkill. Must wait > 200 bus cycles */ | |
243 | ||
244 | #endif /* enable SDRAM init */ | |
245 | } | |
246 | ||
6d0f6bcf | 247 | #if defined(CONFIG_SYS_DRAM_TEST) |
11c45ebd JH |
248 | int |
249 | testdram(void) | |
250 | { | |
6d0f6bcf JCPV |
251 | uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; |
252 | uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; | |
11c45ebd JH |
253 | uint *p; |
254 | ||
255 | printf("Testing DRAM from 0x%08x to 0x%08x\n", | |
6d0f6bcf JCPV |
256 | CONFIG_SYS_MEMTEST_START, |
257 | CONFIG_SYS_MEMTEST_END); | |
11c45ebd JH |
258 | |
259 | printf("DRAM test phase 1:\n"); | |
260 | for (p = pstart; p < pend; p++) | |
261 | *p = 0xaaaaaaaa; | |
262 | ||
263 | for (p = pstart; p < pend; p++) { | |
264 | if (*p != 0xaaaaaaaa) { | |
265 | printf ("DRAM test fails at: %08x\n", (uint) p); | |
266 | return 1; | |
267 | } | |
268 | } | |
269 | ||
270 | printf("DRAM test phase 2:\n"); | |
271 | for (p = pstart; p < pend; p++) | |
272 | *p = 0x55555555; | |
273 | ||
274 | for (p = pstart; p < pend; p++) { | |
275 | if (*p != 0x55555555) { | |
276 | printf ("DRAM test fails at: %08x\n", (uint) p); | |
277 | return 1; | |
278 | } | |
279 | } | |
280 | ||
281 | printf("DRAM test passed.\n"); | |
282 | return 0; | |
283 | } | |
284 | #endif | |
285 | ||
286 | #if !defined(CONFIG_SPD_EEPROM) | |
287 | /************************************************************************* | |
288 | * fixed_sdram init -- doesn't use serial presence detect. | |
289 | * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. | |
290 | ************************************************************************/ | |
291 | long int fixed_sdram (void) | |
292 | { | |
6d0f6bcf | 293 | #define CONFIG_SYS_DDR_CONTROL 0xc300c000 |
11c45ebd | 294 | |
6d0f6bcf | 295 | volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); |
11c45ebd JH |
296 | |
297 | ddr->cs0_bnds = 0x0000007f; | |
298 | ddr->cs1_bnds = 0x008000ff; | |
299 | ddr->cs2_bnds = 0x00000000; | |
300 | ddr->cs3_bnds = 0x00000000; | |
301 | ddr->cs0_config = 0x80010101; | |
302 | ddr->cs1_config = 0x80010101; | |
303 | ddr->cs2_config = 0x00000000; | |
304 | ddr->cs3_config = 0x00000000; | |
45239cf4 | 305 | ddr->timing_cfg_3 = 0x00000000; |
11c45ebd JH |
306 | ddr->timing_cfg_0 = 0x00220802; |
307 | ddr->timing_cfg_1 = 0x38377322; | |
308 | ddr->timing_cfg_2 = 0x0fa044C7; | |
309 | ddr->sdram_cfg = 0x4300C000; | |
310 | ddr->sdram_cfg_2 = 0x24401000; | |
311 | ddr->sdram_mode = 0x23C00542; | |
312 | ddr->sdram_mode_2 = 0x00000000; | |
313 | ddr->sdram_interval = 0x05080100; | |
314 | ddr->sdram_md_cntl = 0x00000000; | |
315 | ddr->sdram_data_init = 0x00000000; | |
53677ef1 | 316 | ddr->sdram_clk_cntl = 0x03800000; |
11c45ebd JH |
317 | asm("sync;isync;msync"); |
318 | udelay(500); | |
319 | ||
320 | #if defined (CONFIG_DDR_ECC) | |
321 | /* Enable ECC checking */ | |
6d0f6bcf | 322 | ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
11c45ebd | 323 | #else |
6d0f6bcf | 324 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
11c45ebd JH |
325 | #endif |
326 | ||
6d0f6bcf | 327 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
11c45ebd JH |
328 | } |
329 | #endif | |
330 | ||
331 | #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) | |
332 | /* For some reason the Tundra PCI bridge shows up on itself as a | |
333 | * different device. Work around that by refusing to configure it. | |
334 | */ | |
335 | void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } | |
336 | ||
337 | static struct pci_config_table pci_sbc8548_config_table[] = { | |
338 | {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, | |
339 | {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, | |
340 | {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, | |
341 | mpc85xx_config_via_usbide, {0,0,0}}, | |
342 | {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, | |
343 | mpc85xx_config_via_usb, {0,0,0}}, | |
344 | {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, | |
345 | mpc85xx_config_via_usb2, {0,0,0}}, | |
346 | {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, | |
347 | mpc85xx_config_via_power, {0,0,0}}, | |
348 | {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, | |
349 | mpc85xx_config_via_ac97, {0,0,0}}, | |
350 | {}, | |
351 | }; | |
352 | ||
353 | static struct pci_controller pci1_hose = { | |
354 | config_table: pci_sbc8548_config_table}; | |
355 | #endif /* CONFIG_PCI */ | |
356 | ||
357 | #ifdef CONFIG_PCI2 | |
358 | static struct pci_controller pci2_hose; | |
359 | #endif /* CONFIG_PCI2 */ | |
360 | ||
361 | #ifdef CONFIG_PCIE1 | |
362 | static struct pci_controller pcie1_hose; | |
363 | #endif /* CONFIG_PCIE1 */ | |
364 | ||
365 | int first_free_busno=0; | |
366 | ||
2dba0dea KG |
367 | extern int fsl_pci_setup_inbound_windows(struct pci_region *r); |
368 | extern void fsl_pci_init(struct pci_controller *hose); | |
369 | ||
11c45ebd JH |
370 | void |
371 | pci_init_board(void) | |
372 | { | |
6d0f6bcf | 373 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
11c45ebd JH |
374 | |
375 | #ifdef CONFIG_PCI1 | |
376 | { | |
6d0f6bcf | 377 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; |
11c45ebd JH |
378 | struct pci_controller *hose = &pci1_hose; |
379 | struct pci_config_table *table; | |
2dba0dea | 380 | struct pci_region *r = hose->regions; |
11c45ebd JH |
381 | |
382 | uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ | |
383 | uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ | |
384 | uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ | |
385 | ||
386 | uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); | |
387 | ||
388 | uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ | |
389 | ||
390 | if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { | |
391 | printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", | |
392 | (pci_32) ? 32 : 64, | |
393 | (pci_speed == 33333000) ? "33" : | |
394 | (pci_speed == 66666000) ? "66" : "unknown", | |
395 | pci_clk_sel ? "sync" : "async", | |
396 | pci_agent ? "agent" : "host", | |
397 | pci_arb ? "arbiter" : "external-arbiter" | |
398 | ); | |
399 | ||
400 | ||
401 | /* inbound */ | |
2dba0dea | 402 | r += fsl_pci_setup_inbound_windows(r); |
11c45ebd JH |
403 | |
404 | /* outbound memory */ | |
2dba0dea | 405 | pci_set_region(r++, |
6d0f6bcf JCPV |
406 | CONFIG_SYS_PCI1_MEM_BASE, |
407 | CONFIG_SYS_PCI1_MEM_PHYS, | |
408 | CONFIG_SYS_PCI1_MEM_SIZE, | |
11c45ebd JH |
409 | PCI_REGION_MEM); |
410 | ||
411 | /* outbound io */ | |
2dba0dea | 412 | pci_set_region(r++, |
6d0f6bcf JCPV |
413 | CONFIG_SYS_PCI1_IO_BASE, |
414 | CONFIG_SYS_PCI1_IO_PHYS, | |
415 | CONFIG_SYS_PCI1_IO_SIZE, | |
11c45ebd | 416 | PCI_REGION_IO); |
2dba0dea | 417 | hose->region_count = r - hose->regions; |
11c45ebd JH |
418 | |
419 | /* relocate config table pointers */ | |
420 | hose->config_table = \ | |
421 | (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); | |
422 | for (table = hose->config_table; table && table->vendor; table++) | |
423 | table->config_device += gd->reloc_off; | |
424 | ||
425 | hose->first_busno=first_free_busno; | |
426 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
427 | ||
428 | fsl_pci_init(hose); | |
429 | first_free_busno=hose->last_busno+1; | |
430 | printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); | |
431 | #ifdef CONFIG_PCIX_CHECK | |
432 | if (!(gur->pordevsr & PORDEVSR_PCI)) { | |
433 | /* PCI-X init */ | |
434 | if (CONFIG_SYS_CLK_FREQ < 66000000) | |
435 | printf("PCI-X will only work at 66 MHz\n"); | |
436 | ||
437 | reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | |
438 | | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; | |
439 | pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); | |
440 | } | |
441 | #endif | |
442 | } else { | |
443 | printf (" PCI: disabled\n"); | |
444 | } | |
445 | } | |
446 | #else | |
447 | gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ | |
448 | #endif | |
449 | ||
450 | #ifdef CONFIG_PCI2 | |
451 | { | |
452 | uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ | |
453 | uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ | |
454 | if (pci_dual) { | |
455 | printf (" PCI2: 32 bit, 66 MHz, %s\n", | |
456 | pci2_clk_sel ? "sync" : "async"); | |
457 | } else { | |
458 | printf (" PCI2: disabled\n"); | |
459 | } | |
460 | } | |
461 | #else | |
462 | gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ | |
463 | #endif /* CONFIG_PCI2 */ | |
464 | ||
465 | #ifdef CONFIG_PCIE1 | |
466 | { | |
6d0f6bcf | 467 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; |
11c45ebd JH |
468 | struct pci_controller *hose = &pcie1_hose; |
469 | int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); | |
2dba0dea | 470 | struct pci_region *r = hose->regions; |
11c45ebd JH |
471 | |
472 | int pcie_configured = io_sel >= 1; | |
473 | ||
474 | if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ | |
475 | printf ("\n PCIE connected to slot as %s (base address %x)", | |
476 | pcie_ep ? "End Point" : "Root Complex", | |
477 | (uint)pci); | |
478 | ||
479 | if (pci->pme_msg_det) { | |
480 | pci->pme_msg_det = 0xffffffff; | |
481 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
482 | } | |
483 | printf ("\n"); | |
484 | ||
485 | /* inbound */ | |
2dba0dea | 486 | pci_set_region(r++, |
6d0f6bcf JCPV |
487 | CONFIG_SYS_PCI_MEMORY_BUS, |
488 | CONFIG_SYS_PCI_MEMORY_PHYS, | |
489 | CONFIG_SYS_PCI_MEMORY_SIZE, | |
11c45ebd JH |
490 | PCI_REGION_MEM | PCI_REGION_MEMORY); |
491 | ||
492 | /* outbound memory */ | |
2dba0dea | 493 | pci_set_region(r++, |
6d0f6bcf JCPV |
494 | CONFIG_SYS_PCIE1_MEM_BASE, |
495 | CONFIG_SYS_PCIE1_MEM_PHYS, | |
496 | CONFIG_SYS_PCIE1_MEM_SIZE, | |
11c45ebd JH |
497 | PCI_REGION_MEM); |
498 | ||
499 | /* outbound io */ | |
2dba0dea | 500 | pci_set_region(r++, |
6d0f6bcf JCPV |
501 | CONFIG_SYS_PCIE1_IO_BASE, |
502 | CONFIG_SYS_PCIE1_IO_PHYS, | |
503 | CONFIG_SYS_PCIE1_IO_SIZE, | |
11c45ebd JH |
504 | PCI_REGION_IO); |
505 | ||
2dba0dea | 506 | hose->region_count = r - hose->regions; |
11c45ebd JH |
507 | |
508 | hose->first_busno=first_free_busno; | |
509 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
510 | ||
511 | fsl_pci_init(hose); | |
512 | printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); | |
513 | ||
514 | first_free_busno=hose->last_busno+1; | |
515 | ||
516 | } else { | |
517 | printf (" PCIE: disabled\n"); | |
518 | } | |
519 | } | |
520 | #else | |
521 | gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ | |
522 | #endif | |
523 | ||
524 | } | |
525 | ||
526 | int last_stage_init(void) | |
527 | { | |
528 | return 0; | |
529 | } | |
530 | ||
531 | #if defined(CONFIG_OF_BOARD_SETUP) | |
2dba0dea | 532 | extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, |
3cbd8231 | 533 | struct pci_controller *hose); |
11c45ebd | 534 | |
2dba0dea KG |
535 | void ft_board_setup(void *blob, bd_t *bd) |
536 | { | |
537 | ft_cpu_setup(blob, bd); | |
11c45ebd | 538 | #ifdef CONFIG_PCI1 |
2dba0dea | 539 | ft_fsl_pci_setup(blob, "pci0", &pci1_hose); |
11c45ebd JH |
540 | #endif |
541 | #ifdef CONFIG_PCIE1 | |
2dba0dea | 542 | ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); |
11c45ebd JH |
543 | #endif |
544 | } | |
545 | #endif |