[people/ms/u-boot.git] / board / sbc8641d / sbc8641d.c

/*
 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
 * Copyright 2007 Embedded Specialties, Inc.
 * Joe Hamman joe.hamman@embeddedspecialties.com
 *
 * Copyright 2004 Freescale Semiconductor.
 * Jeff Brown
 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <libfdt.h>
#include <fdt_support.h>

DECLARE_GLOBAL_DATA_PTR;

long int fixed_sdram (void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	puts ("Board: Wind River SBC8641D\n");

	return 0;
}

int dram_init(void)
{
	long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram ();
#endif

	debug ("    DDR: ");
	gd->ram_size = dram_size;

	return 0;
}

#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	puts ("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	puts ("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	puts ("SDRAM test passed.\n");
	return 0;
}
#endif

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
long int fixed_sdram (void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile struct ccsr_ddr *ddr = &immap->im_ddr1;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;

	asm ("sync;isync");

	udelay (500);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
	asm ("sync; isync");

	udelay (500);
	ddr = &immap->im_ddr2;

	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
	ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;

	asm ("sync;isync");

	udelay (500);

	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
	asm ("sync; isync");

	udelay (500);
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif				/* !defined(CONFIG_SPD_EEPROM) */

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

void pci_init_board(void)
{
	fsl_pcie_init_board(0);
}
#endif /* CONFIG_PCI */


#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

	return 0;
}
#endif

void sbc8641d_reset_board (void)
{
	puts ("Resetting board....\n");
}

/*
 * get_board_sys_clk
 *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
 */

unsigned long get_board_sys_clk (ulong dummy)
{
	int i;
	ulong val = 0;

	i = 5;
	i &= 0x07;

	switch (i) {
	case 0:
		val = 33000000;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66000000;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 134000000;
		break;
	case 7:
		val = 166000000;
		break;
	}

	return val;
}

void board_reset(void)
{
#ifdef CONFIG_SYS_RESET_ADDRESS
	ulong addr = CONFIG_SYS_RESET_ADDRESS;

	/* flush and disable I/D cache */
	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
	__asm__ __volatile__ ("ori	4, 3, 0xc00"	::: "r4");
	__asm__ __volatile__ ("andc	5, 3, 5"	::: "r5");
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("mtspr	1008, 4");
	__asm__ __volatile__ ("isync");
	__asm__ __volatile__ ("sync");
	__asm__ __volatile__ ("mtspr	1008, 5");
	__asm__ __volatile__ ("isync");
	__asm__ __volatile__ ("sync");

	/*
	 * SRR0 has system reset vector, SRR1 has default MSR value
	 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
	 */
	__asm__ __volatile__ ("mtspr	26, %0"		:: "r" (addr));
	__asm__ __volatile__ ("li	4, (1 << 6)"	::: "r4");
	__asm__ __volatile__ ("mtspr	27, 4");
	__asm__ __volatile__ ("rfi");
#endif
}
Commit	Line	Data
8ac27327 JH	1	/*
	2	* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
	3	* Copyright 2007 Embedded Specialties, Inc.
	4	* Joe Hamman joe.hamman@embeddedspecialties.com
	5	*
	6	* Copyright 2004 Freescale Semiconductor.
	7	* Jeff Brown
	8	* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
	9	*
	10	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	11	*
3765b3e7	12	* SPDX-License-Identifier: GPL-2.0+
8ac27327 JH	13	*/
	14
	15	#include <common.h>
	16	#include <command.h>
	17	#include <pci.h>
	18	#include <asm/processor.h>
	19	#include <asm/immap_86xx.h>
c8514622	20	#include <asm/fsl_pci.h>
5614e71b	21	#include <fsl_ddr_sdram.h>
5d27e02c	22	#include <asm/fsl_serdes.h>
13f5433f JL	23	#include <libfdt.h>
13f5433f JL	24	#include <fdt_support.h>
8ac27327	25
088454cd SG	26	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	27
8ac27327 JH	28	long int fixed_sdram (void);
	29
	30	int board_early_init_f (void)
	31	{
	32	return 0;
	33	}
	34
	35	int checkboard (void)
	36	{
	37	puts ("Board: Wind River SBC8641D\n");
	38
8ac27327 JH	39	return 0;
	40	}
	41
f1683aa7	42	int dram_init(void)
8ac27327 JH	43	{
	44	long dram_size = 0;
	45
	46	#if defined(CONFIG_SPD_EEPROM)
9bd4e591	47	dram_size = fsl_ddr_sdram();
8ac27327 JH	48	#else
	49	dram_size = fixed_sdram ();
	50	#endif
	51
21cd5815	52	debug (" DDR: ");
088454cd SG	53	gd->ram_size = dram_size;
	54
	55	return 0;
8ac27327 JH	56	}
8ac27327 JH	57
6d0f6bcf	58	#if defined(CONFIG_SYS_DRAM_TEST)
8ac27327 JH	59	int testdram (void)
8ac27327 JH	60	{
6d0f6bcf JCPV	61	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	62	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
8ac27327 JH	63	uint *p;
	64
	65	puts ("SDRAM test phase 1:\n");
	66	for (p = pstart; p < pend; p++)
	67	*p = 0xaaaaaaaa;
	68
	69	for (p = pstart; p < pend; p++) {
	70	if (*p != 0xaaaaaaaa) {
	71	printf ("SDRAM test fails at: %08x\n", (uint) p);
	72	return 1;
	73	}
	74	}
	75
	76	puts ("SDRAM test phase 2:\n");
	77	for (p = pstart; p < pend; p++)
	78	*p = 0x55555555;
	79
	80	for (p = pstart; p < pend; p++) {
	81	if (*p != 0x55555555) {
	82	printf ("SDRAM test fails at: %08x\n", (uint) p);
	83	return 1;
	84	}
	85	}
	86
	87	puts ("SDRAM test passed.\n");
	88	return 0;
	89	}
	90	#endif
	91
	92	#if !defined(CONFIG_SPD_EEPROM)
	93	/*
	94	* Fixed sdram init -- doesn't use serial presence detect.
	95	*/
	96	long int fixed_sdram (void)
	97	{
6d0f6bcf JCPV	98	#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf JCPV	99	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
9a17eb5b	100	volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
8ac27327	101
6d0f6bcf JCPV	102	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	103	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
	104	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
	105	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
	106	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	107	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
	108	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
	109	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
	110	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	111	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	112	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	113	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
e7ee23ec	114	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
6d0f6bcf	115	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
e7ee23ec	116	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
6d0f6bcf	117	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
9a17eb5b	118	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
6d0f6bcf JCPV	119	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	120	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	121	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
8ac27327 JH	122
	123	asm ("sync;isync");
	124
	125	udelay (500);
	126
e7ee23ec	127	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
8ac27327 JH	128	asm ("sync; isync");
	129
	130	udelay (500);
	131	ddr = &immap->im_ddr2;
	132
6d0f6bcf JCPV	133	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
	134	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
	135	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
	136	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
	137	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
	138	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
	139	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
	140	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
	141	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
	142	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
	143	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
	144	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
e7ee23ec	145	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
6d0f6bcf	146	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
e7ee23ec	147	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
6d0f6bcf	148	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
9a17eb5b	149	ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
6d0f6bcf JCPV	150	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
	151	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
	152	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
8ac27327 JH	153
	154	asm ("sync;isync");
	155
	156	udelay (500);
	157
e7ee23ec	158	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
8ac27327 JH	159	asm ("sync; isync");
	160
	161	udelay (500);
	162	#endif
6d0f6bcf	163	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
8ac27327 JH	164	}
	165	#endif /* !defined(CONFIG_SPD_EEPROM) */
	166
	167	#if defined(CONFIG_PCI)
	168	/*
	169	* Initialize PCI Devices, report devices found.
	170	*/
	171
cca34967	172	void pci_init_board(void)
8ac27327	173	{
c51136ec	174	fsl_pcie_init_board(0);
8ac27327	175	}
c51136ec	176	#endif /* CONFIG_PCI */
8ac27327	177
13f5433f JL	178
13f5433f JL	179	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	180	int ft_board_setup(void blob, bd_t bd)
8ac27327	181	{
13f5433f	182	ft_cpu_setup(blob, bd);
8ac27327	183
6525d51f	184	FT_FSL_PCI_SETUP;
e895a4b0 SG	185
e895a4b0 SG	186	return 0;
8ac27327 JH	187	}
	188	#endif
	189
	190	void sbc8641d_reset_board (void)
	191	{
	192	puts ("Resetting board....\n");
	193	}
	194
	195	/*
	196	* get_board_sys_clk
	197	* Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
	198	*/
	199
	200	unsigned long get_board_sys_clk (ulong dummy)
	201	{
	202	int i;
	203	ulong val = 0;
	204
	205	i = 5;
	206	i &= 0x07;
	207
	208	switch (i) {
	209	case 0:
	210	val = 33000000;
	211	break;
	212	case 1:
	213	val = 40000000;
	214	break;
	215	case 2:
	216	val = 50000000;
	217	break;
	218	case 3:
	219	val = 66000000;
	220	break;
	221	case 4:
	222	val = 83000000;
	223	break;
	224	case 5:
	225	val = 100000000;
	226	break;
	227	case 6:
	228	val = 134000000;
	229	break;
	230	case 7:
	231	val = 166000000;
	232	break;
	233	}
	234
	235	return val;
	236	}
4ef630df PT	237
	238	void board_reset(void)
	239	{
	240	#ifdef CONFIG_SYS_RESET_ADDRESS
	241	ulong addr = CONFIG_SYS_RESET_ADDRESS;
	242
	243	/* flush and disable I/D cache */
	244	__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
	245	__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
	246	__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
	247	__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
	248	__asm__ __volatile__ ("sync");
	249	__asm__ __volatile__ ("mtspr 1008, 4");
	250	__asm__ __volatile__ ("isync");
	251	__asm__ __volatile__ ("sync");
	252	__asm__ __volatile__ ("mtspr 1008, 5");
	253	__asm__ __volatile__ ("isync");
	254	__asm__ __volatile__ ("sync");
	255
	256	/*
	257	* SRR0 has system reset vector, SRR1 has default MSR value
	258	* rfi restores MSR from SRR1 and sets the PC to the SRR0 value
	259	*/
	260	__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
	261	__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
	262	__asm__ __volatile__ ("mtspr 27, 4");
	263	__asm__ __volatile__ ("rfi");
	264	#endif
	265	}