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[people/ms/u-boot.git] / board / shannon / flash.c
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1/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Alex Zuepke <azu@sysgo.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26
27ulong myflush(void);
28
29
30#define FLASH_BANK_SIZE 0x400000 /* 4 MB */
31#define MAIN_SECT_SIZE 0x20000 /* 128 KB */
32
33flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
34
35
36#define CMD_READ_ARRAY 0x00F000F0
37#define CMD_UNLOCK1 0x00AA00AA
38#define CMD_UNLOCK2 0x00550055
39#define CMD_ERASE_SETUP 0x00800080
40#define CMD_ERASE_CONFIRM 0x00300030
41#define CMD_PROGRAM 0x00A000A0
42#define CMD_UNLOCK_BYPASS 0x00200020
43
44#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
45#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
46
47#define BIT_ERASE_DONE 0x00800080
48#define BIT_RDY_MASK 0x00800080
49#define BIT_PROGRAM_ERROR 0x00200020
50#define BIT_TIMEOUT 0x80000000 /* our flag */
51
52#define READY 1
53#define ERR 2
54#define TMO 4
55
56/*-----------------------------------------------------------------------
57 */
58
59ulong flash_init(void)
60{
61 int i, j;
62 ulong size = 0;
63
64 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
65 {
66 ulong flashbase = 0;
67 flash_info[i].flash_id =
68 (AMD_MANUFACT & FLASH_VENDMASK) |
69 (AMD_ID_LV160B & FLASH_TYPEMASK);
70 flash_info[i].size = FLASH_BANK_SIZE;
71 flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
72 memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
73 if (i == 0)
74 flashbase = PHYS_FLASH_1;
75 else
76 panic("configured to many flash banks!\n");
77 for (j = 0; j < flash_info[i].sector_count; j++)
78 {
79
80 if (j <= 3)
81 {
82 /* 1st one is 32 KB */
83 if (j == 0)
84 {
85 flash_info[i].start[j] = flashbase + 0;
86 }
87
88 /* 2nd and 3rd are both 16 KB */
89 if ((j == 1) || (j == 2))
90 {
91 flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000;
92 }
93
94 /* 4th 64 KB */
95 if (j == 3)
96 {
97 flash_info[i].start[j] = flashbase + 0x10000;
98 }
99 }
100 else
101 {
102 flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE;
103 }
104 }
105 size += flash_info[i].size;
106 }
107
108 /*
109 * Protect monitor and environment sectors
110 * Inferno is complicated, it's hardware locked
111 */
112#ifdef CONFIG_INFERNO
113 /* first one, 0x00000 to 0x07fff */
114 flash_protect(FLAG_PROTECT_SET,
115 CFG_FLASH_BASE + 0x00000,
116 CFG_FLASH_BASE + 0x08000 - 1,
117 &flash_info[0]);
118
119 /* third to 10th, 0x0c000 - 0xdffff */
120 flash_protect(FLAG_PROTECT_SET,
121 CFG_FLASH_BASE + 0x0c000,
122 CFG_FLASH_BASE + 0xe0000 - 1,
123 &flash_info[0]);
124#else
125 flash_protect(FLAG_PROTECT_SET,
126 CFG_FLASH_BASE,
3b57fe0a 127 CFG_FLASH_BASE + monitor_flash_len - 1,
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128 &flash_info[0]);
129
130 flash_protect(FLAG_PROTECT_SET,
131 CFG_ENV_ADDR,
132 CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
133 &flash_info[0]);
134#endif
135 return size;
136}
137
138/*-----------------------------------------------------------------------
139 */
140void flash_print_info (flash_info_t *info)
141{
142 int i;
143
144 switch (info->flash_id & FLASH_VENDMASK)
145 {
146 case (AMD_MANUFACT & FLASH_VENDMASK):
147 printf("AMD: ");
148 break;
149 default:
150 printf("Unknown Vendor ");
151 break;
152 }
153
154 switch (info->flash_id & FLASH_TYPEMASK)
155 {
156 case (AMD_ID_LV160B & FLASH_TYPEMASK):
157 printf("2x Amd29F160BB (16Mbit)\n");
158 break;
159 default:
160 printf("Unknown Chip Type\n");
161 goto Done;
162 break;
163 }
164
165 printf(" Size: %ld MB in %d Sectors\n",
166 info->size >> 20, info->sector_count);
167
168 printf(" Sector Start Addresses:");
169 for (i = 0; i < info->sector_count; i++)
170 {
171 if ((i % 5) == 0)
172 {
173 printf ("\n ");
174 }
175 printf (" %08lX%s", info->start[i],
176 info->protect[i] ? " (RO)" : " ");
177 }
178 printf ("\n");
179
180Done:
181}
182
183/*-----------------------------------------------------------------------
184 */
185
186int flash_erase (flash_info_t *info, int s_first, int s_last)
187{
188 ulong result;
189 int iflag, cflag, prot, sect;
190 int rc = ERR_OK;
191 int chip1, chip2;
192
193 /* first look for protection bits */
194
195 if (info->flash_id == FLASH_UNKNOWN)
196 return ERR_UNKNOWN_FLASH_TYPE;
197
198 if ((s_first < 0) || (s_first > s_last)) {
199 return ERR_INVAL;
200 }
201
202 if ((info->flash_id & FLASH_VENDMASK) !=
203 (AMD_MANUFACT & FLASH_VENDMASK)) {
204 return ERR_UNKNOWN_FLASH_VENDOR;
205 }
206
207 prot = 0;
208 for (sect=s_first; sect<=s_last; ++sect) {
209 if (info->protect[sect]) {
210 prot++;
211 }
212 }
213 if (prot)
214 return ERR_PROTECTED;
215
216 /*
217 * Disable interrupts which might cause a timeout
218 * here. Remember that our exception vectors are
219 * at address 0 in the flash, and we don't want a
220 * (ticker) exception to happen while the flash
221 * chip is in programming mode.
222 */
223 cflag = icache_status();
224 icache_disable();
225 iflag = disable_interrupts();
226
227 /* Start erase on unprotected sectors */
228 for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
229 {
230 printf("Erasing sector %2d ... ", sect);
231
232 /* arm simple, non interrupt dependent timer */
233 reset_timer_masked();
234
235 if (info->protect[sect] == 0)
236 { /* not protected */
237 vu_long *addr = (vu_long *)(info->start[sect]);
238
239 MEM_FLASH_ADDR1 = CMD_UNLOCK1;
240 MEM_FLASH_ADDR2 = CMD_UNLOCK2;
241 MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
242
243 MEM_FLASH_ADDR1 = CMD_UNLOCK1;
244 MEM_FLASH_ADDR2 = CMD_UNLOCK2;
245 *addr = CMD_ERASE_CONFIRM;
246
247 /* wait until flash is ready */
248 chip1 = chip2 = 0;
249
250 do
251 {
252 result = *addr;
253
254 /* check timeout */
255 if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
256 {
257 MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
258 chip1 = TMO;
259 break;
260 }
261
262 if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
263 chip1 = READY;
264
265 if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
266 chip1 = ERR;
267
268 if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
269 chip2 = READY;
270
271 if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
272 chip2 = ERR;
273
274 } while (!chip1 || !chip2);
275
276 MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
277
278 if (chip1 == ERR || chip2 == ERR)
279 {
280 rc = ERR_PROG_ERROR;
281 goto outahere;
282 }
283 if (chip1 == TMO)
284 {
285 rc = ERR_TIMOUT;
286 goto outahere;
287 }
288
289 printf("ok.\n");
290 }
291 else /* it was protected */
292 {
293 printf("protected!\n");
294 }
295 }
296
297 if (ctrlc())
298 printf("User Interrupt!\n");
299
300outahere:
301 /* allow flash to settle - wait 10 ms */
302 udelay_masked(10000);
303
304 if (iflag)
305 enable_interrupts();
306
307 if (cflag)
308 icache_enable();
309
310 return rc;
311}
312
313/*-----------------------------------------------------------------------
314 * Copy memory to flash
315 */
316
317volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
318{
319 vu_long *addr = (vu_long *)dest;
320 ulong result;
321 int rc = ERR_OK;
322 int cflag, iflag;
323 int chip1, chip2;
324
325 /*
326 * Check if Flash is (sufficiently) erased
327 */
328 result = *addr;
329 if ((result & data) != data)
8bde7f77 330 return ERR_NOT_ERASED;
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331
332
333 /*
334 * Disable interrupts which might cause a timeout
335 * here. Remember that our exception vectors are
336 * at address 0 in the flash, and we don't want a
337 * (ticker) exception to happen while the flash
338 * chip is in programming mode.
339 */
340 cflag = icache_status();
341 icache_disable();
342 iflag = disable_interrupts();
343
344 MEM_FLASH_ADDR1 = CMD_UNLOCK1;
345 MEM_FLASH_ADDR2 = CMD_UNLOCK2;
346 MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
347 *addr = CMD_PROGRAM;
348 *addr = data;
349
350 /* arm simple, non interrupt dependent timer */
351 reset_timer_masked();
352
353 /* wait until flash is ready */
354 chip1 = chip2 = 0;
355 do
356 {
357 result = *addr;
358
359 /* check timeout */
360 if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
361 {
362 chip1 = ERR | TMO;
363 break;
364 }
365 if (!chip1 && ((result & 0x80) == (data & 0x80)))
366 chip1 = READY;
367
368 if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR))
369 {
370 result = *addr;
371
372 if ((result & 0x80) == (data & 0x80))
373 chip1 = READY;
374 else
375 chip1 = ERR;
376 }
377
378 if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
379 chip2 = READY;
380
381 if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR))
382 {
383 result = *addr;
384
385 if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
386 chip2 = READY;
387 else
388 chip2 = ERR;
389 }
390
391 } while (!chip1 || !chip2);
392
393 *addr = CMD_READ_ARRAY;
394
395 if (chip1 == ERR || chip2 == ERR || *addr != data)
8bde7f77 396 rc = ERR_PROG_ERROR;
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397
398 if (iflag)
399 enable_interrupts();
400
401 if (cflag)
402 icache_enable();
403
404 return rc;
405}
406
407/*-----------------------------------------------------------------------
408 * Copy memory to flash.
409 */
410
411int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
412{
413 ulong cp, wp, data;
414 int l;
415 int i, rc;
416
417 wp = (addr & ~3); /* get lower word aligned address */
418
419 /*
420 * handle unaligned start bytes
421 */
422 if ((l = addr - wp) != 0) {
423 data = 0;
424 for (i=0, cp=wp; i<l; ++i, ++cp) {
425 data = (data >> 8) | (*(uchar *)cp << 24);
426 }
427 for (; i<4 && cnt>0; ++i) {
428 data = (data >> 8) | (*src++ << 24);
429 --cnt;
430 ++cp;
431 }
432 for (; cnt==0 && i<4; ++i, ++cp) {
433 data = (data >> 8) | (*(uchar *)cp << 24);
434 }
435
436 if ((rc = write_word(info, wp, data)) != 0) {
437 return (rc);
438 }
439 wp += 4;
440 }
441
442 /*
443 * handle word aligned part
444 */
445 while (cnt >= 4) {
446 data = *((vu_long*)src);
447 if ((rc = write_word(info, wp, data)) != 0) {
448 return (rc);
449 }
450 src += 4;
451 wp += 4;
452 cnt -= 4;
453 }
454
455 if (cnt == 0) {
456 return ERR_OK;
457 }
458
459 /*
460 * handle unaligned tail bytes
461 */
462 data = 0;
463 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
464 data = (data >> 8) | (*src++ << 24);
465 --cnt;
466 }
467 for (; i<4; ++i, ++cp) {
468 data = (data >> 8) | (*(uchar *)cp << 24);
469 }
470
471 return write_word(info, wp, data);
472}