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* Patches by Robert Schwebel, 26 Jun 2003:
[people/ms/u-boot.git] / board / siemens / pcu_e / pcu_e.c
CommitLineData
f8cac651
WD		 1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc8xx.h>
26#include <commproc.h>
27#include <i2c.h>
28#include <command.h>
29#include <cmd_bsp.h>
30
31/* ------------------------------------------------------------------------- */
32
33static long int dram_size (long int, long int *, long int);
34static void puma_status (void);
35static void puma_set_mode (int mode);
36static int puma_init_done (void);
37static void puma_load (ulong addr, ulong len);
38
39/* ------------------------------------------------------------------------- */
40
41#define _NOT_USED_ 0xFFFFFFFF
42
43/*
44 * 50 MHz SDRAM access using UPM A
45 */
46const uint sdram_table[] =
47{
48 /*
49 * Single Read. (Offset 0 in UPM RAM)
50 */
51 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
52 0x1ffddc47, /* last */
53 /*
54 * SDRAM Initialization (offset 5 in UPM RAM)
55 *
56 * This is no UPM entry point. The following definition uses
57 * the remaining space to establish an initialization
58 * sequence, which is executed by a RUN command.
59 *
60 */
61 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
62 /*
63 * Burst Read. (Offset 8 in UPM RAM)
64 */
65 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
66 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
69
70 /*
71 * Single Write. (Offset 18 in UPM RAM)
72 */
73 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 /*
76 * Burst Write. (Offset 20 in UPM RAM)
77 */
78 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
79 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
80 _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 /*
84 * Refresh (Offset 30 in UPM RAM)
85 */
86 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
87 0xfffffc84, 0xfffffc07, /* last */
88 _NOT_USED_, _NOT_USED_,
89 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 /*
91 * Exception. (Offset 3c in UPM RAM)
92 */
93 0x7ffffc07, /* last */
94 _NOT_USED_, _NOT_USED_, _NOT_USED_,
95};
96
97/* ------------------------------------------------------------------------- */
98
99/*
100 * PUMA access using UPM B
101 */
102const uint puma_table[] =
103{
104 /*
105 * Single Read. (Offset 0 in UPM RAM)
106 */
107 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
108 _NOT_USED_,
109 /*
110 * Precharge and MRS
111 */
112 _NOT_USED_, _NOT_USED_, _NOT_USED_,
113 /*
114 * Burst Read. (Offset 8 in UPM RAM)
115 */
116 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
117 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
118 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
119 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
120 /*
121 * Single Write. (Offset 18 in UPM RAM)
122 */
123 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
124 _NOT_USED_,
125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
126 /*
127 * Burst Write. (Offset 20 in UPM RAM)
128 */
129 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
130 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
131 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
132 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
133 /*
134 * Refresh (Offset 30 in UPM RAM)
135 */
136 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
137 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
138 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
139 /*
140 * Exception. (Offset 3c in UPM RAM)
141 */
142 0x7ffffc07, /* last */
143 _NOT_USED_, _NOT_USED_, _NOT_USED_,
144};
145
146/* ------------------------------------------------------------------------- */
147
148
149/*
150 * Check Board Identity:
151 *
152 */
153
154int checkboard (void)
155{
156 puts ("Board: Siemens PCU E\n");
157 return (0);
158}
159
160/* ------------------------------------------------------------------------- */
161
162long int
163initdram (int board_type)
164{
165 volatile immap_t *immr = (immap_t *)CFG_IMMR;
166 volatile memctl8xx_t *memctl = &immr->im_memctl;
167 long int size_b0, reg;
168 int i;
169
170 /*
171 * Configure UPMA for SDRAM
172 */
173 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
174
175 memctl->memc_mptpr = CFG_MPTPR;
176
177 /* burst length=4, burst type=sequential, CAS latency=2 */
178 memctl->memc_mar = 0x00000088;
179
180 /*
181 * Map controller bank 2 to the SDRAM bank at preliminary address.
182 */
183#if PCU_E_WITH_SWAPPED_CS /* XXX */
184 memctl->memc_or5 = CFG_OR5_PRELIM;
185 memctl->memc_br5 = CFG_BR5_PRELIM;
186#else /* XXX */
187 memctl->memc_or2 = CFG_OR2_PRELIM;
188 memctl->memc_br2 = CFG_BR2_PRELIM;
189#endif /* XXX */
190
191 /* initialize memory address register */
192 memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
193
194 /* mode initialization (offset 5) */
195#if PCU_E_WITH_SWAPPED_CS /* XXX */
196 udelay(200); /* 0x8000A105 */
197 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
198#else /* XXX */
199 udelay(200); /* 0x80004105 */
200 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
201#endif /* XXX */
202
203 /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
204#if PCU_E_WITH_SWAPPED_CS /* XXX */
205 udelay(1); /* 0x8000A830 */
206 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
207#else /* XXX */
208 udelay(1); /* 0x80004830 */
209 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
210#endif /* XXX */
211
212#if PCU_E_WITH_SWAPPED_CS /* XXX */
213 udelay(1); /* 0x8000A106 */
214 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
215#else /* XXX */
216 udelay(1); /* 0x80004106 */
217 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
218#endif /* XXX */
219
220 reg = memctl->memc_mamr;
221 reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */
222 reg |= MAMR_TLFB_4X; /* ... to 4x */
223 reg |= MAMR_PTBE; /* enable refresh */
224 memctl->memc_mamr = reg;
225
226 udelay(200);
227
228 /* Need at least 10 DRAM accesses to stabilize */
229 for (i=0; i<10; ++i) {
230#if PCU_E_WITH_SWAPPED_CS /* XXX */
231 volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
232#else /* XXX */
233 volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
234#endif /* XXX */
235 unsigned long val;
236
237 val = *(addr + i);
238 *(addr + i) = val;
239 }
240
241 /*
242 * Check Bank 0 Memory Size for re-configuration
243 */
244#if PCU_E_WITH_SWAPPED_CS /* XXX */
245 size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
246#else /* XXX */
247 size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
248#endif /* XXX */
249
250 memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
251
252 /*
253 * Final mapping:
254 */
255
256#if PCU_E_WITH_SWAPPED_CS /* XXX */
257 memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
258 memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
259#else /* XXX */
260 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
261 memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
262#endif /* XXX */
263 udelay(1000);
264
265 /*
266 * Configure UPMB for PUMA
267 */
268 upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
269
270 return (size_b0);
271}
272
273/* ------------------------------------------------------------------------- */
274
275/*
276 * Check memory range for valid RAM. A simple memory test determines
277 * the actually available RAM size between addresses `base' and
278 * `base + maxsize'. Some (not all) hardware errors are detected:
279 * - short between address lines
280 * - short between data lines
281 */
282
283static long int dram_size (long int mamr_value, long int *base, long int maxsize)
284{
285 volatile immap_t *immr = (immap_t *)CFG_IMMR;
286 volatile memctl8xx_t *memctl = &immr->im_memctl;
287 volatile long int *addr;
288 ulong cnt, val;
289 ulong save[32]; /* to make test non-destructive */
290 unsigned char i = 0;
291
292 memctl->memc_mamr = mamr_value;
293
294 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
295 addr = base + cnt; /* pointer arith! */
296
297 save[i++] = *addr;
298 *addr = ~cnt;
299 }
300
301 /* write 0 to base address */
302 addr = base;
303 save[i] = *addr;
304 *addr = 0;
305
306 /* check at base address */
307 if ((val = *addr) != 0) {
308 *addr = save[i];
309 return (0);
310 }
311
312 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
313 addr = base + cnt; /* pointer arith! */
314
315 val = *addr;
316 *addr = save[--i];
317
318 if (val != (~cnt)) {
319 return (cnt * sizeof(long));
320 }
321 }
322 return (maxsize);
323}
324
325/* ------------------------------------------------------------------------- */
326
327#if PCU_E_WITH_SWAPPED_CS /* XXX */
328#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
329#else /* XXX */
330#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
331 CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
332#endif /* XXX */
333
334#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
335
336void reset_phy(void)
337{
338 immap_t *immr = (immap_t *)CFG_IMMR;
339 ulong value;
340
341 /* Configure all needed port pins for GPIO */
342#if PCU_E_WITH_SWAPPED_CS /* XXX */
343# if CFG_ETH_MDDIS_VALUE
344 immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
345# else
346 immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
347# endif
348 immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
349 immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
350 immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
351#endif /* XXX */
352 immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
353 immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
354
355 value = immr->im_cpm.cp_pbdat;
356
357 /* Assert Powerdown and Reset signals */
358 value |= CFG_PB_ETH_POWERDOWN;
359 value &= ~(CFG_PB_ETH_RESET);
360
361 /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
362#if !PCU_E_WITH_SWAPPED_CS
363# if CFG_ETH_MDDIS_VALUE
364 value |= CFG_PB_ETH_MDDIS;
365# else
366 value &= ~(CFG_PB_ETH_MDDIS);
367# endif
368#endif
369#if CFG_ETH_CFG1_VALUE
370 value |= CFG_PB_ETH_CFG1;
371#else
372 value &= ~(CFG_PB_ETH_CFG1);
373#endif
374#if CFG_ETH_CFG2_VALUE
375 value |= CFG_PB_ETH_CFG2;
376#else
377 value &= ~(CFG_PB_ETH_CFG2);
378#endif
379#if CFG_ETH_CFG3_VALUE
380 value |= CFG_PB_ETH_CFG3;
381#else
382 value &= ~(CFG_PB_ETH_CFG3);
383#endif
384
385 /* Drive output signals to initial state */
386 immr->im_cpm.cp_pbdat = value;
387 immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
388 udelay (10000);
389
390 /* De-assert Ethernet Powerdown */
391 immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
392 udelay (10000);
393
394 /* de-assert RESET signal of PHY */
395 immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
396 udelay (1000);
397}
398
399/*-----------------------------------------------------------------------
400 * Board Special Commands: access functions for "PUMA" FPGA
401 */
402#if (CONFIG_COMMANDS & CFG_CMD_BSP)
403
404#define PUMA_READ_MODE 0
405#define PUMA_LOAD_MODE 1
406
407int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
408{
409 ulong addr, len;
410
411 switch (argc) {
412 case 2: /* PUMA reset */
413 if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */
414 puma_status ();
415 return 0;
416 }
417 break;
418 case 4: /* PUMA load addr len */
419 if (strcmp(argv[1],"load") != 0)
420 break;
421
422 addr = simple_strtoul(argv[2], NULL, 16);
423 len = simple_strtoul(argv[3], NULL, 16);
424
425 printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
426 addr, len, len);
427 puma_load (addr, len);
428
429 return 0;
430 default:
431 break;
432 }
433 printf ("Usage:\n%s\n", cmdtp->usage);
434 return 1;
435}
436
437#endif /* CFG_CMD_BSP */
438
439/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
440
441static void puma_set_mode (int mode)
442{
443 volatile immap_t *immr = (immap_t *)CFG_IMMR;
444 volatile memctl8xx_t *memctl = &immr->im_memctl;
445
446 /* disable PUMA in memory controller */
447#if PCU_E_WITH_SWAPPED_CS /* XXX */
448 memctl->memc_br3 = 0;
449#else /* XXX */
450 memctl->memc_br4 = 0;
451#endif /* XXX */
452
453 switch (mode) {
454 case PUMA_READ_MODE:
455#if PCU_E_WITH_SWAPPED_CS /* XXX */
456 memctl->memc_or3 = PUMA_CONF_OR_READ;
457 memctl->memc_br3 = PUMA_CONF_BR_READ;
458#else /* XXX */
459 memctl->memc_or4 = PUMA_CONF_OR_READ;
460 memctl->memc_br4 = PUMA_CONF_BR_READ;
461#endif /* XXX */
462 break;
463 case PUMA_LOAD_MODE:
464#if PCU_E_WITH_SWAPPED_CS /* XXX */
465 memctl->memc_or3 = PUMA_CONF_OR_LOAD;
466 memctl->memc_br3 = PUMA_CONF_BR_LOAD;
467#else /* XXX */
468 memctl->memc_or4 = PUMA_CONF_OR_READ;
469 memctl->memc_br4 = PUMA_CONF_BR_READ;
470#endif /* XXX */
471 break;
472 }
473}
474
475/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
476
477#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
478
479static void puma_load (ulong addr, ulong len)
480{
481 volatile immap_t *immr = (immap_t *)CFG_IMMR;
482 volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
483 uchar *data = (uchar *)addr;
484 int i;
485
486 /* align length */
487 if (len & 1)
488 ++len;
489
490 /* Reset FPGA */
491 immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */
492 immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
493 immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
494
495#if PCU_E_WITH_SWAPPED_CS /* XXX */
496 immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
497 immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
498 immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
499 immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */
500#else
501 immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */
502 immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */
503 immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */
504 immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */
505#endif /* XXX */
506 udelay (100);
507
508#if PCU_E_WITH_SWAPPED_CS /* XXX */
509 immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
510#else
511 immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
512#endif /* XXX */
513
514 /* wait until INIT indicates completion of reset */
515 for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
516 udelay (1000);
517 if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
518 break;
519 }
520 if (i == PUMA_INIT_TIMEOUT) {
521 printf ("*** PUMA init timeout ***\n");
522 return;
523 }
524
525 puma_set_mode (PUMA_LOAD_MODE);
526
527 while (len--)
528 *fpga_addr = *data++;
529
530 puma_set_mode (PUMA_READ_MODE);
531
532 puma_status ();
533}
534
535/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
536
537static void puma_status (void)
538{
539 /* Check state */
540 printf ("PUMA initialization is %scomplete\n",
541 puma_init_done() ? "" : "NOT ");
542}
543
544/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
545
546static int puma_init_done (void)
547{
548 volatile immap_t *immr = (immap_t *)CFG_IMMR;
549
550 /* make sure pin is GPIO input */
551 immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
552 immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
553 immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
554
555 return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
556}
557
558/* ------------------------------------------------------------------------- */
559
560int misc_init_r (void)
561{
562 ulong addr = 0;
563 ulong len = 0;
564 char *s;
565
566 printf ("PUMA: ");
567 if (puma_init_done()) {
568 printf ("initialized\n");
569 return 0;
570 }
571
572 if ((s = getenv("puma_addr")) != NULL)
573 addr = simple_strtoul(s, NULL, 16);
574
575 if ((s = getenv("puma_len")) != NULL)
576 len = simple_strtoul(s, NULL, 16);
577
578 if ((!addr) || (!len)) {
579 printf ("net list undefined\n");
580 return 0;
581 }
582
583 printf ("loading... ");
584
585 puma_load (addr, len);
586 return (0);
587}
588
589/* ------------------------------------------------------------------------- */
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