[people/ms/u-boot.git] / board / solidrun / mx6cuboxi / mx6cuboxi.c

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
 *
 * Based on SPL code from Solidrun tree, which is:
 * Author: Tungyi Lin <tungyilin1127@gmail.com>
 *
 * Derived from EDM_CF_IMX6 code by TechNexion,Inc
 * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <malloc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <spl.h>
#include <usb.h>
#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |		\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

#define ETH_PHY_RESET	IMX_GPIO_NR(4, 15)
#define USB_H1_VBUS	IMX_GPIO_NR(1, 0)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();
	return 0;
}

static iomux_v3_cfg_t const uart1_pads[] = {
	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};

static iomux_v3_cfg_t const usdhc2_pads[] = {
	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};

static iomux_v3_cfg_t const hb_cbi_sense[] = {
	/* These pins are for sensing if it is a CuBox-i or a HummingBoard */
	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
};

static iomux_v3_cfg_t const usb_pads[] = {
	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static void setup_iomux_uart(void)
{
	SETUP_IOMUX_PADS(uart1_pads);
}

static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC2_BASE_ADDR},
};

int board_mmc_getcd(struct mmc *mmc)
{
	return 1; /* uSDHC2 is always present */
}

int board_mmc_init(bd_t *bis)
{
	SETUP_IOMUX_PADS(usdhc2_pads);
	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;

	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}

static iomux_v3_cfg_t const enet_pads[] = {
	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	/* AR8035 reset */
	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
	/* AR8035 interrupt */
	IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* GPIO16 -> AR8035 25MHz */
	IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK	  | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC	  | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
	IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
};

static void setup_iomux_enet(void)
{
	SETUP_IOMUX_PADS(enet_pads);

	gpio_direction_output(ETH_PHY_RESET, 0);
	mdelay(10);
	gpio_set_value(ETH_PHY_RESET, 1);
	udelay(100);
}

int board_phy_config(struct phy_device *phydev)
{
	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
#define ETH_PHY_MASK	((1 << 0x0) | (1 << 0x4))

int board_eth_init(bd_t *bis)
{
	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	struct mii_dev *bus;
	struct phy_device *phydev;

	int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
	if (ret)
		return ret;

	/* set gpr1[ENET_CLK_SEL] */
	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);

	setup_iomux_enet();

	bus = fec_get_miibus(IMX_FEC_BASE, -1);
	if (!bus)
		return -EINVAL;

	phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
	if (!phydev) {
		ret = -EINVAL;
		goto free_bus;
	}

	debug("using phy at address %d\n", phydev->addr);
	ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
	if (ret)
		goto free_phydev;

	return 0;

free_phydev:
	free(phydev);
free_bus:
	free(bus);
	return ret;
}

#ifdef CONFIG_VIDEO_IPUV3
static void do_enable_hdmi(struct display_info_t const *dev)
{
	imx_enable_hdmi_phy();
}

struct display_info_t const displays[] = {
	{
		.bus	= -1,
		.addr	= 0,
		.pixfmt	= IPU_PIX_FMT_RGB24,
		.detect	= detect_hdmi,
		.enable	= do_enable_hdmi,
		.mode	= {
			.name           = "HDMI",
			/* 1024x768@60Hz (VESA)*/
			.refresh        = 60,
			.xres           = 1024,
			.yres           = 768,
			.pixclock       = 15384,
			.left_margin    = 160,
			.right_margin   = 24,
			.upper_margin   = 29,
			.lower_margin   = 3,
			.hsync_len      = 136,
			.vsync_len      = 6,
			.sync           = FB_SYNC_EXT,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	}
};

size_t display_count = ARRAY_SIZE(displays);

static int setup_display(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	int reg;
	int timeout = 100000;

	enable_ipu_clock();
	imx_setup_hdmi();

	/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);

	reg = readl(&ccm->analog_pll_video);
	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
	writel(reg, &ccm->analog_pll_video);

	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);

	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
	writel(reg, &ccm->analog_pll_video);

	while (timeout--)
		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
			break;
	if (timeout < 0) {
		printf("Warning: video pll lock timeout!\n");
		return -ETIMEDOUT;
	}

	reg = readl(&ccm->analog_pll_video);
	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
	writel(reg, &ccm->analog_pll_video);

	/* gate ipu1_di0_clk */
	clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);

	/* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
	reg = readl(&ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
	       (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
	       (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
	writel(reg, &ccm->chsccdr);

	/* enable ipu1_di0_clk */
	setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);

	return 0;
}
#endif /* CONFIG_VIDEO_IPUV3 */

#ifdef CONFIG_USB_EHCI_MX6
static void setup_usb(void)
{
	SETUP_IOMUX_PADS(usb_pads);
}

int board_ehci_hcd_init(int port)
{
	if (port == 1)
		gpio_direction_output(USB_H1_VBUS, 1);

	return 0;
}
#endif

int board_early_init_f(void)
{
	int ret = 0;
	setup_iomux_uart();

#ifdef CONFIG_VIDEO_IPUV3
	ret = setup_display();
#endif

#ifdef CONFIG_USB_EHCI_MX6
	setup_usb();
#endif
	return ret;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	return 0;
}

static bool is_hummingboard(void)
{
	int val1, val2;

	SETUP_IOMUX_PADS(hb_cbi_sense);

	gpio_direction_input(IMX_GPIO_NR(4, 9));
	gpio_direction_input(IMX_GPIO_NR(3, 4));

	val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
	val2 = gpio_get_value(IMX_GPIO_NR(3, 4));

	/*
	 * Machine selection -
	 * Machine        val1, val2
	 * -------------------------
	 * HB rev 3.x     x     0
	 * CBi            0     1
	 * HB             1     1
	 */

	if (val2 == 0)
		return true;
	else if (val1 == 0)
		return false;
	else
		return true;
}

int checkboard(void)
{
	if (is_hummingboard())
		puts("Board: MX6 Hummingboard\n");
	else
		puts("Board: MX6 Cubox-i\n");

	return 0;
}

int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (is_hummingboard())
		setenv("board_name", "HUMMINGBOARD");
	else
		setenv("board_name", "CUBOXI");

	if (is_mx6dq())
		setenv("board_rev", "MX6Q");
	else
		setenv("board_rev", "MX6DL");
#endif

	return 0;
}

#ifdef CONFIG_SPL_BUILD
#include <asm/arch/mx6-ddr.h>
static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
	.dram_sdclk_0 =  0x00020030,
	.dram_sdclk_1 =  0x00020030,
	.dram_cas =  0x00020030,
	.dram_ras =  0x00020030,
	.dram_reset =  0x00020030,
	.dram_sdcke0 =  0x00003000,
	.dram_sdcke1 =  0x00003000,
	.dram_sdba2 =  0x00000000,
	.dram_sdodt0 =  0x00003030,
	.dram_sdodt1 =  0x00003030,
	.dram_sdqs0 =  0x00000030,
	.dram_sdqs1 =  0x00000030,
	.dram_sdqs2 =  0x00000030,
	.dram_sdqs3 =  0x00000030,
	.dram_sdqs4 =  0x00000030,
	.dram_sdqs5 =  0x00000030,
	.dram_sdqs6 =  0x00000030,
	.dram_sdqs7 =  0x00000030,
	.dram_dqm0 =  0x00020030,
	.dram_dqm1 =  0x00020030,
	.dram_dqm2 =  0x00020030,
	.dram_dqm3 =  0x00020030,
	.dram_dqm4 =  0x00020030,
	.dram_dqm5 =  0x00020030,
	.dram_dqm6 =  0x00020030,
	.dram_dqm7 =  0x00020030,
};

static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
	.dram_sdclk_0 = 0x00000028,
	.dram_sdclk_1 = 0x00000028,
	.dram_cas =	0x00000028,
	.dram_ras =	0x00000028,
	.dram_reset =	0x000c0028,
	.dram_sdcke0 =	0x00003000,
	.dram_sdcke1 =	0x00003000,
	.dram_sdba2 =	0x00000000,
	.dram_sdodt0 =	0x00003030,
	.dram_sdodt1 =	0x00003030,
	.dram_sdqs0 =	0x00000028,
	.dram_sdqs1 =	0x00000028,
	.dram_sdqs2 =	0x00000028,
	.dram_sdqs3 =	0x00000028,
	.dram_sdqs4 =	0x00000028,
	.dram_sdqs5 =	0x00000028,
	.dram_sdqs6 =	0x00000028,
	.dram_sdqs7 =	0x00000028,
	.dram_dqm0 =	0x00000028,
	.dram_dqm1 =	0x00000028,
	.dram_dqm2 =	0x00000028,
	.dram_dqm3 =	0x00000028,
	.dram_dqm4 =	0x00000028,
	.dram_dqm5 =	0x00000028,
	.dram_dqm6 =	0x00000028,
	.dram_dqm7 =	0x00000028,
};

static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
	.grp_ddr_type =  0x000C0000,
	.grp_ddrmode_ctl =  0x00020000,
	.grp_ddrpke =  0x00000000,
	.grp_addds =  0x00000030,
	.grp_ctlds =  0x00000030,
	.grp_ddrmode =  0x00020000,
	.grp_b0ds =  0x00000030,
	.grp_b1ds =  0x00000030,
	.grp_b2ds =  0x00000030,
	.grp_b3ds =  0x00000030,
	.grp_b4ds =  0x00000030,
	.grp_b5ds =  0x00000030,
	.grp_b6ds =  0x00000030,
	.grp_b7ds =  0x00000030,
};

static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = 0x00000028,
	.grp_ctlds = 0x00000028,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x00000028,
	.grp_b1ds = 0x00000028,
	.grp_b2ds = 0x00000028,
	.grp_b3ds = 0x00000028,
	.grp_b4ds = 0x00000028,
	.grp_b5ds = 0x00000028,
	.grp_b6ds = 0x00000028,
	.grp_b7ds = 0x00000028,
};

/* microSOM with Dual processor and 1GB memory */
static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
	.p0_mpwldectrl0 =  0x00000000,
	.p0_mpwldectrl1 =  0x00000000,
	.p1_mpwldectrl0 =  0x00000000,
	.p1_mpwldectrl1 =  0x00000000,
	.p0_mpdgctrl0 =    0x0314031c,
	.p0_mpdgctrl1 =    0x023e0304,
	.p1_mpdgctrl0 =    0x03240330,
	.p1_mpdgctrl1 =    0x03180260,
	.p0_mprddlctl =    0x3630323c,
	.p1_mprddlctl =    0x3436283a,
	.p0_mpwrdlctl =    0x36344038,
	.p1_mpwrdlctl =    0x422a423c,
};

/* microSOM with Quad processor and 2GB memory */
static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
	.p0_mpwldectrl0 =  0x00000000,
	.p0_mpwldectrl1 =  0x00000000,
	.p1_mpwldectrl0 =  0x00000000,
	.p1_mpwldectrl1 =  0x00000000,
	.p0_mpdgctrl0 =    0x0314031c,
	.p0_mpdgctrl1 =    0x023e0304,
	.p1_mpdgctrl0 =    0x03240330,
	.p1_mpdgctrl1 =    0x03180260,
	.p0_mprddlctl =    0x3630323c,
	.p1_mprddlctl =    0x3436283a,
	.p0_mpwrdlctl =    0x36344038,
	.p1_mpwrdlctl =    0x422a423c,
};

/* microSOM with Solo processor and 512MB memory */
static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
	.p0_mpwldectrl0 = 0x0045004D,
	.p0_mpwldectrl1 = 0x003A0047,
	.p0_mpdgctrl0 =   0x023C0224,
	.p0_mpdgctrl1 =   0x02000220,
	.p0_mprddlctl =   0x44444846,
	.p0_mpwrdlctl =   0x32343032,
};

/* microSOM with Dual lite processor and 1GB memory */
static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
	.p0_mpwldectrl0 =  0x0045004D,
	.p0_mpwldectrl1 =  0x003A0047,
	.p1_mpwldectrl0 =  0x001F001F,
	.p1_mpwldectrl1 =  0x00210035,
	.p0_mpdgctrl0 =    0x023C0224,
	.p0_mpdgctrl1 =    0x02000220,
	.p1_mpdgctrl0 =    0x02200220,
	.p1_mpdgctrl1 =    0x02040208,
	.p0_mprddlctl =    0x44444846,
	.p1_mprddlctl =    0x4042463C,
	.p0_mpwrdlctl =    0x32343032,
	.p1_mpwrdlctl =    0x36363430,
};

static struct mx6_ddr3_cfg mem_ddr_2g = {
	.mem_speed = 1600,
	.density   = 2,
	.width     = 16,
	.banks     = 8,
	.rowaddr   = 14,
	.coladdr   = 10,
	.pagesz    = 2,
	.trcd      = 1375,
	.trcmin    = 4875,
	.trasmin   = 3500,
	.SRT       = 1,
};

static struct mx6_ddr3_cfg mem_ddr_4g = {
	.mem_speed = 1600,
	.density = 4,
	.width = 16,
	.banks = 8,
	.rowaddr = 15,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC03, &ccm->CCGR1);
	writel(0x0FFFC000, &ccm->CCGR2);
	writel(0x3FF00000, &ccm->CCGR3);
	writel(0x00FFF300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
}

static void gpr_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	writel(0x007F007F, &iomux->gpr[6]);
	writel(0x007F007F, &iomux->gpr[7]);
}

static void spl_dram_init(int width)
{
	struct mx6_ddr_sysinfo sysinfo = {
		/* width of data bus: 0=16, 1=32, 2=64 */
		.dsize = width / 32,
		/* config for full 4GB range so that get_mem_size() works */
		.cs_density = 32,	/* 32Gb per CS */
		.ncs = 1,		/* single chip select */
		.cs1_mirror = 0,
		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
		.walat = 1,	/* Write additional latency */
		.ralat = 5,	/* Read additional latency */
		.mif3_mode = 3,	/* Command prediction working mode */
		.bi_on = 1,	/* Bank interleaving enabled */
		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
		.ddr_type = DDR_TYPE_DDR3,
		.refsel = 1,	/* Refresh cycles at 32KHz */
		.refr = 7,	/* 8 refresh commands per refresh cycle */
	};

	if (is_mx6dq())
		mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
	else
		mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);

	if (is_cpu_type(MXC_CPU_MX6D))
		mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
	else if (is_cpu_type(MXC_CPU_MX6Q))
		mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
	else if (is_cpu_type(MXC_CPU_MX6DL))
		mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
	else if (is_cpu_type(MXC_CPU_MX6SOLO))
		mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
}

void board_init_f(ulong dummy)
{
	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	ccgr_init();
	gpr_init();

	/* iomux and setup of i2c */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	if (is_cpu_type(MXC_CPU_MX6SOLO))
		spl_dram_init(32);
	else
		spl_dram_init(64);

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
#endif
Commit	Line	Data
b8ce6fe2 FE	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
	6	* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
	7	*
	8	* Based on SPL code from Solidrun tree, which is:
	9	* Author: Tungyi Lin <tungyilin1127@gmail.com>
	10	*
	11	* Derived from EDM_CF_IMX6 code by TechNexion,Inc
	12	* Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
	13	*
	14	* SPDX-License-Identifier: GPL-2.0+
	15	*/
	16
	17	#include <asm/arch/clock.h>
	18	#include <asm/arch/imx-regs.h>
	19	#include <asm/arch/iomux.h>
	20	#include <asm/arch/mx6-pins.h>
f68a9c6b	21	#include <asm/arch/mxc_hdmi.h>
b8ce6fe2 FE	22	#include <asm/errno.h>
	23	#include <asm/gpio.h>
	24	#include <asm/imx-common/iomux-v3.h>
f68a9c6b	25	#include <asm/imx-common/video.h>
b8ce6fe2 FE	26	#include <mmc.h>
b8ce6fe2 FE	27	#include <fsl_esdhc.h>
712be3ee	28	#include <malloc.h>
b8ce6fe2 FE	29	#include <miiphy.h>
	30	#include <netdev.h>
	31	#include <asm/arch/crm_regs.h>
	32	#include <asm/io.h>
	33	#include <asm/arch/sys_proto.h>
b8ce6fe2	34	#include <spl.h>
e1d74379	35	#include <usb.h>
e162c6b1	36	#include <usb/ehci-ci.h>
b8ce6fe2 FE	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
	40	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	41	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	42	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	43
	44	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	45	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	46	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	47
	48	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	49	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	50
	51	#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN \| \
	52	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	53
	54	#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) \| \
	55	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	56
	57	#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
e1d74379	58	#define USB_H1_VBUS IMX_GPIO_NR(1, 0)
b8ce6fe2 FE	59
	60	int dram_init(void)
	61	{
	62	gd->ram_size = imx_ddr_size();
	63	return 0;
	64	}
	65
	66	static iomux_v3_cfg_t const uart1_pads[] = {
cfdcc5f7 FE	67	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
cfdcc5f7 FE	68	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
b8ce6fe2 FE	69	};
	70
	71	static iomux_v3_cfg_t const usdhc2_pads[] = {
cfdcc5f7 FE	72	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	73	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	74	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	75	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	76	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	77	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
b8ce6fe2 FE	78	};
b8ce6fe2 FE	79
feb6cc5c FE	80	static iomux_v3_cfg_t const hb_cbi_sense[] = {
	81	/* These pins are for sensing if it is a CuBox-i or a HummingBoard */
	82	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	83	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	84	};
	85
e1d74379 FE	86	static iomux_v3_cfg_t const usb_pads[] = {
	87	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	88	};
	89
b8ce6fe2 FE	90	static void setup_iomux_uart(void)
b8ce6fe2 FE	91	{
cfdcc5f7	92	SETUP_IOMUX_PADS(uart1_pads);
b8ce6fe2 FE	93	}
	94
	95	static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	96	{USDHC2_BASE_ADDR},
	97	};
	98
	99	int board_mmc_getcd(struct mmc *mmc)
	100	{
	101	return 1; /* uSDHC2 is always present */
	102	}
	103
	104	int board_mmc_init(bd_t *bis)
	105	{
cfdcc5f7	106	SETUP_IOMUX_PADS(usdhc2_pads);
b8ce6fe2 FE	107	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
	108	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	109	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
	110
	111	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	112	}
	113
	114	static iomux_v3_cfg_t const enet_pads[] = {
cfdcc5f7 FE	115	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
cfdcc5f7 FE	116	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
b8ce6fe2	117	/* AR8035 reset */
cfdcc5f7	118	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 \| MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
b8ce6fe2	119	/* AR8035 interrupt */
cfdcc5f7	120	IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
b8ce6fe2	121	/* GPIO16 -> AR8035 25MHz */
cfdcc5f7 FE	122	IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	123	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	124	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	125	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	126	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	127	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	128	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
b8ce6fe2	129	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
cfdcc5f7 FE	130	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
	131	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	132	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
	133	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
	134	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	135	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	136	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
a4d45038 FE	137	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 \| MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
a4d45038 FE	138	IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 \| MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
b8ce6fe2 FE	139	};
	140
	141	static void setup_iomux_enet(void)
	142	{
cfdcc5f7	143	SETUP_IOMUX_PADS(enet_pads);
b8ce6fe2 FE	144
b8ce6fe2 FE	145	gpio_direction_output(ETH_PHY_RESET, 0);
4b421d4e	146	mdelay(10);
b8ce6fe2	147	gpio_set_value(ETH_PHY_RESET, 1);
4b421d4e	148	udelay(100);
b8ce6fe2 FE	149	}
	150
	151	int board_phy_config(struct phy_device *phydev)
	152	{
	153	if (phydev->drv->config)
	154	phydev->drv->config(phydev);
	155
	156	return 0;
	157	}
	158
712be3ee FE	159	/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
	160	#define ETH_PHY_MASK ((1 << 0x0) \| (1 << 0x4))
	161
b8ce6fe2 FE	162	int board_eth_init(bd_t *bis)
	163	{
	164	struct iomuxc const iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
712be3ee FE	165	struct mii_dev *bus;
712be3ee FE	166	struct phy_device *phydev;
b8ce6fe2	167
6d97dc10	168	int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
b8ce6fe2 FE	169	if (ret)
	170	return ret;
	171
	172	/* set gpr1[ENET_CLK_SEL] */
	173	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
	174
	175	setup_iomux_enet();
	176
712be3ee FE	177	bus = fec_get_miibus(IMX_FEC_BASE, -1);
	178	if (!bus)
	179	return -EINVAL;
	180
	181	phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
	182	if (!phydev) {
	183	ret = -EINVAL;
	184	goto free_bus;
	185	}
	186
	187	debug("using phy at address %d\n", phydev->addr);
	188	ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
	189	if (ret)
	190	goto free_phydev;
	191
	192	return 0;
	193
	194	free_phydev:
	195	free(phydev);
	196	free_bus:
	197	free(bus);
	198	return ret;
b8ce6fe2 FE	199	}
b8ce6fe2 FE	200
f68a9c6b FE	201	#ifdef CONFIG_VIDEO_IPUV3
	202	static void do_enable_hdmi(struct display_info_t const *dev)
	203	{
	204	imx_enable_hdmi_phy();
	205	}
	206
	207	struct display_info_t const displays[] = {
	208	{
	209	.bus = -1,
	210	.addr = 0,
	211	.pixfmt = IPU_PIX_FMT_RGB24,
	212	.detect = detect_hdmi,
	213	.enable = do_enable_hdmi,
	214	.mode = {
	215	.name = "HDMI",
	216	/* 1024x768@60Hz (VESA)*/
	217	.refresh = 60,
	218	.xres = 1024,
	219	.yres = 768,
	220	.pixclock = 15384,
	221	.left_margin = 160,
	222	.right_margin = 24,
	223	.upper_margin = 29,
	224	.lower_margin = 3,
	225	.hsync_len = 136,
	226	.vsync_len = 6,
	227	.sync = FB_SYNC_EXT,
	228	.vmode = FB_VMODE_NONINTERLACED
	229	}
	230	}
	231	};
	232
	233	size_t display_count = ARRAY_SIZE(displays);
	234
	235	static int setup_display(void)
	236	{
	237	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	238	int reg;
	239	int timeout = 100000;
	240
	241	enable_ipu_clock();
	242	imx_setup_hdmi();
	243
	244	/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
	245	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
	246
	247	reg = readl(&ccm->analog_pll_video);
	248	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
	249	reg \|= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
	250	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
	251	reg \|= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
	252	writel(reg, &ccm->analog_pll_video);
	253
	254	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
	255	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
	256
	257	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
	258	writel(reg, &ccm->analog_pll_video);
	259
	260	while (timeout--)
	261	if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
	262	break;
	263	if (timeout < 0) {
	264	printf("Warning: video pll lock timeout!\n");
265	return -ETIMEDOUT;
266	}
267
268	reg = readl(&ccm->analog_pll_video);
269	reg \|= BM_ANADIG_PLL_VIDEO_ENABLE;
270	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
271	writel(reg, &ccm->analog_pll_video);
272
273	/* gate ipu1_di0_clk */
274	clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
275
276	/* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
277	reg = readl(&ccm->chsccdr);
278	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK \|
279	MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK \|
280	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
281	reg \|= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) \|
282	(6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) \|
283	(0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
284	writel(reg, &ccm->chsccdr);
285
286	/* enable ipu1_di0_clk */
287	setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
288
289	return 0;
290	}
291	#endif /* CONFIG_VIDEO_IPUV3 */
292
e1d74379 FE	293	#ifdef CONFIG_USB_EHCI_MX6
	294	static void setup_usb(void)
	295	{
	296	SETUP_IOMUX_PADS(usb_pads);
	297	}
	298
	299	int board_ehci_hcd_init(int port)
	300	{
	301	if (port == 1)
	302	gpio_direction_output(USB_H1_VBUS, 1);
	303
	304	return 0;
	305	}
	306	#endif
	307
b8ce6fe2 FE	308	int board_early_init_f(void)
b8ce6fe2 FE	309	{
f68a9c6b	310	int ret = 0;
b8ce6fe2	311	setup_iomux_uart();
f68a9c6b FE	312
	313	#ifdef CONFIG_VIDEO_IPUV3
	314	ret = setup_display();
	315	#endif
e1d74379 FE	316
	317	#ifdef CONFIG_USB_EHCI_MX6
	318	setup_usb();
	319	#endif
f68a9c6b	320	return ret;
b8ce6fe2 FE	321	}
	322
	323	int board_init(void)
	324	{
	325	/* address of boot parameters */
	326	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	327
	328	return 0;
	329	}
	330
feb6cc5c FE	331	static bool is_hummingboard(void)
	332	{
	333	int val1, val2;
	334
	335	SETUP_IOMUX_PADS(hb_cbi_sense);
	336
	337	gpio_direction_input(IMX_GPIO_NR(4, 9));
	338	gpio_direction_input(IMX_GPIO_NR(3, 4));
	339
	340	val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
	341	val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
	342
	343	/*
	344	* Machine selection -
	345	* Machine val1, val2
	346	* -------------------------
	347	* HB rev 3.x x 0
	348	* CBi 0 1
	349	* HB 1 1
	350	*/
	351
	352	if (val2 == 0)
	353	return true;
	354	else if (val1 == 0)
	355	return false;
	356	else
	357	return true;
	358	}
	359
b8ce6fe2 FE	360	int checkboard(void)
b8ce6fe2 FE	361	{
feb6cc5c FE	362	if (is_hummingboard())
	363	puts("Board: MX6 Hummingboard\n");
	364	else
	365	puts("Board: MX6 Cubox-i\n");
	366
b8ce6fe2 FE	367	return 0;
	368	}
	369
205d5869 FE	370	int board_late_init(void)
	371	{
	372	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	373	if (is_hummingboard())
	374	setenv("board_name", "HUMMINGBOARD");
	375	else
	376	setenv("board_name", "CUBOXI");
	377
4a2f9014	378	if (is_mx6dq())
205d5869 FE	379	setenv("board_rev", "MX6Q");
	380	else
	381	setenv("board_rev", "MX6DL");
	382	#endif
	383
	384	return 0;
	385	}
	386
b8ce6fe2	387	#ifdef CONFIG_SPL_BUILD
cfdcc5f7	388	#include <asm/arch/mx6-ddr.h>
8cb6817e	389	static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
b8ce6fe2 FE	390	.dram_sdclk_0 = 0x00020030,
	391	.dram_sdclk_1 = 0x00020030,
	392	.dram_cas = 0x00020030,
	393	.dram_ras = 0x00020030,
	394	.dram_reset = 0x00020030,
	395	.dram_sdcke0 = 0x00003000,
	396	.dram_sdcke1 = 0x00003000,
	397	.dram_sdba2 = 0x00000000,
	398	.dram_sdodt0 = 0x00003030,
	399	.dram_sdodt1 = 0x00003030,
	400	.dram_sdqs0 = 0x00000030,
	401	.dram_sdqs1 = 0x00000030,
	402	.dram_sdqs2 = 0x00000030,
	403	.dram_sdqs3 = 0x00000030,
	404	.dram_sdqs4 = 0x00000030,
	405	.dram_sdqs5 = 0x00000030,
	406	.dram_sdqs6 = 0x00000030,
	407	.dram_sdqs7 = 0x00000030,
	408	.dram_dqm0 = 0x00020030,
	409	.dram_dqm1 = 0x00020030,
	410	.dram_dqm2 = 0x00020030,
	411	.dram_dqm3 = 0x00020030,
	412	.dram_dqm4 = 0x00020030,
	413	.dram_dqm5 = 0x00020030,
	414	.dram_dqm6 = 0x00020030,
	415	.dram_dqm7 = 0x00020030,
	416	};
	417
8cb6817e FE	418	static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
	419	.dram_sdclk_0 = 0x00000028,
	420	.dram_sdclk_1 = 0x00000028,
	421	.dram_cas = 0x00000028,
	422	.dram_ras = 0x00000028,
	423	.dram_reset = 0x000c0028,
	424	.dram_sdcke0 = 0x00003000,
	425	.dram_sdcke1 = 0x00003000,
	426	.dram_sdba2 = 0x00000000,
	427	.dram_sdodt0 = 0x00003030,
	428	.dram_sdodt1 = 0x00003030,
	429	.dram_sdqs0 = 0x00000028,
	430	.dram_sdqs1 = 0x00000028,
	431	.dram_sdqs2 = 0x00000028,
	432	.dram_sdqs3 = 0x00000028,
	433	.dram_sdqs4 = 0x00000028,
	434	.dram_sdqs5 = 0x00000028,
	435	.dram_sdqs6 = 0x00000028,
	436	.dram_sdqs7 = 0x00000028,
	437	.dram_dqm0 = 0x00000028,
	438	.dram_dqm1 = 0x00000028,
	439	.dram_dqm2 = 0x00000028,
	440	.dram_dqm3 = 0x00000028,
	441	.dram_dqm4 = 0x00000028,
	442	.dram_dqm5 = 0x00000028,
	443	.dram_dqm6 = 0x00000028,
	444	.dram_dqm7 = 0x00000028,
	445	};
	446
	447	static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
b8ce6fe2 FE	448	.grp_ddr_type = 0x000C0000,
	449	.grp_ddrmode_ctl = 0x00020000,
	450	.grp_ddrpke = 0x00000000,
	451	.grp_addds = 0x00000030,
	452	.grp_ctlds = 0x00000030,
	453	.grp_ddrmode = 0x00020000,
	454	.grp_b0ds = 0x00000030,
	455	.grp_b1ds = 0x00000030,
	456	.grp_b2ds = 0x00000030,
	457	.grp_b3ds = 0x00000030,
	458	.grp_b4ds = 0x00000030,
	459	.grp_b5ds = 0x00000030,
	460	.grp_b6ds = 0x00000030,
	461	.grp_b7ds = 0x00000030,
	462	};
	463
8cb6817e FE	464	static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	465	.grp_ddr_type = 0x000c0000,
	466	.grp_ddrmode_ctl = 0x00020000,
	467	.grp_ddrpke = 0x00000000,
	468	.grp_addds = 0x00000028,
	469	.grp_ctlds = 0x00000028,
	470	.grp_ddrmode = 0x00020000,
	471	.grp_b0ds = 0x00000028,
	472	.grp_b1ds = 0x00000028,
	473	.grp_b2ds = 0x00000028,
	474	.grp_b3ds = 0x00000028,
	475	.grp_b4ds = 0x00000028,
	476	.grp_b5ds = 0x00000028,
	477	.grp_b6ds = 0x00000028,
	478	.grp_b7ds = 0x00000028,
	479	};
	480
	481	/* microSOM with Dual processor and 1GB memory */
	482	static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
b8ce6fe2 FE	483	.p0_mpwldectrl0 = 0x00000000,
	484	.p0_mpwldectrl1 = 0x00000000,
	485	.p1_mpwldectrl0 = 0x00000000,
	486	.p1_mpwldectrl1 = 0x00000000,
	487	.p0_mpdgctrl0 = 0x0314031c,
	488	.p0_mpdgctrl1 = 0x023e0304,
	489	.p1_mpdgctrl0 = 0x03240330,
	490	.p1_mpdgctrl1 = 0x03180260,
	491	.p0_mprddlctl = 0x3630323c,
	492	.p1_mprddlctl = 0x3436283a,
	493	.p0_mpwrdlctl = 0x36344038,
	494	.p1_mpwrdlctl = 0x422a423c,
	495	};
	496
8cb6817e FE	497	/* microSOM with Quad processor and 2GB memory */
	498	static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
	499	.p0_mpwldectrl0 = 0x00000000,
	500	.p0_mpwldectrl1 = 0x00000000,
	501	.p1_mpwldectrl0 = 0x00000000,
	502	.p1_mpwldectrl1 = 0x00000000,
	503	.p0_mpdgctrl0 = 0x0314031c,
	504	.p0_mpdgctrl1 = 0x023e0304,
	505	.p1_mpdgctrl0 = 0x03240330,
	506	.p1_mpdgctrl1 = 0x03180260,
	507	.p0_mprddlctl = 0x3630323c,
	508	.p1_mprddlctl = 0x3436283a,
	509	.p0_mpwrdlctl = 0x36344038,
	510	.p1_mpwrdlctl = 0x422a423c,
	511	};
	512
	513	/* microSOM with Solo processor and 512MB memory */
	514	static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
	515	.p0_mpwldectrl0 = 0x0045004D,
	516	.p0_mpwldectrl1 = 0x003A0047,
	517	.p0_mpdgctrl0 = 0x023C0224,
	518	.p0_mpdgctrl1 = 0x02000220,
	519	.p0_mprddlctl = 0x44444846,
	520	.p0_mpwrdlctl = 0x32343032,
	521	};
	522
	523	/* microSOM with Dual lite processor and 1GB memory */
	524	static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
	525	.p0_mpwldectrl0 = 0x0045004D,
	526	.p0_mpwldectrl1 = 0x003A0047,
	527	.p1_mpwldectrl0 = 0x001F001F,
	528	.p1_mpwldectrl1 = 0x00210035,
	529	.p0_mpdgctrl0 = 0x023C0224,
	530	.p0_mpdgctrl1 = 0x02000220,
	531	.p1_mpdgctrl0 = 0x02200220,
dbab8b8e	532	.p1_mpdgctrl1 = 0x02040208,
8cb6817e FE	533	.p0_mprddlctl = 0x44444846,
	534	.p1_mprddlctl = 0x4042463C,
	535	.p0_mpwrdlctl = 0x32343032,
	536	.p1_mpwrdlctl = 0x36363430,
	537	};
	538
	539	static struct mx6_ddr3_cfg mem_ddr_2g = {
b8ce6fe2 FE	540	.mem_speed = 1600,
	541	.density = 2,
	542	.width = 16,
	543	.banks = 8,
	544	.rowaddr = 14,
	545	.coladdr = 10,
	546	.pagesz = 2,
	547	.trcd = 1375,
	548	.trcmin = 4875,
	549	.trasmin = 3500,
	550	.SRT = 1,
	551	};
	552
8cb6817e FE	553	static struct mx6_ddr3_cfg mem_ddr_4g = {
	554	.mem_speed = 1600,
	555	.density = 4,
	556	.width = 16,
	557	.banks = 8,
	558	.rowaddr = 15,
	559	.coladdr = 10,
	560	.pagesz = 2,
	561	.trcd = 1375,
	562	.trcmin = 4875,
	563	.trasmin = 3500,
	564	};
	565
b8ce6fe2 FE	566	static void ccgr_init(void)
	567	{
	568	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	569
	570	writel(0x00C03F3F, &ccm->CCGR0);
	571	writel(0x0030FC03, &ccm->CCGR1);
	572	writel(0x0FFFC000, &ccm->CCGR2);
	573	writel(0x3FF00000, &ccm->CCGR3);
	574	writel(0x00FFF300, &ccm->CCGR4);
	575	writel(0x0F0000C3, &ccm->CCGR5);
	576	writel(0x000003FF, &ccm->CCGR6);
	577	}
	578
	579	static void gpr_init(void)
	580	{
	581	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	582
	583	/* enable AXI cache for VDOA/VPU/IPU */
	584	writel(0xF00000CF, &iomux->gpr[4]);
	585	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	586	writel(0x007F007F, &iomux->gpr[6]);
	587	writel(0x007F007F, &iomux->gpr[7]);
	588	}
	589
8cb6817e	590	static void spl_dram_init(int width)
b8ce6fe2 FE	591	{
	592	struct mx6_ddr_sysinfo sysinfo = {
	593	/* width of data bus: 0=16, 1=32, 2=64 */
8cb6817e	594	.dsize = width / 32,
b8ce6fe2 FE	595	/* config for full 4GB range so that get_mem_size() works */
	596	.cs_density = 32, /* 32Gb per CS */
	597	.ncs = 1, /* single chip select */
	598	.cs1_mirror = 0,
	599	.rtt_wr = 1 /DDR3_RTT_60_OHM/, /* RTT_Wr = RZQ/4 */
	600	.rtt_nom = 1 /DDR3_RTT_60_OHM/, /* RTT_Nom = RZQ/4 */
	601	.walat = 1, /* Write additional latency */
	602	.ralat = 5, /* Read additional latency */
	603	.mif3_mode = 3, /* Command prediction working mode */
	604	.bi_on = 1, /* Bank interleaving enabled */
	605	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	606	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
f2ff8343	607	.ddr_type = DDR_TYPE_DDR3,
edf00937 FE	608	.refsel = 1, /* Refresh cycles at 32KHz */
edf00937 FE	609	.refr = 7, /* 8 refresh commands per refresh cycle */
b8ce6fe2 FE	610	};
b8ce6fe2 FE	611
4a2f9014	612	if (is_mx6dq())
8cb6817e FE	613	mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
	614	else
	615	mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
	616
	617	if (is_cpu_type(MXC_CPU_MX6D))
	618	mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
	619	else if (is_cpu_type(MXC_CPU_MX6Q))
	620	mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
	621	else if (is_cpu_type(MXC_CPU_MX6DL))
dbab8b8e	622	mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
8cb6817e FE	623	else if (is_cpu_type(MXC_CPU_MX6SOLO))
8cb6817e FE	624	mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
b8ce6fe2 FE	625	}
	626
	627	void board_init_f(ulong dummy)
	628	{
	629	/* setup AIPS and disable watchdog */
	630	arch_cpu_init();
	631
	632	ccgr_init();
	633	gpr_init();
	634
	635	/* iomux and setup of i2c */
	636	board_early_init_f();
	637
	638	/* setup GP timer */
	639	timer_init();
	640
	641	/* UART clocks enabled and gd valid - init serial console */
	642	preloader_console_init();
	643
	644	/* DDR initialization */
8cb6817e FE	645	if (is_cpu_type(MXC_CPU_MX6SOLO))
	646	spl_dram_init(32);
	647	else
	648	spl_dram_init(64);
b8ce6fe2 FE	649
	650	/* Clear the BSS. */
	651	memset(__bss_start, 0, __bss_end - __bss_start);
	652
	653	/* load/boot image from boot device */
	654	board_init_r(NULL, 0);
	655	}
	656	#endif