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d5254f14 AR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * STMicrolelctronics, <www.st.com> | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * ARM Ltd. | |
7 | * Philippe Robin, <philippe.robin@arm.com> | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
d5254f14 AR |
10 | */ |
11 | ||
12 | #include <common.h> | |
7194ab80 | 13 | #include <netdev.h> |
d5254f14 | 14 | #include <asm/io.h> |
bb4291e6 | 15 | #include <asm/arch/gpio.h> |
d5254f14 AR |
16 | |
17 | DECLARE_GLOBAL_DATA_PTR; | |
18 | ||
19 | #ifdef CONFIG_SHOW_BOOT_PROGRESS | |
20 | void show_boot_progress(int progress) | |
21 | { | |
22 | printf("%i\n", progress); | |
23 | } | |
24 | #endif | |
25 | ||
26 | /* | |
27 | * Miscellaneous platform dependent initialisations | |
28 | */ | |
29 | int board_init(void) | |
30 | { | |
31 | gd->bd->bi_arch_number = MACH_TYPE_NOMADIK; | |
32 | gd->bd->bi_boot_params = 0x00000100; | |
33 | writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20); | |
34 | writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24); | |
35 | writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28); | |
36 | writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE); | |
37 | ||
d3be1bca AR |
38 | /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */ |
39 | writel(0x0000305b, REG_FSMC_BCR1); | |
40 | writel(0x00033f33, REG_FSMC_BTR1); | |
d5254f14 | 41 | |
f7aa59b2 AR |
42 | /* Set up SMCS0 for OneNand: sram-like once again */ |
43 | writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */ | |
44 | writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */ | |
45 | ||
d3be1bca | 46 | icache_enable(); |
d5254f14 AR |
47 | return 0; |
48 | } | |
49 | ||
bb4291e6 | 50 | int board_late_init(void) |
d5254f14 | 51 | { |
bb4291e6 AR |
52 | /* Set the two I2C gpio lines to be gpio high */ |
53 | nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1); | |
54 | nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1); | |
55 | nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO); | |
56 | ||
57 | /* Reset the I2C port expander, on GPIO77 */ | |
58 | nmk_gpio_af(77, GPIO_GPIO); | |
59 | nmk_gpio_dir(77, 1); | |
60 | nmk_gpio_set(77, 0); | |
61 | udelay(10); | |
62 | nmk_gpio_set(77, 1); | |
63 | ||
d5254f14 AR |
64 | return 0; |
65 | } | |
66 | ||
67 | int dram_init(void) | |
68 | { | |
afba32bc AR |
69 | gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, |
70 | CONFIG_SYS_SDRAM_SIZE); | |
71 | return 0; | |
72 | } | |
73 | ||
74 | void dram_init_banksize(void) | |
75 | { | |
d5254f14 AR |
76 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
77 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
78 | ||
79 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; | |
80 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | |
d5254f14 | 81 | } |
7194ab80 BW |
82 | |
83 | #ifdef CONFIG_CMD_NET | |
84 | int board_eth_init(bd_t *bis) | |
85 | { | |
86 | int rc = 0; | |
87 | #ifdef CONFIG_SMC91111 | |
88 | rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); | |
89 | #endif | |
90 | return rc; | |
91 | } | |
92 | #endif |