[people/ms/u-boot.git] / board / st / stm32f746-disco / stm32f746-disco.c

/*
 * (C) Copyright 2016
 * Vikas Manocha, <vikas.manocha@st.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <ram.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
#include <asm/arch/fmc.h>
#include <dm/platform_data/serial_stm32x7.h>
#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_defs.h>
#include <asm/arch/syscfg.h>
#include <asm/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
{
	int mr_node;

	mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
	if (mr_node < 0)
		return mr_node;
	*mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
						      "reg", 0, mr_size, false);
	debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);

	return 0;
}
int dram_init(void)
{
	int rv;
	fdt_addr_t mr_base, mr_size;

#ifndef CONFIG_SUPPORT_SPL
	struct udevice *dev;
	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
	if (rv) {
		debug("DRAM init failed: %d\n", rv);
		return rv;
	}

#endif
	rv = get_memory_base_size(&mr_base, &mr_size);
	if (rv)
		return rv;
	gd->ram_size = mr_size;
	gd->ram_top = mr_base;

	return rv;
}

int dram_init_banksize(void)
{
	fdt_addr_t mr_base, mr_size;
	get_memory_base_size(&mr_base, &mr_size);
	/*
	 * Fill in global info with description of SRAM configuration
	 */
	gd->bd->bi_dram[0].start = mr_base;
	gd->bd->bi_dram[0].size  = mr_size;

	return 0;
}

#ifdef CONFIG_ETH_DESIGNWARE
static int stmmac_setup(void)
{
	clock_setup(SYSCFG_CLOCK_CFG);
	/* Set >RMII mode */
	STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
	clock_setup(STMMAC_CLOCK_CFG);

	return 0;
}

int board_early_init_f(void)
{
	stmmac_setup();

	return 0;
}
#endif

#ifdef CONFIG_SPL_BUILD
int spl_dram_init(void)
{
	struct udevice *dev;
	int rv;
	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
	if (rv)
		debug("DRAM init failed: %d\n", rv);
	return rv;
}
void spl_board_init(void)
{
	spl_dram_init();
	preloader_console_init();
	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
}
u32 spl_boot_device(void)
{
	return BOOT_DEVICE_NOR;
}

#endif
u32 get_board_rev(void)
{
	return 0;
}

int board_late_init(void)
{
	struct gpio_desc gpio = {};
	int node;

	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
	if (node < 0)
		return -1;

	gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
				   GPIOD_IS_OUT);

	if (dm_gpio_is_valid(&gpio)) {
		dm_gpio_set_value(&gpio, 0);
		mdelay(10);
		dm_gpio_set_value(&gpio, 1);
	}

	/* read button 1*/
	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
	if (node < 0)
		return -1;

	gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
				   &gpio, GPIOD_IS_IN);

	if (dm_gpio_is_valid(&gpio)) {
		if (dm_gpio_get_value(&gpio))
			puts("usr button is at HIGH LEVEL\n");
		else
			puts("usr button is at LOW LEVEL\n");
	}

	return 0;
}

int board_init(void)
{
	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
	return 0;
}
Commit	Line	Data
e66c49fa VM	1	/*
	2	* (C) Copyright 2016
	3	* Vikas Manocha, <vikas.manocha@st.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
2d9c33ca VM	9	#include <dm.h>
2d9c33ca VM	10	#include <ram.h>
b9747696	11	#include <spl.h>
e66c49fa VM	12	#include <asm/io.h>
	13	#include <asm/armv7m.h>
	14	#include <asm/arch/stm32.h>
	15	#include <asm/arch/gpio.h>
9d922450	16	#include <asm/arch/fmc.h>
e66c49fa VM	17	#include <dm/platform_data/serial_stm32x7.h>
	18	#include <asm/arch/stm32_periph.h>
	19	#include <asm/arch/stm32_defs.h>
b20b70fc	20	#include <asm/arch/syscfg.h>
2f80a9f7	21	#include <asm/gpio.h>
e66c49fa VM	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
57af3cc3 VM	25	int get_memory_base_size(fdt_addr_t mr_base, fdt_addr_t mr_size)
	26	{
	27	int mr_node;
	28
	29	mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
	30	if (mr_node < 0)
	31	return mr_node;
	32	*mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
	33	"reg", 0, mr_size, false);
	34	debug("mr_base = %lx, mr_size= %lx\n", mr_base, mr_size);
	35
	36	return 0;
	37	}
25c1b135 TN	38	int dram_init(void)
25c1b135 TN	39	{
25c1b135	40	int rv;
57af3cc3	41	fdt_addr_t mr_base, mr_size;
25c1b135	42
b9747696 VM	43	#ifndef CONFIG_SUPPORT_SPL
b9747696 VM	44	struct udevice *dev;
2d9c33ca VM	45	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
	46	if (rv) {
	47	debug("DRAM init failed: %d\n", rv);
	48	return rv;
	49	}
57af3cc3	50
b9747696	51	#endif
57af3cc3 VM	52	rv = get_memory_base_size(&mr_base, &mr_size);
57af3cc3 VM	53	if (rv)
2d9c33ca	54	return rv;
57af3cc3 VM	55	gd->ram_size = mr_size;
57af3cc3 VM	56	gd->ram_top = mr_base;
25c1b135	57
57af3cc3 VM	58	return rv;
	59	}
	60
	61	int dram_init_banksize(void)
	62	{
	63	fdt_addr_t mr_base, mr_size;
	64	get_memory_base_size(&mr_base, &mr_size);
25c1b135 TN	65	/*
	66	* Fill in global info with description of SRAM configuration
	67	*/
57af3cc3 VM	68	gd->bd->bi_dram[0].start = mr_base;
57af3cc3 VM	69	gd->bd->bi_dram[0].size = mr_size;
25c1b135	70
57af3cc3	71	return 0;
25c1b135 TN	72	}
25c1b135 TN	73
b20b70fc	74	#ifdef CONFIG_ETH_DESIGNWARE
b20b70fc MK	75	static int stmmac_setup(void)
b20b70fc MK	76	{
b20b70fc	77	clock_setup(SYSCFG_CLOCK_CFG);
b20b70fc MK	78	/* Set >RMII mode */
b20b70fc MK	79	STM32_SYSCFG->pmc \|= SYSCFG_PMC_MII_RMII_SEL;
b20b70fc MK	80	clock_setup(STMMAC_CLOCK_CFG);
	81
	82	return 0;
	83	}
b20b70fc	84
280057bd	85	int board_early_init_f(void)
d4363baa	86	{
280057bd VM	87	stmmac_setup();
280057bd VM	88
d4363baa MK	89	return 0;
	90	}
	91	#endif
	92
b9747696 VM	93	#ifdef CONFIG_SPL_BUILD
	94	int spl_dram_init(void)
	95	{
	96	struct udevice *dev;
	97	int rv;
	98	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
	99	if (rv)
	100	debug("DRAM init failed: %d\n", rv);
	101	return rv;
	102	}
	103	void spl_board_init(void)
	104	{
	105	spl_dram_init();
	106	preloader_console_init();
	107	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
	108	}
	109	u32 spl_boot_device(void)
	110	{
	111	return BOOT_DEVICE_NOR;
	112	}
	113
	114	#endif
e66c49fa VM	115	u32 get_board_rev(void)
	116	{
	117	return 0;
	118	}
	119
2f80a9f7 VM	120	int board_late_init(void)
	121	{
	122	struct gpio_desc gpio = {};
	123	int node;
	124
	125	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
	126	if (node < 0)
	127	return -1;
	128
150c5afe	129	gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
2f80a9f7 VM	130	GPIOD_IS_OUT);
	131
	132	if (dm_gpio_is_valid(&gpio)) {
	133	dm_gpio_set_value(&gpio, 0);
	134	mdelay(10);
	135	dm_gpio_set_value(&gpio, 1);
	136	}
	137
	138	/* read button 1*/
	139	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
	140	if (node < 0)
	141	return -1;
	142
150c5afe SG	143	gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
150c5afe SG	144	&gpio, GPIOD_IS_IN);
2f80a9f7 VM	145
	146	if (dm_gpio_is_valid(&gpio)) {
	147	if (dm_gpio_get_value(&gpio))
	148	puts("usr button is at HIGH LEVEL\n");
	149	else
	150	puts("usr button is at LOW LEVEL\n");
	151	}
	152
	153	return 0;
	154	}
	155
e66c49fa VM	156	int board_init(void)
e66c49fa VM	157	{
57af3cc3	158	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
e66c49fa VM	159	return 0;
e66c49fa VM	160	}