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9fa32b12 VM |
1 | /* |
2 | * (C) Copyright 2014 | |
3 | * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <miiphy.h> | |
10 | #include <asm/arch/stv0991_periph.h> | |
11 | #include <asm/arch/stv0991_defs.h> | |
2ce4eaf4 VM |
12 | #include <asm/arch/hardware.h> |
13 | #include <asm/arch/gpio.h> | |
14 | #include <netdev.h> | |
15 | #include <asm/io.h> | |
39e4795a VM |
16 | #include <dm/platdata.h> |
17 | #include <dm/platform_data/serial_pl01x.h> | |
9fa32b12 VM |
18 | |
19 | DECLARE_GLOBAL_DATA_PTR; | |
20 | ||
2ce4eaf4 VM |
21 | struct gpio_regs *const gpioa_regs = |
22 | (struct gpio_regs *) GPIOA_BASE_ADDR; | |
23 | ||
e0320b74 | 24 | #ifndef CONFIG_OF_CONTROL |
39e4795a VM |
25 | static const struct pl01x_serial_platdata serial_platdata = { |
26 | .base = 0x80406000, | |
27 | .type = TYPE_PL011, | |
28 | .clock = 2700 * 1000, | |
29 | }; | |
30 | ||
31 | U_BOOT_DEVICE(stv09911_serials) = { | |
32 | .name = "serial_pl01x", | |
33 | .platdata = &serial_platdata, | |
34 | }; | |
e0320b74 | 35 | #endif |
39e4795a | 36 | |
9fa32b12 VM |
37 | #ifdef CONFIG_SHOW_BOOT_PROGRESS |
38 | void show_boot_progress(int progress) | |
39 | { | |
40 | printf("%i\n", progress); | |
41 | } | |
42 | #endif | |
43 | ||
2ce4eaf4 VM |
44 | void enable_eth_phy(void) |
45 | { | |
46 | /* Set GPIOA_06 pad HIGH (Appli board)*/ | |
47 | writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir); | |
48 | writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data); | |
49 | } | |
50 | int board_eth_enable(void) | |
51 | { | |
52 | stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4); | |
53 | clock_setup(ETH_CLOCK_CFG); | |
54 | enable_eth_phy(); | |
55 | return 0; | |
56 | } | |
57 | ||
54afb500 VM |
58 | int board_qspi_enable(void) |
59 | { | |
60 | stv0991_pinmux_config(QSPI_CS_CLK_PAD); | |
61 | clock_setup(QSPI_CLOCK_CFG); | |
62 | return 0; | |
63 | } | |
64 | ||
9fa32b12 VM |
65 | /* |
66 | * Miscellaneous platform dependent initialisations | |
67 | */ | |
68 | int board_init(void) | |
69 | { | |
2ce4eaf4 | 70 | board_eth_enable(); |
54afb500 | 71 | board_qspi_enable(); |
9fa32b12 VM |
72 | return 0; |
73 | } | |
74 | ||
75 | int board_uart_init(void) | |
76 | { | |
77 | stv0991_pinmux_config(UART_GPIOC_30_31); | |
78 | clock_setup(UART_CLOCK_CFG); | |
79 | return 0; | |
80 | } | |
2ce4eaf4 | 81 | |
9fa32b12 VM |
82 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
83 | int board_early_init_f(void) | |
84 | { | |
85 | board_uart_init(); | |
86 | return 0; | |
87 | } | |
88 | #endif | |
89 | ||
90 | int dram_init(void) | |
91 | { | |
92 | gd->ram_size = PHYS_SDRAM_1_SIZE; | |
93 | return 0; | |
94 | } | |
95 | ||
76b00aca | 96 | int dram_init_banksize(void) |
9fa32b12 VM |
97 | { |
98 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
99 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
76b00aca SG |
100 | |
101 | return 0; | |
9fa32b12 | 102 | } |
2ce4eaf4 VM |
103 | |
104 | #ifdef CONFIG_CMD_NET | |
105 | int board_eth_init(bd_t *bis) | |
106 | { | |
107 | int ret = 0; | |
108 | ||
ef48f6dd | 109 | #if defined(CONFIG_ETH_DESIGNWARE) |
2ce4eaf4 VM |
110 | u32 interface = PHY_INTERFACE_MODE_MII; |
111 | if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0) | |
112 | ret++; | |
113 | #endif | |
114 | return ret; | |
115 | } | |
116 | #endif |