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Convert CONFIG_SPL_LIBGENERIC_SUPPORT to Kconfig
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1if ARCH_SUNXI
2
53b5bf3c
SG
3config SPL_GPIO_SUPPORT
4 default y
5
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SG
6config SPL_LIBCOMMON_SUPPORT
7 default y
8
1646eba8
SG
9config SPL_LIBDISK_SUPPORT
10 default y
11
cc4288ef
SG
12config SPL_LIBGENERIC_SUPPORT
13 default y
14
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HG
15# Note only one of these may be selected at a time! But hidden choices are
16# not supported by Kconfig
17config SUNXI_GEN_SUN4I
18 bool
19 ---help---
20 Select this for sunxi SoCs which have resets and clocks set up
21 as the original A10 (mach-sun4i).
22
23config SUNXI_GEN_SUN6I
24 bool
25 ---help---
26 Select this for sunxi SoCs which have sun6i like periphery, like
27 separate ahb reset control registers, custom pmic bus, new style
28 watchdog, etc.
29
30
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31choice
32 prompt "Sunxi SoC Variant"
3da9536e 33 optional
2c7e3b90 34
c3be2793 35config MACH_SUN4I
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36 bool "sun4i (Allwinner A10)"
37 select CPU_V7
44d8ae5b 38 select SUNXI_GEN_SUN4I
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39 select SUPPORT_SPL
40
c3be2793 41config MACH_SUN5I
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42 bool "sun5i (Allwinner A13)"
43 select CPU_V7
44d8ae5b 44 select SUNXI_GEN_SUN4I
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45 select SUPPORT_SPL
46
c3be2793 47config MACH_SUN6I
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48 bool "sun6i (Allwinner A31)"
49 select CPU_V7
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50 select CPU_V7_HAS_NONSEC
51 select CPU_V7_HAS_VIRT
217f92bb 52 select ARCH_SUPPORT_PSCI
44d8ae5b 53 select SUNXI_GEN_SUN6I
8c2c9cfa 54 select SUPPORT_SPL
cc08ea4c 55 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 56
c3be2793 57config MACH_SUN7I
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58 bool "sun7i (Allwinner A20)"
59 select CPU_V7
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60 select CPU_V7_HAS_NONSEC
61 select CPU_V7_HAS_VIRT
217f92bb 62 select ARCH_SUPPORT_PSCI
44d8ae5b 63 select SUNXI_GEN_SUN4I
2c7e3b90 64 select SUPPORT_SPL
b366fb92 65 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 66
5e6bacdb 67config MACH_SUN8I_A23
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68 bool "sun8i (Allwinner A23)"
69 select CPU_V7
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70 select CPU_V7_HAS_NONSEC
71 select CPU_V7_HAS_VIRT
217f92bb 72 select ARCH_SUPPORT_PSCI
44d8ae5b 73 select SUNXI_GEN_SUN6I
08fd1479 74 select SUPPORT_SPL
014414f5 75 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
2c7e3b90 76
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77config MACH_SUN8I_A33
78 bool "sun8i (Allwinner A33)"
79 select CPU_V7
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80 select CPU_V7_HAS_NONSEC
81 select CPU_V7_HAS_VIRT
217f92bb 82 select ARCH_SUPPORT_PSCI
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83 select SUNXI_GEN_SUN6I
84 select SUPPORT_SPL
014414f5 85 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
8c3dacff 86
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87config MACH_SUN8I_A83T
88 bool "sun8i (Allwinner A83T)"
89 select CPU_V7
90 select SUNXI_GEN_SUN6I
91 select SUPPORT_SPL
92
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93config MACH_SUN8I_H3
94 bool "sun8i (Allwinner H3)"
95 select CPU_V7
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96 select CPU_V7_HAS_NONSEC
97 select CPU_V7_HAS_VIRT
217f92bb 98 select ARCH_SUPPORT_PSCI
1c27b7dc 99 select SUNXI_GEN_SUN6I
0404d53f 100 select SUPPORT_SPL
853f6d1e 101 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
1c27b7dc 102
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103config MACH_SUN9I
104 bool "sun9i (Allwinner A80)"
105 select CPU_V7
106 select SUNXI_GEN_SUN6I
107
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108config MACH_SUN50I
109 bool "sun50i (Allwinner A64)"
110 select ARM64
111 select SUNXI_GEN_SUN6I
112
2c7e3b90 113endchoice
8a6564da 114
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HG
115# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
116config MACH_SUN8I
117 bool
762e24a0 118 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
5e6bacdb 119
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120config DRAM_TYPE
121 int "sunxi dram type"
122 depends on MACH_SUN8I_A83T
123 default 3
124 ---help---
125 Set the dram type, 3: DDR3, 7: LPDDR3
5e6bacdb 126
37781a1a 127config DRAM_CLK
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HG
128 int "sunxi dram clock speed"
129 default 312 if MACH_SUN6I || MACH_SUN8I
130 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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HG
131 ---help---
132 Set the dram clock speed, valid range 240 - 480, must be a multiple
e1a0888e 133 of 24.
37781a1a 134
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SS
135if MACH_SUN5I || MACH_SUN7I
136config DRAM_MBUS_CLK
137 int "sunxi mbus clock speed"
138 default 300
139 ---help---
140 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
141
142endif
143
37781a1a 144config DRAM_ZQ
8ffc487c
HG
145 int "sunxi dram zq value"
146 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
147 default 127 if MACH_SUN7I
37781a1a 148 ---help---
e1a0888e 149 Set the dram zq value.
8ffc487c 150
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HG
151config DRAM_ODT_EN
152 bool "sunxi dram odt enable"
153 default n if !MACH_SUN8I_A23
154 default y if MACH_SUN8I_A23
155 ---help---
156 Select this to enable dram odt (on die termination).
157
8ffc487c
HG
158if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
159config DRAM_EMR1
160 int "sunxi dram emr1 value"
161 default 0 if MACH_SUN4I
162 default 4 if MACH_SUN5I || MACH_SUN7I
163 ---help---
e1a0888e 164 Set the dram controller emr1 value.
d133647a 165
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SS
166config DRAM_TPR3
167 hex "sunxi dram tpr3 value"
168 default 0
169 ---help---
170 Set the dram controller tpr3 parameter. This parameter configures
171 the delay on the command lane and also phase shifts, which are
172 applied for sampling incoming read data. The default value 0
173 means that no phase/delay adjustments are necessary. Properly
174 configuring this parameter increases reliability at high DRAM
175 clock speeds.
176
177config DRAM_DQS_GATING_DELAY
178 hex "sunxi dram dqs_gating_delay value"
179 default 0
180 ---help---
181 Set the dram controller dqs_gating_delay parmeter. Each byte
182 encodes the DQS gating delay for each byte lane. The delay
183 granularity is 1/4 cycle. For example, the value 0x05060606
184 means that the delay is 5 quarter-cycles for one lane (1.25
185 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
186 The default value 0 means autodetection. The results of hardware
187 autodetection are not very reliable and depend on the chip
188 temperature (sometimes producing different results on cold start
189 and warm reboot). But the accuracy of hardware autodetection
190 is usually good enough, unless running at really high DRAM
191 clocks speeds (up to 600MHz). If unsure, keep as 0.
192
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SS
193choice
194 prompt "sunxi dram timings"
195 default DRAM_TIMINGS_VENDOR_MAGIC
196 ---help---
197 Select the timings of the DDR3 chips.
198
199config DRAM_TIMINGS_VENDOR_MAGIC
200 bool "Magic vendor timings from Android"
201 ---help---
202 The same DRAM timings as in the Allwinner boot0 bootloader.
203
204config DRAM_TIMINGS_DDR3_1066F_1333H
205 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
206 ---help---
207 Use the timings of the standard JEDEC DDR3-1066F speed bin for
208 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
209 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
210 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
211 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
212 that down binning to DDR3-1066F is supported (because DDR3-1066F
213 uses a bit faster timings than DDR3-1333H).
214
215config DRAM_TIMINGS_DDR3_800E_1066G_1333J
216 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
217 ---help---
218 Use the timings of the slowest possible JEDEC speed bin for the
219 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
220 DDR3-800E, DDR3-1066G or DDR3-1333J.
221
222endchoice
223
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HG
224endif
225
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HG
226if MACH_SUN8I_A23
227config DRAM_ODT_CORRECTION
228 int "sunxi dram odt correction value"
229 default 0
230 ---help---
231 Set the dram odt correction value (range -255 - 255). In allwinner
232 fex files, this option is found in bits 8-15 of the u32 odt_en variable
233 in the [dram] section. When bit 31 of the odt_en variable is set
234 then the correction is negative. Usually the value for this is 0.
235endif
236
e71b422b 237config SYS_CLK_FREQ
d96ebc46 238 default 816000000 if MACH_SUN50I
e71b422b
IP
239 default 912000000 if MACH_SUN7I
240 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
241
8a6564da 242config SYS_CONFIG_NAME
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243 default "sun4i" if MACH_SUN4I
244 default "sun5i" if MACH_SUN5I
245 default "sun6i" if MACH_SUN6I
246 default "sun7i" if MACH_SUN7I
247 default "sun8i" if MACH_SUN8I
1871a8ca 248 default "sun9i" if MACH_SUN9I
d96ebc46 249 default "sun50i" if MACH_SUN50I
dd84058d 250
dd84058d 251config SYS_BOARD
dd84058d
MY
252 default "sunxi"
253
254config SYS_SOC
dd84058d
MY
255 default "sunxi"
256
f0ce28e9
SS
257config UART0_PORT_F
258 bool "UART0 on MicroSD breakout board"
f0ce28e9
SS
259 default n
260 ---help---
261 Repurpose the SD card slot for getting access to the UART0 serial
262 console. Primarily useful only for low level u-boot debugging on
263 tablets, where normal UART0 is difficult to access and requires
264 device disassembly and/or soldering. As the SD card can't be used
265 at the same time, the system can be only booted in the FEL mode.
266 Only enable this if you really know what you are doing.
267
accc9e44 268config OLD_SUNXI_KERNEL_COMPAT
ab65006b 269 bool "Enable workarounds for booting old kernels"
accc9e44
HG
270 default n
271 ---help---
272 Set this to enable various workarounds for old kernels, this results in
273 sub-optimal settings for newer kernels, only enable if needed.
274
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MR
275config MMC
276 depends on !UART0_PORT_F
277 default y if ARCH_SUNXI
278
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HG
279config MMC0_CD_PIN
280 string "Card detect pin for mmc0"
acdab175 281 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
cd82113a
HG
282 default ""
283 ---help---
284 Set the card detect pin for mmc0, leave empty to not use cd. This
285 takes a string in the format understood by sunxi_name_to_gpio, e.g.
286 PH1 for pin 1 of port H.
287
288config MMC1_CD_PIN
289 string "Card detect pin for mmc1"
290 default ""
291 ---help---
292 See MMC0_CD_PIN help text.
293
294config MMC2_CD_PIN
295 string "Card detect pin for mmc2"
296 default ""
297 ---help---
298 See MMC0_CD_PIN help text.
299
300config MMC3_CD_PIN
301 string "Card detect pin for mmc3"
302 default ""
303 ---help---
304 See MMC0_CD_PIN help text.
305
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PK
306config MMC1_PINS
307 string "Pins for mmc1"
308 default ""
309 ---help---
310 Set the pins used for mmc1, when applicable. This takes a string in the
311 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
312
313config MMC2_PINS
314 string "Pins for mmc2"
315 default ""
316 ---help---
317 See MMC1_PINS help text.
318
319config MMC3_PINS
320 string "Pins for mmc3"
321 default ""
322 ---help---
323 See MMC1_PINS help text.
324
2ccfac01
HG
325config MMC_SUNXI_SLOT_EXTRA
326 int "mmc extra slot number"
327 default -1
328 ---help---
329 sunxi builds always enable mmc0, some boards also have a second sdcard
330 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
331 support for this.
332
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HG
333config INITIAL_USB_SCAN_DELAY
334 int "delay initial usb scan by x ms to allow builtin devices to init"
335 default 0
336 ---help---
337 Some boards have on board usb devices which need longer than the
338 USB spec's 1 second to connect from board powerup. Set this config
339 option to a non 0 value to add an extra delay before the first usb
340 bus scan.
341
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HG
342config USB0_VBUS_PIN
343 string "Vbus enable pin for usb0 (otg)"
344 default ""
345 ---help---
346 Set the Vbus enable pin for usb0 (otg). This takes a string in the
347 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
348
52defe8f
HG
349config USB0_VBUS_DET
350 string "Vbus detect pin for usb0 (otg)"
52defe8f
HG
351 default ""
352 ---help---
353 Set the Vbus detect pin for usb0 (otg). This takes a string in the
354 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
355
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HG
356config USB0_ID_DET
357 string "ID detect pin for usb0 (otg)"
358 default ""
359 ---help---
360 Set the ID detect pin for usb0 (otg). This takes a string in the
361 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
362
115200ce
HG
363config USB1_VBUS_PIN
364 string "Vbus enable pin for usb1 (ehci0)"
365 default "PH6" if MACH_SUN4I || MACH_SUN7I
76946dfe 366 default "PH27" if MACH_SUN6I
115200ce
HG
367 ---help---
368 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
369 a string in the format understood by sunxi_name_to_gpio, e.g.
370 PH1 for pin 1 of port H.
371
372config USB2_VBUS_PIN
373 string "Vbus enable pin for usb2 (ehci1)"
374 default "PH3" if MACH_SUN4I || MACH_SUN7I
76946dfe 375 default "PH24" if MACH_SUN6I
115200ce
HG
376 ---help---
377 See USB1_VBUS_PIN help text.
378
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HG
379config USB3_VBUS_PIN
380 string "Vbus enable pin for usb3 (ehci2)"
381 default ""
382 ---help---
383 See USB1_VBUS_PIN help text.
384
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PK
385config I2C0_ENABLE
386 bool "Enable I2C/TWI controller 0"
387 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
388 default n if MACH_SUN6I || MACH_SUN8I
0878a8a7 389 select CMD_I2C
6c739c5d
PK
390 ---help---
391 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
392 its clock and setting up the bus. This is especially useful on devices
393 with slaves connected to the bus or with pins exposed through e.g. an
394 expansion port/header.
395
396config I2C1_ENABLE
397 bool "Enable I2C/TWI controller 1"
398 default n
0878a8a7 399 select CMD_I2C
6c739c5d
PK
400 ---help---
401 See I2C0_ENABLE help text.
402
403config I2C2_ENABLE
404 bool "Enable I2C/TWI controller 2"
405 default n
0878a8a7 406 select CMD_I2C
6c739c5d
PK
407 ---help---
408 See I2C0_ENABLE help text.
409
410if MACH_SUN6I || MACH_SUN7I
411config I2C3_ENABLE
412 bool "Enable I2C/TWI controller 3"
413 default n
0878a8a7 414 select CMD_I2C
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PK
415 ---help---
416 See I2C0_ENABLE help text.
417endif
418
0d8382ae 419if SUNXI_GEN_SUN6I
9d082687
JW
420config R_I2C_ENABLE
421 bool "Enable the PRCM I2C/TWI controller"
0d8382ae
JW
422 # This is used for the pmic on H3
423 default y if SY8106A_POWER
0878a8a7 424 select CMD_I2C
9d082687
JW
425 ---help---
426 Set this to y to enable the I2C controller which is part of the PRCM.
0d8382ae 427endif
9d082687 428
6c739c5d
PK
429if MACH_SUN7I
430config I2C4_ENABLE
431 bool "Enable I2C/TWI controller 4"
432 default n
0878a8a7 433 select CMD_I2C
6c739c5d
PK
434 ---help---
435 See I2C0_ENABLE help text.
436endif
437
2fcf033d 438config AXP_GPIO
ab65006b 439 bool "Enable support for gpio-s on axp PMICs"
2fcf033d
HG
440 default n
441 ---help---
442 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
443
7f2c521f 444config VIDEO
ab65006b 445 bool "Enable graphical uboot console on HDMI, LCD or VGA"
fa855d3d 446 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
7f2c521f
LV
447 default y
448 ---help---
2dae800f
HG
449 Say Y here to add support for using a cfb console on the HDMI, LCD
450 or VGA output found on most sunxi devices. See doc/README.video for
451 info on how to select the video output and mode.
452
2fbf091a 453config VIDEO_HDMI
ab65006b 454 bool "HDMI output support"
2fbf091a
HG
455 depends on VIDEO && !MACH_SUN8I
456 default y
457 ---help---
458 Say Y here to add support for outputting video over HDMI.
459
d9786d23 460config VIDEO_VGA
ab65006b 461 bool "VGA output support"
d9786d23
HG
462 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
463 default n
464 ---help---
465 Say Y here to add support for outputting video over VGA.
466
e2bbdfb1 467config VIDEO_VGA_VIA_LCD
ab65006b 468 bool "VGA via LCD controller support"
2583d5b1 469 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
e2bbdfb1
HG
470 default n
471 ---help---
472 Say Y here to add support for external DACs connected to the parallel
473 LCD interface driving a VGA connector, such as found on the
474 Olimex A13 boards.
475
fb75d972 476config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
ab65006b 477 bool "Force sync active high for VGA via LCD controller support"
fb75d972
HG
478 depends on VIDEO_VGA_VIA_LCD
479 default n
480 ---help---
481 Say Y here if you've a board which uses opendrain drivers for the vga
482 hsync and vsync signals. Opendrain drivers cannot generate steep enough
483 positive edges for a stable video output, so on boards with opendrain
484 drivers the sync signals must always be active high.
485
507e27df
CYT
486config VIDEO_VGA_EXTERNAL_DAC_EN
487 string "LCD panel power enable pin"
488 depends on VIDEO_VGA_VIA_LCD
489 default ""
490 ---help---
491 Set the enable pin for the external VGA DAC. This takes a string in the
492 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
493
39920c81 494config VIDEO_COMPOSITE
ab65006b 495 bool "Composite video output support"
39920c81
HG
496 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
497 default n
498 ---help---
499 Say Y here to add support for outputting composite video.
500
2dae800f
HG
501config VIDEO_LCD_MODE
502 string "LCD panel timing details"
503 depends on VIDEO
504 default ""
505 ---help---
506 LCD panel timing details string, leave empty if there is no LCD panel.
507 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
508 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
8addd3ed 509 Also see: http://linux-sunxi.org/LCD
2dae800f 510
6515032e
HG
511config VIDEO_LCD_DCLK_PHASE
512 int "LCD panel display clock phase"
513 depends on VIDEO
514 default 1
515 ---help---
516 Select LCD panel display clock phase shift, range 0-3.
517
2dae800f
HG
518config VIDEO_LCD_POWER
519 string "LCD panel power enable pin"
520 depends on VIDEO
521 default ""
522 ---help---
523 Set the power enable pin for the LCD panel. This takes a string in the
524 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
525
242e3d89
HG
526config VIDEO_LCD_RESET
527 string "LCD panel reset pin"
528 depends on VIDEO
529 default ""
530 ---help---
531 Set the reset pin for the LCD panel. This takes a string in the format
532 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
533
2dae800f
HG
534config VIDEO_LCD_BL_EN
535 string "LCD panel backlight enable pin"
536 depends on VIDEO
537 default ""
538 ---help---
539 Set the backlight enable pin for the LCD panel. This takes a string in the
540 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
541 port H.
542
543config VIDEO_LCD_BL_PWM
544 string "LCD panel backlight pwm pin"
545 depends on VIDEO
546 default ""
547 ---help---
548 Set the backlight pwm pin for the LCD panel. This takes a string in the
549 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
7f2c521f 550
a7403ae8
HG
551config VIDEO_LCD_BL_PWM_ACTIVE_LOW
552 bool "LCD panel backlight pwm is inverted"
553 depends on VIDEO
554 default y
555 ---help---
556 Set this if the backlight pwm output is active low.
557
55410089
HG
558config VIDEO_LCD_PANEL_I2C
559 bool "LCD panel needs to be configured via i2c"
560 depends on VIDEO
1fc42018 561 default n
0878a8a7 562 select CMD_I2C
55410089
HG
563 ---help---
564 Say y here if the LCD panel needs to be configured via i2c. This
565 will add a bitbang i2c controller using gpios to talk to the LCD.
566
567config VIDEO_LCD_PANEL_I2C_SDA
568 string "LCD panel i2c interface SDA pin"
569 depends on VIDEO_LCD_PANEL_I2C
570 default "PG12"
571 ---help---
572 Set the SDA pin for the LCD i2c interface. This takes a string in the
573 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
574
575config VIDEO_LCD_PANEL_I2C_SCL
576 string "LCD panel i2c interface SCL pin"
577 depends on VIDEO_LCD_PANEL_I2C
578 default "PG10"
579 ---help---
580 Set the SCL pin for the LCD i2c interface. This takes a string in the
581 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
582
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583
584# Note only one of these may be selected at a time! But hidden choices are
585# not supported by Kconfig
586config VIDEO_LCD_IF_PARALLEL
587 bool
588
589config VIDEO_LCD_IF_LVDS
590 bool
591
592
593choice
594 prompt "LCD panel support"
595 depends on VIDEO
596 ---help---
597 Select which type of LCD panel to support.
598
599config VIDEO_LCD_PANEL_PARALLEL
600 bool "Generic parallel interface LCD panel"
601 select VIDEO_LCD_IF_PARALLEL
602
603config VIDEO_LCD_PANEL_LVDS
604 bool "Generic lvds interface LCD panel"
605 select VIDEO_LCD_IF_LVDS
606
97ece830
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607config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
608 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
609 select VIDEO_LCD_SSD2828
610 select VIDEO_LCD_IF_PARALLEL
611 ---help---
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612 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
613
614config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
615 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
616 select VIDEO_LCD_ANX9804
617 select VIDEO_LCD_IF_PARALLEL
618 select VIDEO_LCD_PANEL_I2C
619 ---help---
620 Select this for eDP LCD panels with 4 lanes running at 1.62G,
621 connected via an ANX9804 bridge chip.
97ece830 622
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623config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
624 bool "Hitachi tx18d42vm LCD panel"
625 select VIDEO_LCD_HITACHI_TX18D42VM
626 select VIDEO_LCD_IF_LVDS
627 ---help---
628 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
629
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630config VIDEO_LCD_TL059WV5C0
631 bool "tl059wv5c0 LCD panel"
632 select VIDEO_LCD_PANEL_I2C
633 select VIDEO_LCD_IF_PARALLEL
634 ---help---
635 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
636 Aigo M60/M608/M606 tablets.
637
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638endchoice
639
640
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641config GMAC_TX_DELAY
642 int "GMAC Transmit Clock Delay Chain"
643 default 0
644 ---help---
645 Set the GMAC Transmit Clock Delay Chain value.
646
ff42d107 647config SPL_STACK_R_ADDR
d96ebc46 648 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
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649 default 0x2fe00000 if MACH_SUN9I
650
dd84058d 651endif